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arm64: dts: imx8mp: Fix pgc_mlmix location

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[ Upstream commit 106f68fc9d ]

The pgc_mlmix shows a power-domain@24, but the reg value is
IMX8MP_POWER_DOMAIN_MLMIX which is set to 4.

The stuff after the @ symbol should match the stuff referenced
by 'reg' so reorder the pgc_mlmix so it to appear as power-domain@4.

Fixes: 834464c850 ("arm64: dts: imx8mp: add mlmix power domain")
Fixes: 4bedc468b7 ("arm64: dts: imx8mp: Add NPU Node")
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Adam Ford 2024-06-17 17:39:51 -05:00 committed by Greg Kroah-Hartman
parent 1beddcda55
commit 0150dbc01d
1 changed files with 17 additions and 17 deletions
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34
arch/arm64/boot/dts/freescale/imx8mp.dtsi
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@ -785,6 +785,23 @@
reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>; reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>;
}; };
pgc_mlmix: power-domain@4 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_MLMIX>;
clocks = <&clk IMX8MP_CLK_ML_AXI>,
<&clk IMX8MP_CLK_ML_AHB>,
<&clk IMX8MP_CLK_NPU_ROOT>;
assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>,
<&clk IMX8MP_CLK_ML_AXI>,
<&clk IMX8MP_CLK_ML_AHB>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
<&clk IMX8MP_SYS_PLL1_800M>,
<&clk IMX8MP_SYS_PLL1_800M>;
assigned-clock-rates = <800000000>,
<800000000>,
<300000000>;
};
pgc_audio: power-domain@5 { pgc_audio: power-domain@5 {
#power-domain-cells = <0>; #power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_AUDIOMIX>; reg = <IMX8MP_POWER_DOMAIN_AUDIOMIX>;
@ -879,23 +896,6 @@
reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>; reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>;
clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
}; };
pgc_mlmix: power-domain@24 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_MLMIX>;
clocks = <&clk IMX8MP_CLK_ML_AXI>,
<&clk IMX8MP_CLK_ML_AHB>,
<&clk IMX8MP_CLK_NPU_ROOT>;
assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>,
<&clk IMX8MP_CLK_ML_AXI>,
<&clk IMX8MP_CLK_ML_AHB>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
<&clk IMX8MP_SYS_PLL1_800M>,
<&clk IMX8MP_SYS_PLL1_800M>;
assigned-clock-rates = <800000000>,
<800000000>,
<300000000>;
};
}; };
}; };
}; };