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clk: at91: sama7g5: Allocate only the needed amount of memory for PLLs
[ Upstream commit2d6e9ee7cb
] The maximum number of PLL components on SAMA7G5 is 3 (one fractional part and 2 dividers). Allocate the needed amount of memory for sama7g5_plls 2d array. Previous code used to allocate 7 array entries for each PLL. While at it, replace 3 with PLL_COMPID_MAX in the loop which parses the sama7g5_plls 2d array. Fixes:cb783bbbcf
("clk: at91: sama7g5: add clock support for sama7g5") Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20240714141315.19480-1-claudiu.beznea@tuxon.dev Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -66,6 +66,7 @@ enum pll_component_id {
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PLL_COMPID_FRAC,
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PLL_COMPID_DIV0,
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PLL_COMPID_DIV1,
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PLL_COMPID_MAX,
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};
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/*
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@ -165,7 +166,7 @@ static struct sama7g5_pll {
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u8 t;
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u8 eid;
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u8 safe_div;
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} sama7g5_plls[][PLL_ID_MAX] = {
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} sama7g5_plls[][PLL_COMPID_MAX] = {
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[PLL_ID_CPU] = {
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[PLL_COMPID_FRAC] = {
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.n = "cpupll_fracck",
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@ -1038,7 +1039,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
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sama7g5_pmc->chws[PMC_MAIN] = hw;
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for (i = 0; i < PLL_ID_MAX; i++) {
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for (j = 0; j < 3; j++) {
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for (j = 0; j < PLL_COMPID_MAX; j++) {
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struct clk_hw *parent_hw;
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if (!sama7g5_plls[i][j].n)
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