LF-13778-4: clk: imx91: Add IMX91_CLK_SPDIF_IPG clock

The IMX91_CLK_SPDIF_GATE also controls the gate of IPG clock
and root clock, need to define them separately.
Otherwise disabling IMX91_CLK_SPDIF_GATE in driver will cause
IPG clock is disabled, then register accessing fail.

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Chancel Liu <chancel.liu@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
This commit is contained in:
Shengjiu Wang 2024-11-01 11:48:11 +08:00 committed by Jason Liu
parent 282d80a360
commit 128a564a8a

View File

@ -34,6 +34,7 @@ static u32 share_count_sai2;
static u32 share_count_sai3;
static u32 share_count_mub;
static u32 share_count_pdm;
static u32 share_count_spdif;
static const char * const a55_core_sels[] = {"a55_alt", "arm_pll"};
static const char *parent_names[MAX_SEL][4] = {
@ -232,7 +233,8 @@ static const struct imx91_clk_ccgr {
{ IMX91_CLK_MQS1_GATE, "mqs1", "sai1_root", 0x9b00, },
{ IMX91_CLK_MQS2_GATE, "mqs2", "sai3_root", 0x9b40, },
{ IMX91_CLK_AUD_XCVR_GATE, "aud_xcvr", "audio_xcvr_root", 0x9b80, },
{ IMX91_CLK_SPDIF_GATE, "spdif", "spdif_root", 0x9c00, },
{ IMX91_CLK_SPDIF_IPG, "spdif_ipg_clk", "bus_wakeup_root", 0x9c00, 0, &share_count_spdif},
{ IMX91_CLK_SPDIF_GATE, "spdif", "spdif_root", 0x9c00, 0, &share_count_spdif},
{ IMX91_CLK_HSIO_32K_GATE, "hsio_32k", "osc_32k", 0x9dc0, CLK_IGNORE_UNUSED, },
{ IMX91_CLK_ENET2_REGULAR_GATE, "enet2_regular", "wakeup_axi_root", 0x9e00, CLK_IGNORE_UNUSED, },
{ IMX91_CLK_ENET1_QOS_TSN_GATE, "enet1_qos_tsn", "wakeup_axi_root", 0x9e40, CLK_IGNORE_UNUSED, },