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LF-13778-4: clk: imx91: Add IMX91_CLK_SPDIF_IPG clock
The IMX91_CLK_SPDIF_GATE also controls the gate of IPG clock and root clock, need to define them separately. Otherwise disabling IMX91_CLK_SPDIF_GATE in driver will cause IPG clock is disabled, then register accessing fail. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Chancel Liu <chancel.liu@nxp.com> Acked-by: Jason Liu <jason.hui.liu@nxp.com>
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@ -34,6 +34,7 @@ static u32 share_count_sai2;
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static u32 share_count_sai3;
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static u32 share_count_mub;
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static u32 share_count_pdm;
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static u32 share_count_spdif;
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static const char * const a55_core_sels[] = {"a55_alt", "arm_pll"};
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static const char *parent_names[MAX_SEL][4] = {
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@ -232,7 +233,8 @@ static const struct imx91_clk_ccgr {
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{ IMX91_CLK_MQS1_GATE, "mqs1", "sai1_root", 0x9b00, },
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{ IMX91_CLK_MQS2_GATE, "mqs2", "sai3_root", 0x9b40, },
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{ IMX91_CLK_AUD_XCVR_GATE, "aud_xcvr", "audio_xcvr_root", 0x9b80, },
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{ IMX91_CLK_SPDIF_GATE, "spdif", "spdif_root", 0x9c00, },
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{ IMX91_CLK_SPDIF_IPG, "spdif_ipg_clk", "bus_wakeup_root", 0x9c00, 0, &share_count_spdif},
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{ IMX91_CLK_SPDIF_GATE, "spdif", "spdif_root", 0x9c00, 0, &share_count_spdif},
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{ IMX91_CLK_HSIO_32K_GATE, "hsio_32k", "osc_32k", 0x9dc0, CLK_IGNORE_UNUSED, },
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{ IMX91_CLK_ENET2_REGULAR_GATE, "enet2_regular", "wakeup_axi_root", 0x9e00, CLK_IGNORE_UNUSED, },
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{ IMX91_CLK_ENET1_QOS_TSN_GATE, "enet1_qos_tsn", "wakeup_axi_root", 0x9e40, CLK_IGNORE_UNUSED, },
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