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LF-4887-6 drm/imx: lcdif: Add MPU interface(8080 mode) support
This patch adds MPU interface(8080 mode) support in the LCDIF driver so that LCDIF may send frames to the sec-dsim MIPI DSI controller embedded in i.MX8mm/mn via that interface. From the MIPI DSI controller perspective, the input interface is called S-i80(Synchronous i80 Interface). The general idea is to leverage the self refresh(SR) helpers offered by the DRM core to make the external display device enter self refresh mode and hence disable LCDIF when appropriate. The relevant DRM connectors' conn_state->self_refresh_aware flags are inspected to determine whether to use MPU interface or DOTCLK interface(also called RGB interface). Since LCDIF will be disabled when the self refresh is active and the data is transferred at modest rate, there are below known limitations: 1) The cur_frame_done interrupt comes at a lower frequency than the display vsync signal frequency due to the low data transfer rate. So, vblank events cannot reflect the real vsync pulses of the external display. 2) Screen tearing phenomenon can be seen, because the frame update is asynchronous to the external display self refresh and the LCDIF controller does not support the 'Tearing Effect' mechanism. 3) The fbdev emulation and boot logo can not be updated onto screen in time, because the external display often enters self refresh mode at those stages. The boot logo will show up until the next time when frame is sent to the external display via the MPU interface, e.g., when the next framebuffer pan display operation is done after the logo is ready in framebuffer. Like the below command line, writing to the framebuffer sys node 'pan' frequently at background may make the framebuffer emulation be a bit responsive. while true; do echo 0,0 > /sys/class/graphics/fb0/pan; sleep 1; done & Cc: Sandor Yu <Sandor.yu@nxp.com> Cc: Wujian sun <wujian.sun_1@nxp.com> Reviewed-by: Sandor Yu <Sandor.yu@nxp.com> Signed-off-by: Liu Ying <victor.liu@nxp.com>
This commit is contained in:
Liu Ying
Dong Aisheng
parent
52e179861e
commit
13c71ee35e
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@ -1,5 +1,5 @@
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/*
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* Copyright 2018 NXP
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* Copyright 2018,2021 NXP
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -22,7 +22,9 @@
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#include <drm/drm_atomic.h>
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#include <drm/drm_edid.h>
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#include <drm/drm_vblank.h>
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_self_refresh_helper.h>
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#include <video/imx-lcdif.h>
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#include <video/videomode.h>
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@ -159,6 +161,7 @@ static void lcdif_crtc_atomic_enable(struct drm_crtc *crtc,
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struct drm_display_mode *mode = &crtc->state->adjusted_mode;
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struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc->state);
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struct videomode vm;
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bool use_i80 = lcdif_drm_connector_is_self_refresh_aware(state);
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drm_display_mode_to_videomode(mode, &vm);
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@ -174,7 +177,7 @@ static void lcdif_crtc_atomic_enable(struct drm_crtc *crtc,
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pm_runtime_get_sync(lcdif_crtc->dev->parent);
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lcdif_set_mode(lcdif, &vm);
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lcdif_set_mode(lcdif, &vm, use_i80);
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/* config LCDIF output bus format */
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lcdif_set_bus_fmt(lcdif, imx_crtc_state->bus_format);
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@ -188,8 +191,14 @@ static void lcdif_crtc_atomic_enable(struct drm_crtc *crtc,
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static void lcdif_crtc_atomic_disable(struct drm_crtc *crtc,
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struct drm_atomic_state *state)
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{
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struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,
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crtc);
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struct lcdif_crtc *lcdif_crtc = to_lcdif_crtc(crtc);
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struct lcdif_soc *lcdif = dev_get_drvdata(lcdif_crtc->dev->parent);
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bool use_i80 = lcdif_drm_connector_is_self_refresh_aware(state);
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if (old_crtc_state->self_refresh_active)
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return;
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spin_lock_irq(&crtc->dev->event_lock);
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if (crtc->state->event) {
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@ -200,7 +209,7 @@ static void lcdif_crtc_atomic_disable(struct drm_crtc *crtc,
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drm_crtc_vblank_off(crtc);
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lcdif_disable_controller(lcdif);
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lcdif_disable_controller(lcdif, use_i80);
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pm_runtime_put(lcdif_crtc->dev->parent);
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}
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@ -337,6 +346,13 @@ static int lcdif_crtc_init(struct lcdif_crtc *lcdif_crtc,
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disable_irq(lcdif_crtc->vbl_irq);
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ret = drm_self_refresh_helper_init(&lcdif_crtc->base);
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if (ret) {
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dev_err(lcdif_crtc->dev,
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"failed to init self refresh helper: %d\n", ret);
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goto primary_plane_deinit;
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}
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return 0;
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primary_plane_deinit:
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@ -380,6 +396,8 @@ static void lcdif_crtc_unbind(struct device *dev, struct device *master,
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struct drm_device *drm = data;
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struct lcdif_crtc *lcdif_crtc = dev_get_drvdata(dev);
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drm_self_refresh_helper_cleanup(&lcdif_crtc->base);
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lcdif_plane_deinit(drm, lcdif_crtc->plane[0]);
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}
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@ -1,5 +1,5 @@
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/*
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* Copyright 2018 NXP
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* Copyright 2018,2021 NXP
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -15,7 +15,25 @@
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#ifndef __LCDIF_KMS_H
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#define __LCDIF_KMS_H
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#include <drm/drm_atomic.h>
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#include <drm/drm_connector.h>
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extern const struct drm_mode_config_funcs lcdif_drm_mode_config_funcs;
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extern struct drm_mode_config_helper_funcs lcdif_drm_mode_config_helpers;
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static inline bool
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lcdif_drm_connector_is_self_refresh_aware(struct drm_atomic_state *state)
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{
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struct drm_connector *conn;
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struct drm_connector_state *conn_state;
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int i;
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for_each_new_connector_in_state(state, conn, conn_state, i) {
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if (conn_state->self_refresh_aware)
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return true;
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}
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return false;
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}
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#endif
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@ -1,5 +1,5 @@
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/*
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* Copyright 2018 NXP
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* Copyright 2018,2021 NXP
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -27,6 +27,7 @@
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#include <video/imx-lcdif.h>
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#include "lcdif-plane.h"
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#include "lcdif-kms.h"
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static uint32_t lcdif_pixel_formats[] = {
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DRM_FORMAT_XRGB8888,
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@ -55,6 +56,7 @@ static int lcdif_plane_atomic_check(struct drm_plane *plane,
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struct drm_crtc_state *crtc_state;
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struct drm_display_mode *mode;
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struct drm_rect clip = { 0 };
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bool use_i80;
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/* 'fb' should also be NULL which has been checked in
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* the core sanity check function 'drm_atomic_plane_check()'
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@ -98,6 +100,17 @@ static int lcdif_plane_atomic_check(struct drm_plane *plane,
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crtc_state->mode_changed = true;
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}
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/* Add affected connectors to check if we use i80 mode or not. */
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ret = drm_atomic_add_affected_connectors(state, plane_state->crtc);
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if (ret)
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return ret;
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use_i80 = lcdif_drm_connector_is_self_refresh_aware(state);
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/* Do not support cropping in i80 mode. */
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if (use_i80 && (plane_state->src_w >> 16 != fb->width))
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return -EINVAL;
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return 0;
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}
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@ -112,6 +125,7 @@ static void lcdif_plane_atomic_update(struct drm_plane *plane,
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struct drm_gem_dma_object *gem_obj = NULL;
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u32 fb_addr, src_off, src_w, fb_idx, cpp, stride;
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bool crop;
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bool use_i80 = lcdif_drm_connector_is_self_refresh_aware(state);
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/* plane and crtc is disabling */
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if (!fb)
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@ -135,7 +149,7 @@ static void lcdif_plane_atomic_update(struct drm_plane *plane,
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return;
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}
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lcdif_set_fb_addr(lcdif, fb_idx, fb_addr);
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lcdif_set_fb_addr(lcdif, fb_idx, fb_addr, use_i80);
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/* Config pixel format and horizontal cropping
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* if CRTC needs a full modeset which needs to
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@ -154,7 +168,9 @@ static void lcdif_plane_atomic_update(struct drm_plane *plane,
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crop = src_w != stride ? true : false;
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lcdif_set_fb_hcrop(lcdif, src_w, stride, crop);
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lcdif_enable_controller(lcdif);
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lcdif_enable_controller(lcdif, use_i80);
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} else if (use_i80) {
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lcdif_enable_controller(lcdif, use_i80);
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}
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}
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@ -1,5 +1,5 @@
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/*
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* Copyright 2018 NXP
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* Copyright 2018,2021 NXP
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -360,12 +360,15 @@ void lcdif_set_bus_fmt(struct lcdif_soc *lcdif, u32 bus_format)
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}
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EXPORT_SYMBOL(lcdif_set_bus_fmt);
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void lcdif_set_fb_addr(struct lcdif_soc *lcdif, int id, u32 addr)
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void lcdif_set_fb_addr(struct lcdif_soc *lcdif, int id, u32 addr, bool use_i80)
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{
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switch (id) {
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case 0:
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/* primary plane */
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writel(addr, lcdif->base + LCDIF_NEXT_BUF);
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if (use_i80)
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writel(addr, lcdif->base + LCDIF_CUR_BUF);
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else
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writel(addr, lcdif->base + LCDIF_NEXT_BUF);
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break;
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default:
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/* TODO: add overlay support */
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@ -432,7 +435,8 @@ void lcdif_set_fb_hcrop(struct lcdif_soc *lcdif, u32 src_w,
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EXPORT_SYMBOL(lcdif_set_fb_hcrop);
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void lcdif_set_mode(struct lcdif_soc *lcdif, struct videomode *vmode)
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void lcdif_set_mode(struct lcdif_soc *lcdif, struct videomode *vmode,
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bool use_i80)
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{
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const struct of_device_id *of_id =
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of_match_device(imx_lcdif_dt_ids, lcdif->dev);
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@ -457,6 +461,12 @@ void lcdif_set_mode(struct lcdif_soc *lcdif, struct videomode *vmode)
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TRANSFER_COUNT_SET_HCOUNT(vmode->hactive),
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lcdif->base + LCDIF_TRANSFER_COUNT);
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if (use_i80) {
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/* use MPU 8080 mode */
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writel(CTRL1_MODE86, lcdif->base + LCDIF_CTRL1 + REG_CLR);
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return;
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}
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vdctrl0 = VDCTRL0_ENABLE_PRESENT |
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VDCTRL0_VSYNC_PERIOD_UNIT |
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VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
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@ -514,20 +524,36 @@ void lcdif_set_mode(struct lcdif_soc *lcdif, struct videomode *vmode)
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}
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EXPORT_SYMBOL(lcdif_set_mode);
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void lcdif_enable_controller(struct lcdif_soc *lcdif)
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void lcdif_enable_controller(struct lcdif_soc *lcdif, bool use_i80)
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{
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u32 ctrl2, vdctrl4;
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u32 ctrl2, vdctrl4, timing;
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ctrl2 = readl(lcdif->base + LCDIF_CTRL2);
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vdctrl4 = readl(lcdif->base + LCDIF_VDCTRL4);
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ctrl2 &= ~CTRL2_OUTSTANDING_REQS(0x7);
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ctrl2 |= CTRL2_OUTSTANDING_REQS(REQ_16);
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ctrl2 |= CTRL2_OUTSTANDING_REQS(use_i80 ? REQ_8 : REQ_16);
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writel(ctrl2, lcdif->base + LCDIF_CTRL2);
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/* Continous dotclock mode */
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writel(CTRL_BYPASS_COUNT | CTRL_DOTCLK_MODE,
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lcdif->base + LCDIF_CTRL + REG_SET);
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if (use_i80) {
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/* MPU 8080 write mode */
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writel(CTRL_DATA_SELECT, lcdif->base + LCDIF_CTRL + REG_SET);
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writel(CTRL_READ_WRITEB, lcdif->base + LCDIF_CTRL + REG_CLR);
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writel(CTRL_BYPASS_COUNT, lcdif->base + LCDIF_CTRL + REG_CLR);
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writel(CTRL_DVI_MODE | CTRL_VSYNC_MODE | CTRL_DOTCLK_MODE,
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lcdif->base + LCDIF_CTRL + REG_CLR);
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writel(CTRL1_COMBINE_MPU_WR_STRB,
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lcdif->base + LCDIF_CTRL1 + REG_CLR);
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timing = TIMING_CMD_HOLD(2) | TIMING_CMD_SETUP(1) |
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TIMING_DATA_HOLD(2) | TIMING_DATA_SETUP(1);
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writel(timing, lcdif->base + LCDIF_TIMING);
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} else {
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/* Continuous dotclock mode */
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writel(CTRL_BYPASS_COUNT | CTRL_DOTCLK_MODE,
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lcdif->base + LCDIF_CTRL + REG_SET);
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}
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/* enable the SYNC signals first, then the DMA engine */
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vdctrl4 |= VDCTRL4_SYNC_SIGNALS_ON;
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@ -543,18 +569,21 @@ void lcdif_enable_controller(struct lcdif_soc *lcdif)
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}
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EXPORT_SYMBOL(lcdif_enable_controller);
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void lcdif_disable_controller(struct lcdif_soc *lcdif)
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void lcdif_disable_controller(struct lcdif_soc *lcdif, bool use_i80)
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{
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int ret;
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u32 ctrl, vdctrl4;
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writel(CTRL_RUN, lcdif->base + LCDIF_CTRL + REG_CLR);
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writel(CTRL_DOTCLK_MODE, lcdif->base + LCDIF_CTRL + REG_CLR);
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ret = readl_poll_timeout(lcdif->base + LCDIF_CTRL, ctrl,
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!(ctrl & CTRL_RUN), 0, 1000);
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if (WARN_ON(ret))
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dev_err(lcdif->dev, "disable lcdif run timeout\n");
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if (!use_i80) {
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writel(CTRL_DOTCLK_MODE, lcdif->base + LCDIF_CTRL + REG_CLR);
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ret = readl_poll_timeout(lcdif->base + LCDIF_CTRL, ctrl,
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!(ctrl & CTRL_RUN), 0, 1000);
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if (WARN_ON(ret))
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dev_err(lcdif->dev, "disable lcdif run timeout\n");
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}
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writel(CTRL_MASTER, lcdif->base + LCDIF_CTRL + REG_CLR);
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@ -1,5 +1,5 @@
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/*
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* Copyright 2018 NXP
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* Copyright 2018,2021 NXP
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -50,8 +50,10 @@
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/* regs bit fields */
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#define CTRL_SFTRST BIT(31)
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#define CTRL_CLKGATE BIT(30)
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#define CTRL_READ_WRITEB BIT(28)
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#define CTRL_SHIFT_DIR(x) REG_PUT((x), 26, 26)
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#define CTRL_SHIFT_NUM(x) REG_PUT((x), 25, 21)
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#define CTRL_DVI_MODE BIT(20)
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#define CTRL_BYPASS_COUNT BIT(19)
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#define CTRL_VSYNC_MODE BIT(18)
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#define CTRL_DOTCLK_MODE BIT(17)
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@ -69,12 +71,14 @@
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#define CTRL_DF24 BIT(1)
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#define CTRL_RUN BIT(0)
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#define CTRL1_COMBINE_MPU_WR_STRB BIT(27)
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#define CTRL1_RECOVERY_ON_UNDERFLOW BIT(24)
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#define CTRL1_FIFO_CLEAR BIT(21)
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#define CTRL1_SET_BYTE_PACKAGING(x) REG_PUT((x), 19, 16)
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#define CTRL1_GET_BYTE_PACKAGING(x) REG_GET((x), 19, 16)
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#define CTRL1_CUR_FRAME_DONE_IRQ_EN BIT(13)
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#define CTRL1_CUR_FRAME_DONE_IRQ BIT(9)
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#define CTRL1_MODE86 BIT(1)
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#define REQ_1 0
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#define REQ_2 1
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@ -91,6 +95,11 @@
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#define TRANSFER_COUNT_SET_HCOUNT(x) ((x) & 0xffff)
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#define TRANSFER_COUNT_GET_HCOUNT(x) ((x) & 0xffff)
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#define TIMING_CMD_HOLD(x) REG_PUT((x), 31, 24)
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#define TIMING_CMD_SETUP(x) REG_PUT((x), 23, 16)
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#define TIMING_DATA_HOLD(x) REG_PUT((x), 15, 8)
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#define TIMING_DATA_SETUP(x) REG_PUT((x), 7, 0)
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#define VDCTRL0_ENABLE_PRESENT BIT(28)
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#define VDCTRL0_VSYNC_ACT_HIGH BIT(27)
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#define VDCTRL0_HSYNC_ACT_HIGH BIT(26)
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@ -1,5 +1,5 @@
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/*
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* Copyright 2018 NXP
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* Copyright 2018,2021 NXP
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -31,12 +31,13 @@ int lcdif_get_bus_fmt_from_pix_fmt(struct lcdif_soc *lcdif,
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uint32_t format);
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int lcdif_set_pix_fmt(struct lcdif_soc *lcdif, u32 format);
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void lcdif_set_bus_fmt(struct lcdif_soc *lcdif, u32 bus_format);
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void lcdif_set_fb_addr(struct lcdif_soc *lcdif, int id, u32 addr);
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void lcdif_set_mode(struct lcdif_soc *lcdif, struct videomode *vmode);
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void lcdif_set_fb_addr(struct lcdif_soc *lcdif, int id, u32 addr, bool use_i80);
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||||
void lcdif_set_mode(struct lcdif_soc *lcdif, struct videomode *vmode,
|
||||
bool use_i80);
|
||||
void lcdif_set_fb_hcrop(struct lcdif_soc *lcdif, u32 src_w,
|
||||
u32 fb_w, bool crop);
|
||||
void lcdif_enable_controller(struct lcdif_soc *lcdif);
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||||
void lcdif_disable_controller(struct lcdif_soc *lcdif);
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||||
void lcdif_enable_controller(struct lcdif_soc *lcdif, bool use_i80);
|
||||
void lcdif_disable_controller(struct lcdif_soc *lcdif, bool use_i80);
|
||||
void lcdif_dump_registers(struct lcdif_soc *lcdif);
|
||||
long lcdif_pix_clk_round_rate(struct lcdif_soc *lcdif,
|
||||
unsigned long rate);
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user