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arm64: probes: Fix simulate_ldr*_literal()
commit50f813e576
upstream. The simulate_ldr_literal() code always loads a 64-bit quantity, and when simulating a 32-bit load into a 'W' register, it discards the most significant 32 bits. For big-endian kernels this means that the relevant bits are discarded, and the value returned is the the subsequent 32 bits in memory (i.e. the value at addr + 4). Additionally, simulate_ldr_literal() and simulate_ldrsw_literal() use a plain C load, which the compiler may tear or elide (e.g. if the target is the zero register). Today this doesn't happen to matter, but it may matter in future if trampoline code uses a LDR (literal) or LDRSW (literal). Update simulate_ldr_literal() and simulate_ldrsw_literal() to use an appropriately-sized READ_ONCE() to perform the access, which avoids these problems. Fixes:39a67d49ba
("arm64: kprobes instruction simulation support") Cc: stable@vger.kernel.org Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Link: https://lore.kernel.org/r/20241008155851.801546-3-mark.rutland@arm.com Signed-off-by: Will Deacon <will@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -171,17 +171,15 @@ simulate_tbz_tbnz(u32 opcode, long addr, struct pt_regs *regs)
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void __kprobes
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simulate_ldr_literal(u32 opcode, long addr, struct pt_regs *regs)
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{
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u64 *load_addr;
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unsigned long load_addr;
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int xn = opcode & 0x1f;
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int disp;
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disp = ldr_displacement(opcode);
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load_addr = (u64 *) (addr + disp);
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load_addr = addr + ldr_displacement(opcode);
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if (opcode & (1 << 30)) /* x0-x30 */
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set_x_reg(regs, xn, *load_addr);
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set_x_reg(regs, xn, READ_ONCE(*(u64 *)load_addr));
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else /* w0-w30 */
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set_w_reg(regs, xn, *load_addr);
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set_w_reg(regs, xn, READ_ONCE(*(u32 *)load_addr));
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instruction_pointer_set(regs, instruction_pointer(regs) + 4);
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}
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@ -189,14 +187,12 @@ simulate_ldr_literal(u32 opcode, long addr, struct pt_regs *regs)
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void __kprobes
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simulate_ldrsw_literal(u32 opcode, long addr, struct pt_regs *regs)
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{
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s32 *load_addr;
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unsigned long load_addr;
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int xn = opcode & 0x1f;
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int disp;
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disp = ldr_displacement(opcode);
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load_addr = (s32 *) (addr + disp);
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load_addr = addr + ldr_displacement(opcode);
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set_x_reg(regs, xn, *load_addr);
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set_x_reg(regs, xn, READ_ONCE(*(s32 *)load_addr));
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instruction_pointer_set(regs, instruction_pointer(regs) + 4);
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}
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