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arm64: dts: imx8mp: Add NPU Node

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[ Upstream commit 4bedc468b7 ]

The NPU is based on the Vivante GC8000 and its power-domain
is controlled my pgc_mlmix.  Since the power-domain uses
some of these clocks, setup the clock parent and rates
inside the power-domain, and add the NPU node.

The data sheet states the CLK_ML_AHB should be 300MHz for
nominal, but 800MHz clock will divide down to 266 instead.
Boards which operate in over-drive mode should update the
clocks on their boards accordingly.  When the driver loads,
the NPU numerates as:

 etnaviv-gpu 38500000.npu: model: GC8000, revision: 8002

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Stable-dep-of: 106f68fc9d ("arm64: dts: imx8mp: Fix pgc_mlmix location")
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Adam Ford 2023-10-22 11:19:10 -05:00 committed by Greg Kroah-Hartman
parent 1667b27562
commit 1beddcda55
1 changed files with 21 additions and 0 deletions
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21
arch/arm64/boot/dts/freescale/imx8mp.dtsi
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@ -886,6 +886,15 @@
clocks = <&clk IMX8MP_CLK_ML_AXI>,
<&clk IMX8MP_CLK_ML_AHB>,
<&clk IMX8MP_CLK_NPU_ROOT>;
assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>,
<&clk IMX8MP_CLK_ML_AXI>,
<&clk IMX8MP_CLK_ML_AHB>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
<&clk IMX8MP_SYS_PLL1_800M>,
<&clk IMX8MP_SYS_PLL1_800M>;
assigned-clock-rates = <800000000>,
<800000000>,
<300000000>;
};
};
};
@ -1970,6 +1979,18 @@
interconnect-names = "g1", "g2", "vc8000e";
};
npu: npu@38500000 {
compatible = "vivante,gc";
reg = <0x38500000 0x200000>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_NPU_ROOT>,
<&clk IMX8MP_CLK_NPU_ROOT>,
<&clk IMX8MP_CLK_ML_AXI>,
<&clk IMX8MP_CLK_ML_AHB>;
clock-names = "core", "shader", "bus", "reg";
power-domains = <&pgc_mlmix>;
};
gic: interrupt-controller@38800000 {
compatible = "arm,gic-v3";
reg = <0x38800000 0x10000>,