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This is the 6.6.51 stable release

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-----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEEZH8oZUiU471FcZm+ONu9yGCSaT4FAmbisF0ACgkQONu9yGCS
 aT5Y8xAAqS/rmrC+/qlFvbtAqK+KXLq9BIGvDHW2QHfCyMpSZ6isehVhh64apHE/
 /XvJ6a+2iPVp5o52iDTUKzbcDr3Jx/QwhS8Xa/HyQQy1rXIPpJNJb8Vuvkn/B2Cq
 cPCfTtfPZUUQTd09uAdBhy5NT8hsT2kSVpmSXDnahn9ih8k0tR40udw5Qf7xpWcf
 HqljbfonLP86mF/SB9m+VhDGF9fekujyb+0iS0OPE+TdvSjKB9ySoeL4PIeTSxrz
 goZdp9ygAYy8Bks825ztbfQszqIwceHU/xZRaUrGfOOk4A5kwTmbdUQu7ooMc+5F
 kbpifbewmY1UGn2KTxgj59xCjQ7HLQe+sqacy0/gALzRSajUNyjLn0n4w3UqaJWb
 pf+gwqHBLgDRfvWctggEdY2ApKgOlM9D7TTpWWB9uv1oR/g3PGfgehZgrMMPgPUw
 EZ8JiwnITfRaRFiH/vSR3aJKRj6qjb4mX3/U8HgGcACtyFfHgtuI7jzhnX36fRNO
 FG38bxSUMrJnlohghfBl6zyaruZBMHVaoQzs6MYZ7qrVvCbt3CHivJdaQ85nw0h7
 YHa2zYFfT0ztyaSMzWq6JatgI7BZfd8PjobhbRZADBBD39KC8aL8XLoDPnpzWMUY
 UDlK8n96gOKo0t8ILDWcIisCVGNogcHJlGppC8Fu7ZyKzYsMhN4=
 =OEL/
 -----END PGP SIGNATURE-----

Merge tag 'v6.6.51' into lf-6.6.y

This is the 6.6.51 stable release

* tag 'v6.6.51': (2369 commits)
  Linux 6.6.51
  Bluetooth: hci_sync: Fix UAF on hci_abort_conn_sync
  Bluetooth: hci_sync: Fix UAF on create_le_conn_complete
  ...

Signed-off-by: Jason Liu <jason.hui.liu@nxp.com>

 Conflicts:
	arch/arm64/boot/dts/freescale/imx8mp.dtsi
	arch/arm64/boot/dts/freescale/imx93.dtsi
	drivers/dma/fsl-edma-common.c
	drivers/dma/fsl-edma-common.h
	drivers/dma/fsl-edma.c
	drivers/irqchip/irq-imx-irqsteer.c
	drivers/perf/fsl_imx9_ddr_perf.c
	drivers/spi/spi-fsl-lpspi.c
	sound/soc/sof/imx/imx8m.c
This commit is contained in:
Jason Liu 2024-09-24 11:32:25 +08:00
commit 239f62168d
2085 changed files with 24226 additions and 13171 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
Documentation/ABI/testing/sysfs-devices-system-cpu
View File

@ -565,7 +565,8 @@ Description: Control Symmetric Multi Threading (SMT)
================ =========================================
If control status is "forceoff" or "notsupported" writes
are rejected.
are rejected. Note that enabling SMT on PowerPC skips
offline cores.
What: /sys/devices/system/cpu/cpuX/power/energy_perf_bias
Date: March 2019

34
Documentation/admin-guide/cifs/usage.rst
View File

@ -722,40 +722,26 @@ Configuration pseudo-files:
======================= =======================================================
SecurityFlags Flags which control security negotiation and
also packet signing. Authentication (may/must)
flags (e.g. for NTLM and/or NTLMv2) may be combined with
flags (e.g. for NTLMv2) may be combined with
the signing flags. Specifying two different password
hashing mechanisms (as "must use") on the other hand
does not make much sense. Default flags are::
0x07007
0x00C5
(NTLM, NTLMv2 and packet signing allowed). The maximum
allowable flags if you want to allow mounts to servers
using weaker password hashes is 0x37037 (lanman,
plaintext, ntlm, ntlmv2, signing allowed). Some
SecurityFlags require the corresponding menuconfig
options to be enabled. Enabling plaintext
authentication currently requires also enabling
lanman authentication in the security flags
because the cifs module only supports sending
laintext passwords using the older lanman dialect
form of the session setup SMB. (e.g. for authentication
using plain text passwords, set the SecurityFlags
to 0x30030)::
(NTLMv2 and packet signing allowed). Some SecurityFlags
may require enabling a corresponding menuconfig option.
may use packet signing 0x00001
must use packet signing 0x01001
may use NTLM (most common password hash) 0x00002
must use NTLM 0x02002
may use NTLMv2 0x00004
must use NTLMv2 0x04004
may use Kerberos security 0x00008
must use Kerberos 0x08008
may use lanman (weak) password hash 0x00010
must use lanman password hash 0x10010
may use plaintext passwords 0x00020
must use plaintext passwords 0x20020
(reserved for future packet encryption) 0x00040
may use Kerberos security (krb5) 0x00008
must use Kerberos 0x08008
may use NTLMSSP 0x00080
must use NTLMSSP 0x80080
seal (packet encryption) 0x00040
must seal 0x40040
cifsFYI If set to non-zero value, additional debug information
will be logged to the system error log. This field

10
Documentation/admin-guide/kernel-parameters.txt
View File

@ -664,12 +664,6 @@
loops can be debugged more effectively on production
systems.
clocksource.max_cswd_read_retries= [KNL]
Number of clocksource_watchdog() retries due to
external delays before the clock will be marked
unstable. Defaults to two retries, that is,
three attempts to read the clock under test.
clocksource.verify_n_cpus= [KNL]
Limit the number of CPUs checked for clocksources
marked with CLOCK_SOURCE_VERIFY_PERCPU that
@ -4655,11 +4649,9 @@
profile= [KNL] Enable kernel profiling via /proc/profile
Format: [<profiletype>,]<number>
Param: <profiletype>: "schedule", "sleep", or "kvm"
Param: <profiletype>: "schedule" or "kvm"
[defaults to kernel profiling]
Param: "schedule" - profile schedule points.
Param: "sleep" - profile D-state sleeping (millisecs).
Requires CONFIG_SCHEDSTATS
Param: "kvm" - profile VM exits.
Param: <number> - step/bucket size as a power of 2 for
statistical time based profiling.

36
Documentation/arch/arm64/silicon-errata.rst
View File

@ -119,32 +119,68 @@ stable kernels.
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-A76 | #1463225 | ARM64_ERRATUM_1463225 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-A76 | #3324349 | ARM64_ERRATUM_3194386 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-A77 | #1508412 | ARM64_ERRATUM_1508412 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-A77 | #3324348 | ARM64_ERRATUM_3194386 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-A78 | #3324344 | ARM64_ERRATUM_3194386 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-A78C | #3324346,3324347| ARM64_ERRATUM_3194386 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-A710 | #2119858 | ARM64_ERRATUM_2119858 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-A710 | #2054223 | ARM64_ERRATUM_2054223 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-A710 | #2224489 | ARM64_ERRATUM_2224489 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-A710 | #3324338 | ARM64_ERRATUM_3194386 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-A715 | #2645198 | ARM64_ERRATUM_2645198 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-A720 | #3456091 | ARM64_ERRATUM_3194386 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-A725 | #3456106 | ARM64_ERRATUM_3194386 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-X1 | #3324344 | ARM64_ERRATUM_3194386 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-X1C | #3324346 | ARM64_ERRATUM_3194386 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-X2 | #2119858 | ARM64_ERRATUM_2119858 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-X2 | #2224489 | ARM64_ERRATUM_2224489 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-X2 | #3324338 | ARM64_ERRATUM_3194386 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-X3 | #3324335 | ARM64_ERRATUM_3194386 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-X4 | #3194386 | ARM64_ERRATUM_3194386 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-X925 | #3324334 | ARM64_ERRATUM_3194386 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Neoverse-N1 | #1349291 | N/A |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Neoverse-N1 | #1542419 | ARM64_ERRATUM_1542419 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Neoverse-N1 | #3324349 | ARM64_ERRATUM_3194386 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Neoverse-N2 | #2139208 | ARM64_ERRATUM_2139208 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Neoverse-N2 | #2067961 | ARM64_ERRATUM_2067961 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Neoverse-N2 | #2253138 | ARM64_ERRATUM_2253138 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Neoverse-N2 | #3324339 | ARM64_ERRATUM_3194386 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Neoverse-V1 | #3324341 | ARM64_ERRATUM_3194386 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Neoverse-V2 | #3324336 | ARM64_ERRATUM_3194386 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Neoverse-V3 | #3312417 | ARM64_ERRATUM_3194386 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | MMU-500 | #841119,826419 | N/A |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | MMU-600 | #1076982,1209401| N/A |

2
Documentation/bpf/map_lpm_trie.rst
View File

@ -17,7 +17,7 @@ significant byte.
LPM tries may be created with a maximum prefix length that is a multiple
of 8, in the range from 8 to 2048. The key used for lookup and update
operations is a ``struct bpf_lpm_trie_key``, extended by
operations is a ``struct bpf_lpm_trie_key_u8``, extended by
``max_prefixlen/8`` bytes.
- For IPv4 addresses the data length is 4 bytes

4
Documentation/cdrom/cdrom-standard.rst
View File

@ -217,7 +217,7 @@ current *struct* is::
int (*media_changed)(struct cdrom_device_info *, int);
int (*tray_move)(struct cdrom_device_info *, int);
int (*lock_door)(struct cdrom_device_info *, int);
int (*select_speed)(struct cdrom_device_info *, int);
int (*select_speed)(struct cdrom_device_info *, unsigned long);
int (*get_last_session) (struct cdrom_device_info *,
struct cdrom_multisession *);
int (*get_mcn)(struct cdrom_device_info *, struct cdrom_mcn *);
@ -396,7 +396,7 @@ action need be taken, and the return value should be 0.
::
int select_speed(struct cdrom_device_info *cdi, int speed)
int select_speed(struct cdrom_device_info *cdi, unsigned long speed)
Some CD-ROM drives are capable of changing their head-speed. There
are several reasons for changing the speed of a CD-ROM drive. Badly

5
Documentation/devicetree/bindings/thermal/thermal-zones.yaml
View File

@ -49,7 +49,10 @@ properties:
to take when the temperature crosses those thresholds.
patternProperties:
"^[a-zA-Z][a-zA-Z0-9\\-]{1,12}-thermal$":
# Node name is limited in size due to Linux kernel requirements - 19
# characters in total (see THERMAL_NAME_LENGTH, including terminating NUL
# byte):
"^[a-zA-Z][a-zA-Z0-9\\-]{1,10}-thermal$":
type: object
description:
Each thermal zone node contains information about how frequently it

6
Documentation/hwmon/corsair-psu.rst
View File

@ -15,11 +15,11 @@ Supported devices:
Corsair HX850i
Corsair HX1000i (Series 2022 and 2023)
Corsair HX1000i (Legacy and Series 2023)
Corsair HX1200i
Corsair HX1200i (Legacy and Series 2023)
Corsair HX1500i (Series 2022 and 2023)
Corsair HX1500i (Legacy and Series 2023)
Corsair RM550i

8
Documentation/kbuild/modules.rst
View File

@ -128,7 +128,7 @@ executed to make module versioning work.
modules_install
Install the external module(s). The default location is
/lib/modules/<kernel_release>/extra/, but a prefix may
/lib/modules/<kernel_release>/updates/, but a prefix may
be added with INSTALL_MOD_PATH (discussed in section 5).
clean
@ -417,7 +417,7 @@ directory:
And external modules are installed in:
/lib/modules/$(KERNELRELEASE)/extra/
/lib/modules/$(KERNELRELEASE)/updates/
5.1 INSTALL_MOD_PATH
--------------------
@ -438,10 +438,10 @@ And external modules are installed in:
-------------------
External modules are by default installed to a directory under
/lib/modules/$(KERNELRELEASE)/extra/, but you may wish to
/lib/modules/$(KERNELRELEASE)/updates/, but you may wish to
locate modules for a specific functionality in a separate
directory. For this purpose, use INSTALL_MOD_DIR to specify an
alternative name to "extra."::
alternative name to "updates."::
$ make INSTALL_MOD_DIR=gandalf -C $KDIR \
M=$PWD modules_install

11
Documentation/locking/hwspinlock.rst
View File

@ -85,6 +85,17 @@ is already free).
Should be called from a process context (might sleep).
::
int hwspin_lock_bust(struct hwspinlock *hwlock, unsigned int id);
After verifying the owner of the hwspinlock, release a previously acquired
hwspinlock; returns 0 on success, or an appropriate error code on failure
(e.g. -EOPNOTSUPP if the bust operation is not defined for the specific
hwspinlock).
Should be called from a process context (might sleep).
::
int hwspin_lock_timeout(struct hwspinlock *hwlock, unsigned int timeout);

9
Documentation/mm/page_table_check.rst
View File

@ -14,7 +14,7 @@ Page table check performs extra verifications at the time when new pages become
accessible from the userspace by getting their page table entries (PTEs PMDs
etc.) added into the table.
In case of detected corruption, the kernel is crashed. There is a small
In case of most detected corruption, the kernel is crashed. There is a small
performance and memory overhead associated with the page table check. Therefore,
it is disabled by default, but can be optionally enabled on systems where the
extra hardening outweighs the performance costs. Also, because page table check
@ -22,6 +22,13 @@ is synchronous, it can help with debugging double map memory corruption issues,
by crashing kernel at the time wrong mapping occurs instead of later which is
often the case with memory corruptions bugs.
It can also be used to do page table entry checks over various flags, dump
warnings when illegal combinations of entry flags are detected. Currently,
userfaultfd is the only user of such to sanity check wr-protect bit against
any writable flags. Illegal flag combinations will not directly cause data
corruption in this case immediately, but that will cause read-only data to
be writable, leading to corrupt when the page content is later modified.
Double mapping detection logic
==============================

2
MAINTAINERS
View File

@ -13732,7 +13732,7 @@ M: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
M: "Paul E. McKenney" <paulmck@kernel.org>
L: linux-kernel@vger.kernel.org
S: Supported
F: arch/powerpc/include/asm/membarrier.h
F: arch/*/include/asm/membarrier.h
F: include/uapi/linux/membarrier.h
F: kernel/sched/membarrier.c

2
Makefile
View File

@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
VERSION = 6
PATCHLEVEL = 6
SUBLEVEL = 36
SUBLEVEL = 51
EXTRAVERSION =
NAME = Hurr durr I'ma ninja sloth

62
arch/arm/boot/dts/allwinner/Makefile
View File

@ -259,68 +259,6 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-v3s-licheepi-zero.dtb \
sun8i-v3s-licheepi-zero-dock.dtb \
sun8i-v40-bananapi-m2-berry.dtb
dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-a23-evb.dtb \
sun8i-a23-gt90h-v4.dtb \
sun8i-a23-inet86dz.dtb \
sun8i-a23-ippo-q8h-v5.dtb \
sun8i-a23-ippo-q8h-v1.2.dtb \
sun8i-a23-polaroid-mid2407pxe03.dtb \
sun8i-a23-polaroid-mid2809pxe04.dtb \
sun8i-a23-q8-tablet.dtb \
sun8i-a33-et-q8-v1.6.dtb \
sun8i-a33-ga10h-v1.1.dtb \
sun8i-a33-inet-d978-rev2.dtb \
sun8i-a33-ippo-q8h-v1.2.dtb \
sun8i-a33-olinuxino.dtb \
sun8i-a33-q8-tablet.dtb \
sun8i-a33-sinlinx-sina33.dtb \
sun8i-a83t-allwinner-h8homlet-v2.dtb \
sun8i-a83t-bananapi-m3.dtb \
sun8i-a83t-cubietruck-plus.dtb \
sun8i-a83t-tbs-a711.dtb \
sun8i-h2-plus-bananapi-m2-zero.dtb \
sun8i-h2-plus-libretech-all-h3-cc.dtb \
sun8i-h2-plus-orangepi-r1.dtb \
sun8i-h2-plus-orangepi-zero.dtb \
sun8i-h3-bananapi-m2-plus.dtb \
sun8i-h3-bananapi-m2-plus-v1.2.dtb \
sun8i-h3-beelink-x2.dtb \
sun8i-h3-libretech-all-h3-cc.dtb \
sun8i-h3-mapleboard-mp130.dtb \
sun8i-h3-nanopi-duo2.dtb \
sun8i-h3-nanopi-m1.dtb\
\
sun8i-h3-nanopi-m1-plus.dtb \
sun8i-h3-nanopi-neo.dtb \
sun8i-h3-nanopi-neo-air.dtb \
sun8i-h3-nanopi-r1.dtb \
sun8i-h3-orangepi-2.dtb \
sun8i-h3-orangepi-lite.dtb \
sun8i-h3-orangepi-one.dtb \
sun8i-h3-orangepi-pc.dtb \
sun8i-h3-orangepi-pc-plus.dtb \
sun8i-h3-orangepi-plus.dtb \
sun8i-h3-orangepi-plus2e.dtb \
sun8i-h3-orangepi-zero-plus2.dtb \
sun8i-h3-rervision-dvk.dtb \
sun8i-h3-zeropi.dtb \
sun8i-h3-emlid-neutis-n5h3-devboard.dtb \
sun8i-r16-bananapi-m2m.dtb \
sun8i-r16-nintendo-nes-classic.dtb \
sun8i-r16-nintendo-super-nes-classic.dtb \
sun8i-r16-parrot.dtb \
sun8i-r40-bananapi-m2-ultra.dtb \
sun8i-r40-oka40i-c.dtb \
sun8i-s3-elimo-initium.dtb \
sun8i-s3-lichee-zero-plus.dtb \
sun8i-s3-pinecube.dtb \
sun8i-t113s-mangopi-mq-r-t113.dtb \
sun8i-t3-cqa3t-bv3.dtb \
sun8i-v3-sl631-imx179.dtb \
sun8i-v3s-licheepi-zero.dtb \
sun8i-v3s-licheepi-zero-dock.dtb \
sun8i-v40-bananapi-m2-berry.dtb
dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
sun9i-a80-cubieboard4.dtb

12
arch/arm/boot/dts/nxp/imx/imx6dl-yapp43-common.dtsi
View File

@ -274,24 +274,24 @@
led@0 {
chan-name = "R";
led-cur = /bits/ 8 <0x20>;
max-cur = /bits/ 8 <0x60>;
led-cur = /bits/ 8 <0x6e>;
max-cur = /bits/ 8 <0xc8>;
reg = <0>;
color = <LED_COLOR_ID_RED>;
};
led@1 {
chan-name = "G";
led-cur = /bits/ 8 <0x20>;
max-cur = /bits/ 8 <0x60>;
led-cur = /bits/ 8 <0xbe>;
max-cur = /bits/ 8 <0xc8>;
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
};
led@2 {
chan-name = "B";
led-cur = /bits/ 8 <0x20>;
max-cur = /bits/ 8 <0x60>;
led-cur = /bits/ 8 <0xbe>;
max-cur = /bits/ 8 <0xc8>;
reg = <2>;
color = <LED_COLOR_ID_BLUE>;
};

23
arch/arm/boot/dts/nxp/imx/imx6q-kontron-samx6i.dtsi
View File

@ -5,31 +5,8 @@
#include "imx6q.dtsi"
#include "imx6qdl-kontron-samx6i.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Kontron SMARC sAMX6i Quad/Dual";
compatible = "kontron,imx6q-samx6i", "fsl,imx6q";
};
/* Quad/Dual SoMs have 3 chip-select signals */
&ecspi4 {
cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>,
<&gpio3 29 GPIO_ACTIVE_LOW>,
<&gpio3 25 GPIO_ACTIVE_LOW>;
};
&pinctrl_ecspi4 {
fsl,pins = <
MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
/* SPI4_IMX_CS2# - connected to internal flash */
MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x1b0b0
/* SPI4_IMX_CS0# - connected to SMARC SPI0_CS0# */
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
/* SPI4_CS3# - connected to SMARC SPI0_CS1# */
MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x1b0b0
>;
};

14
arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi
View File

@ -244,7 +244,8 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi4>;
cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>,
<&gpio3 29 GPIO_ACTIVE_LOW>;
<&gpio3 29 GPIO_ACTIVE_LOW>,
<&gpio3 25 GPIO_ACTIVE_LOW>;
status = "okay";
/* default boot source: workaround #1 for errata ERR006282 */
@ -259,7 +260,7 @@
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
phy-connection-type = "rgmii-id";
phy-handle = <&ethphy>;
mdio {
@ -269,7 +270,7 @@
ethphy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
reset-assert-us = <1000>;
};
};
@ -464,6 +465,8 @@
MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x1b0b0
/* SPI_IMX_CS0# - connected to SMARC SPI0_CS0# */
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
/* SPI4_CS3# - connected to SMARC SPI0_CS1# */
MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x1b0b0
>;
};
@ -516,7 +519,7 @@
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* RST_GBE0_PHY# */
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 /* RST_GBE0_PHY# */
>;
};
@ -729,7 +732,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
wake-up-gpio = <&gpio6 18 GPIO_ACTIVE_HIGH>;
reset-gpio = <&gpio3 13 GPIO_ACTIVE_HIGH>;
reset-gpio = <&gpio3 13 GPIO_ACTIVE_LOW>;
};
/* LCD_BKLT_PWM */
@ -817,5 +820,6 @@
/* CPLD is feeded by watchdog (hardwired) */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog1>;
fsl,ext-reset-output;
status = "okay";
};

1
arch/arm/boot/dts/rockchip/rk3066a.dtsi
View File

@ -123,6 +123,7 @@
pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>;
power-domains = <&power RK3066_PD_VIO>;
rockchip,grf = <&grf>;
#sound-dai-cells = <0>;
status = "disabled";
ports {

1
arch/arm/boot/dts/st/stm32mp151.dtsi
View File

@ -50,6 +50,7 @@
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-parent = <&intc>;
arm,no-tick-in-suspend;
};
clocks {

2
arch/arm/boot/dts/ti/omap/omap3-n900.dts
View File

@ -781,7 +781,7 @@
mount-matrix = "-1", "0", "0",
"0", "1", "0",
"0", "0", "1";
"0", "0", "-1";
};
cam1: camera@3e {

2
arch/arm/include/asm/pgtable.h
View File

@ -158,6 +158,8 @@ extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
#define pgdp_get(pgpd) READ_ONCE(*pgdp)
#define pud_page(pud) pmd_page(__pmd(pud_val(pud)))
#define pud_write(pud) pmd_write(__pmd(pud_val(pud)))

14
arch/arm/include/asm/uaccess.h
View File

@ -133,16 +133,6 @@ extern int __get_user_64t_1(void *);
extern int __get_user_64t_2(void *);
extern int __get_user_64t_4(void *);
#define __GUP_CLOBBER_1 "lr", "cc"
#ifdef CONFIG_CPU_USE_DOMAINS
#define __GUP_CLOBBER_2 "ip", "lr", "cc"
#else
#define __GUP_CLOBBER_2 "lr", "cc"
#endif
#define __GUP_CLOBBER_4 "lr", "cc"
#define __GUP_CLOBBER_32t_8 "lr", "cc"
#define __GUP_CLOBBER_8 "lr", "cc"
#define __get_user_x(__r2, __p, __e, __l, __s) \
__asm__ __volatile__ ( \
__asmeq("%0", "r0") __asmeq("%1", "r2") \
@ -150,7 +140,7 @@ extern int __get_user_64t_4(void *);
"bl __get_user_" #__s \
: "=&r" (__e), "=r" (__r2) \
: "0" (__p), "r" (__l) \
: __GUP_CLOBBER_##__s)
: "ip", "lr", "cc")
/* narrowing a double-word get into a single 32bit word register: */
#ifdef __ARMEB__
@ -172,7 +162,7 @@ extern int __get_user_64t_4(void *);
"bl __get_user_64t_" #__s \
: "=&r" (__e), "=r" (__r2) \
: "0" (__p), "r" (__l) \
: __GUP_CLOBBER_##__s)
: "ip", "lr", "cc")
#else
#define __get_user_x_64t __get_user_x
#endif

3
arch/arm/kernel/perf_callchain.c
View File

@ -85,8 +85,7 @@ static bool
callchain_trace(void *data, unsigned long pc)
{
struct perf_callchain_entry_ctx *entry = data;
perf_callchain_store(entry, pc);
return true;
return perf_callchain_store(entry, pc) == 0;
}
void

2
arch/arm/mach-davinci/pm.c
View File

@ -61,7 +61,7 @@ static void davinci_pm_suspend(void)
/* Configure sleep count in deep sleep register */
val = __raw_readl(pm_config.deepsleep_reg);
val &= ~DEEPSLEEP_SLEEPCOUNT_MASK,
val &= ~DEEPSLEEP_SLEEPCOUNT_MASK;
val |= pm_config.sleepcount;
__raw_writel(val, pm_config.deepsleep_reg);

30
arch/arm/mach-pxa/spitz.c
View File

@ -520,10 +520,8 @@ static struct gpiod_lookup_table spitz_ads7846_gpio_table = {
static struct gpiod_lookup_table spitz_lcdcon_gpio_table = {
.dev_id = "spi2.1",
.table = {
GPIO_LOOKUP("gpio-pxa", SPITZ_GPIO_BACKLIGHT_CONT,
"BL_CONT", GPIO_ACTIVE_LOW),
GPIO_LOOKUP("gpio-pxa", SPITZ_GPIO_BACKLIGHT_ON,
"BL_ON", GPIO_ACTIVE_HIGH),
GPIO_LOOKUP("sharp-scoop.1", 6, "BL_CONT", GPIO_ACTIVE_LOW),
GPIO_LOOKUP("sharp-scoop.1", 7, "BL_ON", GPIO_ACTIVE_HIGH),
{ },
},
};
@ -531,10 +529,8 @@ static struct gpiod_lookup_table spitz_lcdcon_gpio_table = {
static struct gpiod_lookup_table akita_lcdcon_gpio_table = {
.dev_id = "spi2.1",
.table = {
GPIO_LOOKUP("gpio-pxa", AKITA_GPIO_BACKLIGHT_CONT,
"BL_CONT", GPIO_ACTIVE_LOW),
GPIO_LOOKUP("gpio-pxa", AKITA_GPIO_BACKLIGHT_ON,
"BL_ON", GPIO_ACTIVE_HIGH),
GPIO_LOOKUP("i2c-max7310", 3, "BL_ON", GPIO_ACTIVE_HIGH),
GPIO_LOOKUP("i2c-max7310", 4, "BL_CONT", GPIO_ACTIVE_LOW),
{ },
},
};
@ -941,12 +937,9 @@ static inline void spitz_i2c_init(void) {}
static struct gpiod_lookup_table spitz_audio_gpio_table = {
.dev_id = "spitz-audio",
.table = {
GPIO_LOOKUP("sharp-scoop.0", SPITZ_GPIO_MUTE_L - SPITZ_SCP_GPIO_BASE,
"mute-l", GPIO_ACTIVE_HIGH),
GPIO_LOOKUP("sharp-scoop.0", SPITZ_GPIO_MUTE_R - SPITZ_SCP_GPIO_BASE,
"mute-r", GPIO_ACTIVE_HIGH),
GPIO_LOOKUP("sharp-scoop.1", SPITZ_GPIO_MIC_BIAS - SPITZ_SCP2_GPIO_BASE,
"mic", GPIO_ACTIVE_HIGH),
GPIO_LOOKUP("sharp-scoop.0", 3, "mute-l", GPIO_ACTIVE_HIGH),
GPIO_LOOKUP("sharp-scoop.0", 4, "mute-r", GPIO_ACTIVE_HIGH),
GPIO_LOOKUP("sharp-scoop.1", 8, "mic", GPIO_ACTIVE_HIGH),
{ },
},
};
@ -954,12 +947,9 @@ static struct gpiod_lookup_table spitz_audio_gpio_table = {
static struct gpiod_lookup_table akita_audio_gpio_table = {
.dev_id = "spitz-audio",
.table = {
GPIO_LOOKUP("sharp-scoop.0", SPITZ_GPIO_MUTE_L - SPITZ_SCP_GPIO_BASE,
"mute-l", GPIO_ACTIVE_HIGH),
GPIO_LOOKUP("sharp-scoop.0", SPITZ_GPIO_MUTE_R - SPITZ_SCP_GPIO_BASE,
"mute-r", GPIO_ACTIVE_HIGH),
GPIO_LOOKUP("i2c-max7310", AKITA_GPIO_MIC_BIAS - AKITA_IOEXP_GPIO_BASE,
"mic", GPIO_ACTIVE_HIGH),
GPIO_LOOKUP("sharp-scoop.0", 3, "mute-l", GPIO_ACTIVE_HIGH),
GPIO_LOOKUP("sharp-scoop.0", 4, "mute-r", GPIO_ACTIVE_HIGH),
GPIO_LOOKUP("i2c-max7310", 2, "mic", GPIO_ACTIVE_HIGH),
{ },
},
};

38
arch/arm64/Kconfig
View File

@ -1068,6 +1068,44 @@ config ARM64_ERRATUM_3117295
If unsure, say Y.
config ARM64_ERRATUM_3194386
bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing"
default y
help
This option adds the workaround for the following errata:
* ARM Cortex-A76 erratum 3324349
* ARM Cortex-A77 erratum 3324348
* ARM Cortex-A78 erratum 3324344
* ARM Cortex-A78C erratum 3324346
* ARM Cortex-A78C erratum 3324347
* ARM Cortex-A710 erratam 3324338
* ARM Cortex-A720 erratum 3456091
* ARM Cortex-A725 erratum 3456106
* ARM Cortex-X1 erratum 3324344
* ARM Cortex-X1C erratum 3324346
* ARM Cortex-X2 erratum 3324338
* ARM Cortex-X3 erratum 3324335
* ARM Cortex-X4 erratum 3194386
* ARM Cortex-X925 erratum 3324334
* ARM Neoverse-N1 erratum 3324349
* ARM Neoverse N2 erratum 3324339
* ARM Neoverse-V1 erratum 3324341
* ARM Neoverse V2 erratum 3324336
* ARM Neoverse-V3 erratum 3312417
On affected cores "MSR SSBS, #0" instructions may not affect
subsequent speculative instructions, which may permit unexepected
speculative store bypassing.
Work around this problem by placing a Speculation Barrier (SB) or
Instruction Synchronization Barrier (ISB) after kernel changes to
SSBS. The presence of the SSBS special-purpose register is hidden
from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such that userspace
will use the PR_SPEC_STORE_BYPASS prctl to change SSBS.
If unsure, say Y.
config CAVIUM_ERRATUM_22375
bool "Cavium erratum 22375, 24313"
default y

5
arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
View File

@ -215,6 +215,11 @@
#sound-dai-cells = <0>;
status = "disabled";
assigned-clocks = <&clkc CLKID_HDMI_SEL>,
<&clkc CLKID_HDMI>;
assigned-clock-parents = <&xtal>, <0>;
assigned-clock-rates = <0>, <24000000>;
/* VPU VENC Input */
hdmi_tx_venc_port: port@0 {
reg = <0>;

4
arch/arm64/boot/dts/amlogic/meson-g12.dtsi
View File

@ -367,6 +367,10 @@
power-domains = <&pwrc PWRC_G12A_ETH_ID>;
};
&hdmi_tx {
power-domains = <&pwrc PWRC_G12A_VPU_ID>;
};
&vpu {
power-domains = <&pwrc PWRC_G12A_VPU_ID>;
};

10
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
View File

@ -311,10 +311,16 @@
<&reset RESET_HDMI_SYSTEM_RESET>,
<&reset RESET_HDMI_TX>;
reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
clocks = <&clkc CLKID_HDMI_PCLK>,
<&clkc CLKID_CLK81>,
clocks = <&clkc CLKID_HDMI>,
<&clkc CLKID_HDMI_PCLK>,
<&clkc CLKID_GCLK_VENCI_INT0>;
clock-names = "isfr", "iahb", "venci";
power-domains = <&pwrc PWRC_GXBB_VPU_ID>;
assigned-clocks = <&clkc CLKID_HDMI_SEL>,
<&clkc CLKID_HDMI>;
assigned-clock-parents = <&xtal>, <0>;
assigned-clock-rates = <0>, <24000000>;
};
&sysctrl {

10
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
View File

@ -323,10 +323,16 @@
<&reset RESET_HDMI_SYSTEM_RESET>,
<&reset RESET_HDMI_TX>;
reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
clocks = <&clkc CLKID_HDMI_PCLK>,
<&clkc CLKID_CLK81>,
clocks = <&clkc CLKID_HDMI>,
<&clkc CLKID_HDMI_PCLK>,
<&clkc CLKID_GCLK_VENCI_INT0>;
clock-names = "isfr", "iahb", "venci";
power-domains = <&pwrc PWRC_GXBB_VPU_ID>;
assigned-clocks = <&clkc CLKID_HDMI_SEL>,
<&clkc CLKID_HDMI>;
assigned-clock-parents = <&xtal>, <0>;
assigned-clock-rates = <0>, <24000000>;
};
&sysctrl {

8
arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
View File

@ -339,7 +339,7 @@
};
spdifin: audio-controller@400 {
compatible = "amlogic,g12a-spdifin",
compatible = "amlogic,sm1-spdifin",
"amlogic,axg-spdifin";
reg = <0x0 0x400 0x0 0x30>;
#sound-dai-cells = <0>;
@ -353,7 +353,7 @@
};
spdifout_a: audio-controller@480 {
compatible = "amlogic,g12a-spdifout",
compatible = "amlogic,sm1-spdifout",
"amlogic,axg-spdifout";
reg = <0x0 0x480 0x0 0x50>;
#sound-dai-cells = <0>;
@ -518,6 +518,10 @@
"amlogic,meson-gpio-intc";
};
&hdmi_tx {
power-domains = <&pwrc PWRC_SM1_VPU_ID>;
};
&pcie {
power-domains = <&pwrc PWRC_SM1_PCIE_ID>;
};

12
arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts
View File

@ -163,13 +163,12 @@
simple-audio-card,cpu {
sound-dai = <&sai3>;
frame-master;
bitclock-master;
};
simple-audio-card,codec {
sound-dai = <&wm8962>;
clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO1>;
frame-master;
bitclock-master;
};
};
};
@ -381,10 +380,9 @@
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&clk IMX8MP_CLK_SAI3>,
<&clk IMX8MP_AUDIO_PLL2> ;
assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>;
assigned-clock-rates = <12288000>, <361267200>;
assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
assigned-clock-rates = <12288000>;
fsl,sai-mclk-direction-output;
status = "okay";
};

74
arch/arm64/boot/dts/freescale/imx8mp.dtsi
View File

@ -794,6 +794,14 @@
reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>;
};
pgc_mlmix: power-domain@4 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_MLMIX>;
clocks = <&clk IMX8MP_CLK_ML_AXI>,
<&clk IMX8MP_CLK_ML_AHB>,
<&clk IMX8MP_CLK_NPU_ROOT>;
};
pgc_gpumix: power-domain@7 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_GPUMIX>;
@ -818,6 +826,12 @@
power-domains = <&pgc_gpumix>;
};
pgc_vpumix: power-domain@8 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_VPUMIX>;
clocks = <&clk IMX8MP_CLK_VPU_ROOT>;
};
pgc_gpu3d: power-domain@9 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_GPU3D>;
@ -833,7 +847,28 @@
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
};
pgc_hdmimix: power-domains@14 {
pgc_vpu_g1: power-domain@11 {
#power-domain-cells = <0>;
power-domains = <&pgc_vpumix>;
reg = <IMX8MP_POWER_DOMAIN_VPU_G1>;
clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>;
};
pgc_vpu_g2: power-domain@12 {
#power-domain-cells = <0>;
power-domains = <&pgc_vpumix>;
reg = <IMX8MP_POWER_DOMAIN_VPU_G2>;
clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>;
};
pgc_vpu_vc8000e: power-domain@13 {
#power-domain-cells = <0>;
power-domains = <&pgc_vpumix>;
reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>;
clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
};
pgc_hdmimix: power-domain@14 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_HDMIMIX>;
clocks = <&clk IMX8MP_CLK_HDMI_ROOT>,
@ -845,7 +880,7 @@
assigned-clock-rates = <500000000>, <133000000>;
};
pgc_hdmi_phy: power-domains@15 {
pgc_hdmi_phy: power-domain@15 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_HDMI_PHY>;
};
@ -870,41 +905,6 @@
reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>;
clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>;
};
pgc_vpumix: power-domain@19 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_VPUMIX>;
clocks = <&clk IMX8MP_CLK_VPU_ROOT>;
};
pgc_vpu_g1: power-domain@20 {
#power-domain-cells = <0>;
power-domains = <&pgc_vpumix>;
reg = <IMX8MP_POWER_DOMAIN_VPU_G1>;
clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>;
};
pgc_vpu_g2: power-domain@21 {
#power-domain-cells = <0>;
power-domains = <&pgc_vpumix>;
reg = <IMX8MP_POWER_DOMAIN_VPU_G2>;
clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>;
};
pgc_vpu_vc8000e: power-domain@22 {
#power-domain-cells = <0>;
power-domains = <&pgc_vpumix>;
reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>;
clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
};
pgc_mlmix: power-domain@24 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_MLMIX>;
clocks = <&clk IMX8MP_CLK_ML_AXI>,
<&clk IMX8MP_CLK_ML_AHB>,
<&clk IMX8MP_CLK_NPU_ROOT>;
};
};
};
};

2
arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts
View File

@ -437,7 +437,7 @@
pinctrl-0 = <&pinctrl_usdhc2_hs>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
bus-width = <4>;
no-sdio;

2
arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi
View File

@ -19,7 +19,7 @@
linux,cma {
compatible = "shared-dma-pool";
reusable;
alloc-ranges = <0 0x60000000 0 0x40000000>;
alloc-ranges = <0 0x80000000 0 0x40000000>;
size = <0 0x10000000>;
linux,cma-default;
};

2
arch/arm64/boot/dts/freescale/imx93.dtsi
View File

@ -1201,6 +1201,8 @@
fsl,num-tx-queues = <3>;
fsl,num-rx-queues = <3>;
fsl,stop-mode = <&wakeupmix_gpr 0x0c 1>;
nvmem-cells = <&eth_mac1>;
nvmem-cell-names = "mac-address";
status = "disabled";
};

4
arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
View File

@ -318,8 +318,8 @@
/* eMMC is shared pin with parallel NAND */
emmc_pins_default: emmc-pins-default {
mux {
function = "emmc", "emmc_rst";
groups = "emmc";
function = "emmc";
groups = "emmc", "emmc_rst";
};
/* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",

4
arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
View File

@ -244,8 +244,8 @@
/* eMMC is shared pin with parallel NAND */
emmc_pins_default: emmc-pins-default {
mux {
function = "emmc", "emmc_rst";
groups = "emmc";
function = "emmc";
groups = "emmc", "emmc_rst";
};
/* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",

2
arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219.dtsi
View File

@ -28,7 +28,7 @@
dlg,btn-cfg = <50>;
dlg,mic-det-thr = <500>;
dlg,jack-ins-deb = <20>;
dlg,jack-det-rate = "32ms_64ms";
dlg,jack-det-rate = "32_64";
dlg,jack-rem-deb = <1>;
dlg,a-d-btn-thr = <0xa>;

25
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi
View File

@ -156,21 +156,24 @@
vdd18-supply = <&pp1800_mipibrdg>;
vdd33-supply = <&vddio_mipibrdg>;
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
anx7625_in: endpoint {
remote-endpoint = <&dsi_out>;
port@0 {
reg = <0>;
anx7625_in: endpoint {
remote-endpoint = <&dsi_out>;
};
};
};
port@1 {
reg = <1>;
port@1 {
reg = <1>;
anx7625_out: endpoint {
remote-endpoint = <&panel_in>;
anx7625_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};

2
arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
View File

@ -775,7 +775,6 @@
};
pins-rts {
pinmux = <PINMUX_GPIO47__FUNC_URTS1>;
output-enable;
};
pins-cts {
pinmux = <PINMUX_GPIO46__FUNC_UCTS1>;
@ -794,7 +793,6 @@
};
pins-rts {
pinmux = <PINMUX_GPIO47__FUNC_URTS1>;
output-enable;
};
pins-cts {
pinmux = <PINMUX_GPIO46__FUNC_UCTS1>;

1
arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
View File

@ -147,6 +147,7 @@
regulator-boot-on;
gpio = <&pio 127 GPIO_ACTIVE_HIGH>;
vin-supply = <&pp3300_g>;
off-on-delay-us = <500000>;
};
/* separately switched 3.3V power rail */

2
arch/arm64/boot/dts/mediatek/mt8195.dtsi
View File

@ -3395,7 +3395,7 @@
};
};
gpu0-thermal {
gpu-thermal {
polling-delay = <1000>;
polling-delay-passive = <250>;
thermal-sensors = <&lvts_ap MT8195_AP_GPU0>;

1
arch/arm64/boot/dts/qcom/ipq6018.dtsi
View File

@ -579,6 +579,7 @@
clocks = <&xo>;
clock-names = "ref";
tx-fifo-resize;
snps,parkmode-disable-ss-quirk;
snps,is-utmi-l1-suspend;
snps,hird-threshold = /bits/ 8 <0x0>;
snps,dis_u2_susphy_quirk;

2
arch/arm64/boot/dts/qcom/ipq8074.dtsi
View File

@ -641,6 +641,7 @@
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
phys = <&qusb_phy_0>, <&usb0_ssphy>;
phy-names = "usb2-phy", "usb3-phy";
snps,parkmode-disable-ss-quirk;
snps,is-utmi-l1-suspend;
snps,hird-threshold = /bits/ 8 <0x0>;
snps,dis_u2_susphy_quirk;
@ -683,6 +684,7 @@
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
phys = <&qusb_phy_1>, <&usb1_ssphy>;
phy-names = "usb2-phy", "usb3-phy";
snps,parkmode-disable-ss-quirk;
snps,is-utmi-l1-suspend;
snps,hird-threshold = /bits/ 8 <0x0>;
snps,dis_u2_susphy_quirk;

1
arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi
View File

@ -405,7 +405,6 @@
&hsusb_phy1 {
status = "okay";
extcon = <&typec>;
vdda-pll-supply = <&vreg_l12a_1p8>;
vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;

3
arch/arm64/boot/dts/qcom/msm8996.dtsi
View File

@ -2090,7 +2090,7 @@
<&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
freq-table-hz =
<100000000 200000000>,
<0 0>,
<100000000 200000000>,
<0 0>,
<0 0>,
<0 0>,
@ -3082,6 +3082,7 @@
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,is-utmi-l1-suspend;
snps,parkmode-disable-ss-quirk;
tx-fifo-resize;
};
};

37
arch/arm64/boot/dts/qcom/msm8998.dtsi
View File

@ -1588,7 +1588,6 @@
* SoC VDDMX RPM Power Domain in the Adreno driver.
*/
power-domains = <&gpucc GPU_GX_GDSC>;
status = "disabled";
};
gpucc: clock-controller@5065000 {
@ -2160,7 +2159,8 @@
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
phys = <&qusb2phy>, <&usb1_ssphy>;
snps,parkmode-disable-ss-quirk;
phys = <&qusb2phy>, <&usb3phy>;
phy-names = "usb2-phy", "usb3-phy";
snps,has-lpm-erratum;
snps,hird-threshold = /bits/ 8 <0x10>;
@ -2169,33 +2169,26 @@
usb3phy: phy@c010000 {
compatible = "qcom,msm8998-qmp-usb3-phy";
reg = <0x0c010000 0x18c>;
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges;
reg = <0x0c010000 0x1000>;
clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
<&gcc GCC_USB3_CLKREF_CLK>,
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
<&gcc GCC_USB3_CLKREF_CLK>;
clock-names = "aux", "cfg_ahb", "ref";
<&gcc GCC_USB3_PHY_PIPE_CLK>;
clock-names = "aux",
"ref",
"cfg_ahb",
"pipe";
clock-output-names = "usb3_phy_pipe_clk_src";
#clock-cells = <0>;
#phy-cells = <0>;
resets = <&gcc GCC_USB3_PHY_BCR>,
<&gcc GCC_USB3PHY_PHY_BCR>;
reset-names = "phy", "common";
reset-names = "phy",
"phy_phy";
usb1_ssphy: phy@c010200 {
reg = <0xc010200 0x128>,
<0xc010400 0x200>,
<0xc010c00 0x20c>,
<0xc010600 0x128>,
<0xc010800 0x200>;
#phy-cells = <0>;
#clock-cells = <0>;
clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "usb3_phy_pipe_clk_src";
};
status = "disabled";
};
qusb2phy: phy@c012000 {

16
arch/arm64/boot/dts/qcom/qdu1000.dtsi
View File

@ -1452,7 +1452,21 @@
"llcc_broadcast_base",
"multi_channel_register";
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
multi-ch-bit-off = <24 2>;
nvmem-cells = <&multi_chan_ddr>;
nvmem-cell-names = "multi-chan-ddr";
};
sec_qfprom: efuse@221c8000 {
compatible = "qcom,qdu1000-sec-qfprom", "qcom,sec-qfprom";
reg = <0 0x221c8000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
multi_chan_ddr: multi-chan-ddr@12b {
reg = <0x12b 0x1>;
bits = <0 2>;
};
};
};

15
arch/arm64/boot/dts/qcom/qrb4210-rb2.dts
View File

@ -57,6 +57,17 @@
};
};
i2c2_gpio: i2c {
compatible = "i2c-gpio";
sda-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>;
scl-gpios = <&tlmm 7 GPIO_ACTIVE_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
leds {
compatible = "gpio-leds";
@ -187,7 +198,7 @@
};
};
&i2c2 {
&i2c2_gpio {
clock-frequency = <400000>;
status = "okay";
@ -353,6 +364,8 @@
vreg_l9a_1p8: l9 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2000000>;
regulator-always-on;
regulator-boot-on;
};
vreg_l10a_1p8: l10 {

4
arch/arm64/boot/dts/qcom/sa8775p.dtsi
View File

@ -2350,6 +2350,7 @@
phy-names = "serdes";
iommus = <&apps_smmu 0x140 0xf>;
dma-coherent;
snps,tso;
snps,pbl = <32>;
@ -2383,6 +2384,7 @@
phy-names = "serdes";
iommus = <&apps_smmu 0x120 0xf>;
dma-coherent;
snps,tso;
snps,pbl = <32>;
@ -2398,7 +2400,7 @@
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
pcie0: pci@1c00000{

58
arch/arm64/boot/dts/qcom/sc7180.dtsi
View File

@ -15,6 +15,7 @@
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sc7180.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/phy/phy-qcom-qusb2.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/reset/qcom,sdm845-aoss.h>
@ -2795,49 +2796,28 @@
nvmem-cells = <&qusb2p_hstx_trim>;
};
usb_1_qmpphy: phy-wrapper@88e9000 {
usb_1_qmpphy: phy@88e8000 {
compatible = "qcom,sc7180-qmp-usb3-dp-phy";
reg = <0 0x088e9000 0 0x18c>,
<0 0x088e8000 0 0x3c>,
<0 0x088ea000 0 0x18c>;
reg = <0 0x088e8000 0 0x3000>;
status = "disabled";
#address-cells = <2>;
#size-cells = <2>;
ranges;
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
<&gcc GCC_USB3_PRIM_CLKREF_CLK>,
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
clock-names = "aux", "cfg_ahb", "ref", "com_aux";
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
clock-names = "aux",
"ref",
"com_aux",
"usb3_pipe",
"cfg_ahb";
resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
<&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
reset-names = "phy", "common";
usb_1_ssphy: usb3-phy@88e9200 {
reg = <0 0x088e9200 0 0x128>,
<0 0x088e9400 0 0x200>,
<0 0x088e9c00 0 0x218>,
<0 0x088e9600 0 0x128>,
<0 0x088e9800 0 0x200>,
<0 0x088e9a00 0 0x18>;
#clock-cells = <0>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "usb3_phy_pipe_clk_src";
};
dp_phy: dp-phy@88ea200 {
reg = <0 0x088ea200 0 0x200>,
<0 0x088ea400 0 0x200>,
<0 0x088eaa00 0 0x200>,
<0 0x088ea600 0 0x200>,
<0 0x088ea800 0 0x200>;
#clock-cells = <1>;
#phy-cells = <0>;
};
#clock-cells = <1>;
#phy-cells = <1>;
};
pmu@90b6300 {
@ -3001,7 +2981,8 @@
iommus = <&apps_smmu 0x540 0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
snps,parkmode-disable-ss-quirk;
phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
maximum-speed = "super-speed";
};
@ -3307,8 +3288,9 @@
"ctrl_link_iface", "stream_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
phys = <&dp_phy>;
assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
phy-names = "dp";
operating-points-v2 = <&dp_opp_table>;
@ -3365,8 +3347,8 @@
<&gcc GCC_DISP_GPLL0_CLK_SRC>,
<&mdss_dsi0_phy 0>,
<&mdss_dsi0_phy 1>,
<&dp_phy 0>,
<&dp_phy 1>;
<&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
clock-names = "bi_tcxo",
"gcc_disp_gpll0_clk_src",
"dsi0_phy_pll_out_byteclk",

60
arch/arm64/boot/dts/qcom/sc7280.dtsi
View File

@ -18,6 +18,7 @@
#include <dt-bindings/interconnect/qcom,sc7280.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/reset/qcom,sdm845-aoss.h>
#include <dt-bindings/reset/qcom,sdm845-pdc.h>
@ -858,7 +859,7 @@
<&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
<0>, <&pcie1_lane>,
<0>, <0>, <0>,
<&usb_1_ssphy>;
<&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
"pcie_0_pipe_clk", "pcie_1_pipe_clk",
"ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk",
@ -3351,49 +3352,26 @@
resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
};
usb_1_qmpphy: phy-wrapper@88e9000 {
compatible = "qcom,sc7280-qmp-usb3-dp-phy",
"qcom,sm8250-qmp-usb3-dp-phy";
reg = <0 0x088e9000 0 0x200>,
<0 0x088e8000 0 0x40>,
<0 0x088ea000 0 0x200>;
usb_1_qmpphy: phy@88e8000 {
compatible = "qcom,sc7280-qmp-usb3-dp-phy";
reg = <0 0x088e8000 0 0x3000>;
status = "disabled";
#address-cells = <2>;
#size-cells = <2>;
ranges;
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
clock-names = "aux", "ref_clk_src", "com_aux";
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
clock-names = "aux",
"ref",
"com_aux",
"usb3_pipe";
resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
<&gcc GCC_USB3_PHY_PRIM_BCR>;
reset-names = "phy", "common";
usb_1_ssphy: usb3-phy@88e9200 {
reg = <0 0x088e9200 0 0x200>,
<0 0x088e9400 0 0x200>,
<0 0x088e9c00 0 0x400>,
<0 0x088e9600 0 0x200>,
<0 0x088e9800 0 0x200>,
<0 0x088e9a00 0 0x100>;
#clock-cells = <0>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "usb3_phy_pipe_clk_src";
};
dp_phy: dp-phy@88ea200 {
reg = <0 0x088ea200 0 0x200>,
<0 0x088ea400 0 0x200>,
<0 0x088eaa00 0 0x200>,
<0 0x088ea600 0 0x200>,
<0 0x088ea800 0 0x200>;
#phy-cells = <0>;
#clock-cells = <1>;
};
#clock-cells = <1>;
#phy-cells = <1>;
};
usb_2: usb@8cf8800 {
@ -3702,7 +3680,8 @@
iommus = <&apps_smmu 0xe0 0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
snps,parkmode-disable-ss-quirk;
phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
maximum-speed = "super-speed";
};
@ -3807,8 +3786,8 @@
<&gcc GCC_DISP_GPLL0_CLK_SRC>,
<&mdss_dsi_phy 0>,
<&mdss_dsi_phy 1>,
<&dp_phy 0>,
<&dp_phy 1>,
<&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&mdss_edp_phy 0>,
<&mdss_edp_phy 1>;
clock-names = "bi_tcxo",
@ -4144,8 +4123,9 @@
"stream_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
phys = <&dp_phy>;
assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
phy-names = "dp";
operating-points-v2 = <&dp_opp_table>;

39
arch/arm64/boot/dts/qcom/sc8180x.dtsi
View File

@ -1853,7 +1853,7 @@
power-domains = <&gcc PCIE_3_GDSC>;
interconnects = <&aggre2_noc MASTER_PCIE_3 0 &mc_virt SLAVE_EBI_CH0 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_3 0>;
interconnect-names = "pcie-mem", "cpu-pcie";
phys = <&pcie3_phy>;
@ -1952,7 +1952,7 @@
power-domains = <&gcc PCIE_1_GDSC>;
interconnects = <&aggre2_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI_CH0 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_1 0>;
interconnect-names = "pcie-mem", "cpu-pcie";
phys = <&pcie1_phy>;
@ -2051,7 +2051,7 @@
power-domains = <&gcc PCIE_2_GDSC>;
interconnects = <&aggre2_noc MASTER_PCIE_2 0 &mc_virt SLAVE_EBI_CH0 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_2 0>;
interconnect-names = "pcie-mem", "cpu-pcie";
phys = <&pcie2_phy>;
@ -2093,7 +2093,7 @@
"jedec,ufs-2.0";
reg = <0 0x01d84000 0 0x2500>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufs_mem_phy_lanes>;
phys = <&ufs_mem_phy>;
phy-names = "ufsphy";
lanes-per-direction = <2>;
#reset-cells = <1>;
@ -2132,10 +2132,8 @@
ufs_mem_phy: phy-wrapper@1d87000 {
compatible = "qcom,sc8180x-qmp-ufs-phy";
reg = <0 0x01d87000 0 0x1c0>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
reg = <0 0x01d87000 0 0x1000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
clock-names = "ref",
@ -2143,16 +2141,12 @@
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
status = "disabled";
ufs_mem_phy_lanes: phy@1d87400 {
reg = <0 0x01d87400 0 0x108>,
<0 0x01d87600 0 0x1e0>,
<0 0x01d87c00 0 0x1dc>,
<0 0x01d87800 0 0x108>,
<0 0x01d87a00 0 0x1e0>;
#phy-cells = <0>;
};
power-domains = <&gcc UFS_PHY_GDSC>;
#phy-cells = <0>;
status = "disabled";
};
ipa_virt: interconnect@1e00000 {
@ -2551,11 +2545,14 @@
system-cache-controller@9200000 {
compatible = "qcom,sc8180x-llcc";
reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>,
<0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>,
<0 0x09600000 0 0x50000>;
reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
<0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>,
<0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>,
<0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>,
<0 0x09600000 0 0x58000>;
reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
"llcc3_base", "llcc_broadcast_base";
"llcc3_base", "llcc4_base", "llcc5_base",
"llcc6_base", "llcc7_base", "llcc_broadcast_base";
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
};

15
arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
View File

@ -619,15 +619,16 @@
status = "okay";
/* FIXME: verify */
touchscreen@10 {
compatible = "hid-over-i2c";
compatible = "elan,ekth5015m", "elan,ekth6915";
reg = <0x10>;
hid-descr-addr = <0x1>;
interrupts-extended = <&tlmm 175 IRQ_TYPE_LEVEL_LOW>;
vdd-supply = <&vreg_misc_3p3>;
vddl-supply = <&vreg_s10b>;
reset-gpios = <&tlmm 99 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
no-reset-on-power-off;
vcc33-supply = <&vreg_misc_3p3>;
vccio-supply = <&vreg_misc_3p3>;
pinctrl-names = "default";
pinctrl-0 = <&ts0_default>;
@ -1451,8 +1452,8 @@
reset-n-pins {
pins = "gpio99";
function = "gpio";
output-high;
drive-strength = <16>;
drive-strength = <2>;
bias-disable;
};
};

1
arch/arm64/boot/dts/qcom/sdm630.dtsi
View File

@ -1258,6 +1258,7 @@
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,parkmode-disable-ss-quirk;
/*
* SDM630 technically supports USB3 but I

100
arch/arm64/boot/dts/qcom/sdm845.dtsi
View File

@ -18,6 +18,7 @@
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sdm845.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/phy/phy-qcom-qusb2.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/reset/qcom,sdm845-aoss.h>
@ -2634,6 +2635,8 @@
clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
power-domains = <&gcc UFS_PHY_GDSC>;
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
status = "disabled";
@ -3981,80 +3984,54 @@
nvmem-cells = <&qusb2s_hstx_trim>;
};
usb_1_qmpphy: phy@88e9000 {
usb_1_qmpphy: phy@88e8000 {
compatible = "qcom,sdm845-qmp-usb3-dp-phy";
reg = <0 0x088e9000 0 0x18c>,
<0 0x088e8000 0 0x38>,
<0 0x088ea000 0 0x40>;
reg = <0 0x088e8000 0 0x3000>;
status = "disabled";
#address-cells = <2>;
#size-cells = <2>;
ranges;
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
<&gcc GCC_USB3_PRIM_CLKREF_CLK>,
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
clock-names = "aux", "cfg_ahb", "ref", "com_aux";
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
clock-names = "aux",
"ref",
"com_aux",
"usb3_pipe",
"cfg_ahb";
resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
<&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
reset-names = "phy", "common";
usb_1_ssphy: usb3-phy@88e9200 {
reg = <0 0x088e9200 0 0x128>,
<0 0x088e9400 0 0x200>,
<0 0x088e9c00 0 0x218>,
<0 0x088e9600 0 0x128>,
<0 0x088e9800 0 0x200>,
<0 0x088e9a00 0 0x100>;
#clock-cells = <0>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "usb3_phy_pipe_clk_src";
};
dp_phy: dp-phy@88ea200 {
reg = <0 0x088ea200 0 0x200>,
<0 0x088ea400 0 0x200>,
<0 0x088eaa00 0 0x200>,
<0 0x088ea600 0 0x200>,
<0 0x088ea800 0 0x200>;
#clock-cells = <1>;
#phy-cells = <0>;
};
#clock-cells = <1>;
#phy-cells = <1>;
};
usb_2_qmpphy: phy@88eb000 {
compatible = "qcom,sdm845-qmp-usb3-uni-phy";
reg = <0 0x088eb000 0 0x18c>;
status = "disabled";
#address-cells = <2>;
#size-cells = <2>;
ranges;
reg = <0 0x088eb000 0 0x1000>;
clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
<&gcc GCC_USB3_SEC_CLKREF_CLK>,
<&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
clock-names = "aux", "cfg_ahb", "ref", "com_aux";
<&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
<&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
clock-names = "aux",
"cfg_ahb",
"ref",
"com_aux",
"pipe";
clock-output-names = "usb3_uni_phy_pipe_clk_src";
#clock-cells = <0>;
#phy-cells = <0>;
resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
<&gcc GCC_USB3_PHY_SEC_BCR>;
reset-names = "phy", "common";
resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
<&gcc GCC_USB3PHY_PHY_SEC_BCR>;
reset-names = "phy",
"phy_phy";
usb_2_ssphy: phy@88eb200 {
reg = <0 0x088eb200 0 0x128>,
<0 0x088eb400 0 0x1fc>,
<0 0x088eb800 0 0x218>,
<0 0x088eb600 0 0x70>;
#clock-cells = <0>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "usb3_uni_phy_pipe_clk_src";
};
status = "disabled";
};
usb_1: usb@a6f8800 {
@ -4103,7 +4080,8 @@
iommus = <&apps_smmu 0x740 0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
snps,parkmode-disable-ss-quirk;
phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
};
};
@ -4154,7 +4132,8 @@
iommus = <&apps_smmu 0x760 0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
snps,parkmode-disable-ss-quirk;
phys = <&usb_2_hsphy>, <&usb_2_qmpphy>;
phy-names = "usb2-phy", "usb3-phy";
};
};
@ -4571,8 +4550,9 @@
"ctrl_link_iface", "stream_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
phys = <&dp_phy>;
assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
phy-names = "dp";
operating-points-v2 = <&dp_opp_table>;
@ -4910,8 +4890,8 @@
<&mdss_dsi0_phy 1>,
<&mdss_dsi1_phy 0>,
<&mdss_dsi1_phy 1>,
<&dp_phy 0>,
<&dp_phy 1>;
<&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
clock-names = "bi_tcxo",
"gcc_disp_gpll0_clk_src",
"gcc_disp_gpll0_div_clk_src",

1
arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts
View File

@ -488,6 +488,7 @@
&ipa {
qcom,gsi-loader = "self";
memory-region = <&ipa_fw_mem>;
firmware-name = "qcom/sdm850/LENOVO/81JL/ipa_fws.elf";
status = "okay";
};

2
arch/arm64/boot/dts/qcom/sm6115.dtsi
View File

@ -1043,6 +1043,8 @@
clocks = <&gcc GCC_UFS_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
clock-names = "ref", "ref_aux";
power-domains = <&gcc GCC_UFS_PHY_GDSC>;
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
status = "disabled";

5
arch/arm64/boot/dts/qcom/sm6350.dtsi
View File

@ -1197,6 +1197,8 @@
clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
power-domains = <&gcc UFS_PHY_GDSC>;
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
@ -1297,6 +1299,7 @@
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
label = "adsp";
qcom,non-secure-domain;
#address-cells = <1>;
#size-cells = <0>;
@ -1557,6 +1560,7 @@
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
label = "cdsp";
qcom,non-secure-domain;
#address-cells = <1>;
#size-cells = <0>;
@ -1864,6 +1868,7 @@
snps,dis_enblslpm_quirk;
snps,has-lpm-erratum;
snps,hird-threshold = /bits/ 8 <0x10>;
snps,parkmode-disable-ss-quirk;
phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
};

22
arch/arm64/boot/dts/qcom/sm8250.dtsi
View File

@ -2169,7 +2169,7 @@
"jedec,ufs-2.0";
reg = <0 0x01d84000 0 0x3000>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufs_mem_phy_lanes>;
phys = <&ufs_mem_phy>;
phy-names = "ufsphy";
lanes-per-direction = <2>;
#reset-cells = <1>;
@ -2217,10 +2217,8 @@
ufs_mem_phy: phy@1d87000 {
compatible = "qcom,sm8250-qmp-ufs-phy";
reg = <0 0x01d87000 0 0x1c0>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
reg = <0 0x01d87000 0 0x1000>;
clock-names = "ref",
"ref_aux";
clocks = <&rpmhcc RPMH_CXO_CLK>,
@ -2228,16 +2226,12 @@
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
status = "disabled";
ufs_mem_phy_lanes: phy@1d87400 {
reg = <0 0x01d87400 0 0x16c>,
<0 0x01d87600 0 0x200>,
<0 0x01d87c00 0 0x200>,
<0 0x01d87800 0 0x16c>,
<0 0x01d87a00 0 0x200>;
#phy-cells = <0>;
};
power-domains = <&gcc UFS_PHY_GDSC>;
#phy-cells = <0>;
status = "disabled";
};
cryptobam: dma-controller@1dc4000 {

2
arch/arm64/boot/dts/qcom/sm8350.dtsi
View File

@ -1731,6 +1731,8 @@
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
power-domains = <&gcc UFS_PHY_GDSC>;
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
status = "disabled";

2
arch/arm64/boot/dts/qcom/sm8450.dtsi
View File

@ -4200,6 +4200,8 @@
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
<&gcc GCC_UFS_0_CLKREF_EN>;
power-domains = <&gcc UFS_PHY_GDSC>;
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
status = "disabled";

5
arch/arm64/boot/dts/renesas/r8a779a0.dtsi
View File

@ -2910,6 +2910,9 @@
interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
<&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
"hyp-virt";
};
};

5
arch/arm64/boot/dts/renesas/r8a779f0.dtsi
View File

@ -1181,7 +1181,10 @@
interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
<&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
"hyp-virt";
};
ufs30_clk: ufs30-clk {

5
arch/arm64/boot/dts/renesas/r8a779g0.dtsi
View File

@ -2350,6 +2350,9 @@
interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
<&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
"hyp-virt";
};
};

5
arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
View File

@ -50,7 +50,10 @@
interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
<&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
"hyp-virt";
};
};

5
arch/arm64/boot/dts/renesas/r9a07g044.dtsi
View File

@ -1288,6 +1288,9 @@
interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
<&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
"hyp-virt";
};
};

5
arch/arm64/boot/dts/renesas/r9a07g054.dtsi
View File

@ -1295,6 +1295,9 @@
interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
<&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
"hyp-virt";
};
};

89
arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts
View File

@ -5,6 +5,8 @@
*/
/dts-v1/;
#include <dt-bindings/leds/common.h>
#include "rk3308.dtsi"
/ {
@ -15,6 +17,7 @@
ethernet0 = &gmac;
mmc0 = &emmc;
mmc1 = &sdmmc;
mmc2 = &sdio;
};
chosen {
@ -24,17 +27,21 @@
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&green_led_gio>, <&heartbeat_led_gpio>;
pinctrl-0 = <&green_led>, <&heartbeat_led>;
green-led {
color = <LED_COLOR_ID_GREEN>;
default-state = "on";
function = LED_FUNCTION_POWER;
gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
label = "rockpis:green:power";
linux,default-trigger = "default-on";
};
blue-led {
color = <LED_COLOR_ID_BLUE>;
default-state = "on";
function = LED_FUNCTION_HEARTBEAT;
gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
label = "rockpis:blue:user";
linux,default-trigger = "heartbeat";
@ -126,21 +133,37 @@
};
&emmc {
bus-width = <4>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
cap-sd-highspeed;
no-sdio;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
vmmc-supply = <&vcc_io>;
status = "okay";
};
&gmac {
clock_in_out = "output";
phy-handle = <&rtl8201f>;
phy-supply = <&vcc_io>;
snps,reset-gpio = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 50000 50000>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
rtl8201f: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
pinctrl-names = "default";
pinctrl-0 = <&mac_rst>;
reset-assert-us = <20000>;
reset-deassert-us = <50000>;
reset-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
};
};
};
&i2c1 {
@ -151,12 +174,32 @@
pinctrl-names = "default";
pinctrl-0 = <&rtc_32k>;
bluetooth {
bt_reg_on: bt-reg-on {
rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_wake_host: bt-wake-host {
rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
};
host_wake_bt: host-wake-bt {
rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
gmac {
mac_rst: mac-rst {
rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
leds {
green_led_gio: green-led-gpio {
green_led: green-led {
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
};
heartbeat_led_gpio: heartbeat-led-gpio {
heartbeat_led: heartbeat-led {
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
@ -194,15 +237,31 @@
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
max-frequency = <1000000>;
max-frequency = <100000000>;
mmc-pwrseq = <&sdio_pwrseq>;
no-mmc;
no-sd;
non-removable;
sd-uhs-sdr104;
sd-uhs-sdr50;
vmmc-supply = <&vcc_io>;
vqmmc-supply = <&vcc_1v8>;
status = "okay";
rtl8723ds: wifi@1 {
reg = <1>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA0 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host-wake";
pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake>;
};
};
&sdmmc {
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
vmmc-supply = <&vcc_io>;
status = "okay";
};
@ -221,16 +280,22 @@
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer>;
status = "okay";
};
&uart4 {
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "realtek,rtl8723bs-bt";
device-wake-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>;
compatible = "realtek,rtl8723ds-bt";
device-wake-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
enable-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>;
host-wake-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&bt_reg_on &bt_wake_host &host_wake_bt>;
};
};

4
arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts
View File

@ -186,8 +186,8 @@
rk805: pmic@18 {
compatible = "rockchip,rk805";
reg = <0x18>;
interrupt-parent = <&gpio2>;
interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&gpio0>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <1>;
clock-output-names = "xin32k", "rk805-clkout2";
gpio-controller;

4
arch/arm64/boot/dts/rockchip/rk3328.dtsi
View File

@ -822,8 +822,8 @@
<0>, <24000000>,
<24000000>, <24000000>,
<15000000>, <15000000>,
<100000000>, <100000000>,
<100000000>, <100000000>,
<300000000>, <100000000>,
<400000000>, <100000000>,
<50000000>, <100000000>,
<100000000>, <100000000>,
<50000000>, <50000000>,

3
arch/arm64/boot/dts/rockchip/rk3368.dtsi
View File

@ -790,6 +790,7 @@
dma-names = "tx";
pinctrl-names = "default";
pinctrl-0 = <&spdif_tx>;
#sound-dai-cells = <0>;
status = "disabled";
};
@ -801,6 +802,7 @@
clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
dmas = <&dmac_bus 6>, <&dmac_bus 7>;
dma-names = "tx", "rx";
#sound-dai-cells = <0>;
status = "disabled";
};
@ -814,6 +816,7 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&i2s_8ch_bus>;
#sound-dai-cells = <0>;
status = "disabled";
};

2
arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
View File

@ -450,7 +450,7 @@ ap_i2c_audio: &i2c8 {
dlg,btn-cfg = <50>;
dlg,mic-det-thr = <500>;
dlg,jack-ins-deb = <20>;
dlg,jack-det-rate = "32ms_64ms";
dlg,jack-det-rate = "32_64";
dlg,jack-rem-deb = <1>;
dlg,a-d-btn-thr = <0xa>;

2
arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
View File

@ -289,7 +289,7 @@
regulator-name = "vdd_gpu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;

2
arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts
View File

@ -268,7 +268,7 @@
vcc9-supply = <&vcc3v3_sys>;
codec {
mic-in-differential;
rockchip,mic-in-differential;
};
regulators {

2
arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
View File

@ -475,7 +475,7 @@
};
codec {
mic-in-differential;
rockchip,mic-in-differential;
};
};
};

4
arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dts
View File

@ -11,6 +11,10 @@
};
};
&pmu_io_domains {
vccio3-supply = <&vccio_sd>;
};
&sdmmc0 {
bus-width = <4>;
cap-mmc-highspeed;

48
arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi
View File

@ -39,9 +39,9 @@
};
};
dc_12v: dc-12v-regulator {
vcc12v_dcin: vcc12v-dcin-regulator {
compatible = "regulator-fixed";
regulator-name = "dc_12v";
regulator-name = "vcc12v_dcin";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
@ -65,7 +65,7 @@
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&dc_12v>;
vin-supply = <&vcc12v_dcin>;
};
vcc5v0_sys: vcc5v0-sys-regulator {
@ -75,16 +75,7 @@
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&dc_12v>;
};
vcc5v0_usb_host: vcc5v0-usb-host-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usb_host";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc12v_dcin>;
};
vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
@ -94,8 +85,9 @@
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_usb_otg_en>;
regulator-name = "vcc5v0_usb_otg";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc5v0_sys>;
};
};
@ -123,6 +115,10 @@
cpu-supply = <&vdd_cpu>;
};
&display_subsystem {
status = "disabled";
};
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
@ -405,8 +401,8 @@
&pmu_io_domains {
pmuio1-supply = <&vcc3v3_pmu>;
pmuio2-supply = <&vcc3v3_pmu>;
vccio1-supply = <&vccio_acodec>;
vccio3-supply = <&vccio_sd>;
vccio1-supply = <&vcc_3v3>;
vccio2-supply = <&vcc_1v8>;
vccio4-supply = <&vcc_1v8>;
vccio5-supply = <&vcc_3v3>;
vccio6-supply = <&vcc_1v8>;
@ -429,28 +425,12 @@
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host0_xhci {
dr_mode = "host";
extcon = <&usb2phy0>;
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
&usb_host1_xhci {
status = "okay";
};
@ -460,7 +440,7 @@
};
&usb2phy0_host {
phy-supply = <&vcc5v0_usb_host>;
phy-supply = <&vcc5v0_sys>;
status = "okay";
};

16
arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts
View File

@ -39,7 +39,7 @@
&gmac0_rx_bus2
&gmac0_rgmii_clk
&gmac0_rgmii_bus>;
snps,reset-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>;
snps,reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 15ms, 50ms for rtl8211f */
snps,reset-delays-us = <0 15000 50000>;
@ -61,7 +61,7 @@
&gmac1m1_rx_bus2
&gmac1m1_rgmii_clk
&gmac1m1_rgmii_bus>;
snps,reset-gpio = <&gpio0 RK_PB1 GPIO_ACTIVE_LOW>;
snps,reset-gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 15ms, 50ms for rtl8211f */
snps,reset-delays-us = <0 15000 50000>;
@ -71,18 +71,18 @@
};
&mdio0 {
rgmii_phy0: ethernet-phy@0 {
rgmii_phy0: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
reg = <0x1>;
pinctrl-0 = <&eth_phy0_reset_pin>;
pinctrl-names = "default";
};
};
&mdio1 {
rgmii_phy1: ethernet-phy@0 {
rgmii_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
reg = <0x1>;
pinctrl-0 = <&eth_phy1_reset_pin>;
pinctrl-names = "default";
};
@ -102,6 +102,10 @@
};
};
&pmu_io_domains {
vccio3-supply = <&vcc_3v3>;
};
&sdhci {
bus-width = <8>;
max-frequency = <200000000>;

4
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
View File

@ -530,10 +530,6 @@
};
};
};
codec {
mic-in-differential;
};
};
};

1
arch/arm64/boot/dts/rockchip/rk356x.dtsi
View File

@ -749,6 +749,7 @@
clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
power-domains = <&power RK3568_PD_VO>;
status = "disabled";
};

1
arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
View File

@ -390,6 +390,7 @@
pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
<&rk806_dvs2_null>, <&rk806_dvs3_null>;
spi-max-frequency = <1000000>;
system-power-controller;
vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>;

4
arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi
View File

@ -1309,8 +1309,6 @@
0 0 0 0
>;
tdm-slots = <2>;
rx-num-evt = <32>;
tx-num-evt = <32>;
#sound-dai-cells = <0>;
status = "disabled";
};
@ -1327,8 +1325,6 @@
0 0 0 0
>;
tdm-slots = <2>;
rx-num-evt = <32>;
tx-num-evt = <32>;
#sound-dai-cells = <0>;
status = "disabled";
};

2
arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts
View File

@ -903,6 +903,4 @@
0 0 0 0
0 0 0 0
>;
tx-num-evt = <32>;
rx-num-evt = <32>;
};

2
arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi
View File

@ -481,8 +481,6 @@
0 0 0 0
0 0 0 0
>;
tx-num-evt = <32>;
rx-num-evt = <32>;
};
&dss {

12
arch/arm64/include/asm/acpi.h
View File

@ -119,6 +119,18 @@ static inline u32 get_acpi_id_for_cpu(unsigned int cpu)
return acpi_cpu_get_madt_gicc(cpu)->uid;
}
static inline int get_cpu_for_acpi_id(u32 uid)
{
int cpu;
for (cpu = 0; cpu < nr_cpu_ids; cpu++)
if (acpi_cpu_get_madt_gicc(cpu) &&
uid == get_acpi_id_for_cpu(cpu))
return cpu;
return -EINVAL;
}
static inline void arch_fix_phys_package_id(int num, u32 slot) { }
void __init acpi_init_cpus(void);
int apei_claim_sea(struct pt_regs *regs);

4
arch/arm64/include/asm/barrier.h
View File

@ -40,6 +40,10 @@
*/
#define dgh() asm volatile("hint #6" : : : "memory")
#define spec_bar() asm volatile(ALTERNATIVE("dsb nsh\nisb\n", \
SB_BARRIER_INSN"nop\n", \
ARM64_HAS_SB))
#ifdef CONFIG_ARM64_PSEUDO_NMI
#define pmr_sync() \
do { \

16
arch/arm64/include/asm/cputype.h
View File

@ -86,6 +86,14 @@
#define ARM_CPU_PART_CORTEX_X2 0xD48
#define ARM_CPU_PART_NEOVERSE_N2 0xD49
#define ARM_CPU_PART_CORTEX_A78C 0xD4B
#define ARM_CPU_PART_CORTEX_X1C 0xD4C
#define ARM_CPU_PART_CORTEX_X3 0xD4E
#define ARM_CPU_PART_NEOVERSE_V2 0xD4F
#define ARM_CPU_PART_CORTEX_A720 0xD81
#define ARM_CPU_PART_CORTEX_X4 0xD82
#define ARM_CPU_PART_NEOVERSE_V3 0xD84
#define ARM_CPU_PART_CORTEX_X925 0xD85
#define ARM_CPU_PART_CORTEX_A725 0xD87
#define APM_CPU_PART_XGENE 0x000
#define APM_CPU_VAR_POTENZA 0x00
@ -159,6 +167,14 @@
#define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)
#define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)
#define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C)
#define MIDR_CORTEX_X1C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1C)
#define MIDR_CORTEX_X3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X3)
#define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2)
#define MIDR_CORTEX_A720 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720)
#define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4)
#define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)
#define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)
#define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)
#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)

1
arch/arm64/include/asm/jump_label.h
View File

@ -13,6 +13,7 @@
#include <linux/types.h>
#include <asm/insn.h>
#define HAVE_JUMP_LABEL_BATCH
#define JUMP_LABEL_NOP_SIZE AARCH64_INSN_SIZE
static __always_inline bool arch_static_branch(struct static_key * const key,

2
arch/arm64/include/asm/unistd32.h
View File

@ -840,7 +840,7 @@ __SYSCALL(__NR_pselect6_time64, compat_sys_pselect6_time64)
#define __NR_ppoll_time64 414
__SYSCALL(__NR_ppoll_time64, compat_sys_ppoll_time64)
#define __NR_io_pgetevents_time64 416
__SYSCALL(__NR_io_pgetevents_time64, sys_io_pgetevents)
__SYSCALL(__NR_io_pgetevents_time64, compat_sys_io_pgetevents_time64)
#define __NR_recvmmsg_time64 417
__SYSCALL(__NR_recvmmsg_time64, compat_sys_recvmmsg_time64)
#define __NR_mq_timedsend_time64 418

13
arch/arm64/kernel/acpi_numa.c
View File

@ -27,24 +27,13 @@
#include <asm/numa.h>
static int acpi_early_node_map[NR_CPUS] __initdata = { NUMA_NO_NODE };
static int acpi_early_node_map[NR_CPUS] __initdata = { [0 ... NR_CPUS - 1] = NUMA_NO_NODE };
int __init acpi_numa_get_nid(unsigned int cpu)
{
return acpi_early_node_map[cpu];
}
static inline int get_cpu_for_acpi_id(u32 uid)
{
int cpu;
for (cpu = 0; cpu < nr_cpu_ids; cpu++)
if (uid == get_acpi_id_for_cpu(cpu))
return cpu;
return -EINVAL;
}
static int __init acpi_parse_gicc_pxm(union acpi_subtable_headers *header,
const unsigned long end)
{

3
arch/arm64/kernel/armv8_deprecated.c
View File

@ -464,6 +464,9 @@ static int run_all_insn_set_hw_mode(unsigned int cpu)
for (int i = 0; i < ARRAY_SIZE(insn_emulations); i++) {
struct insn_emulation *insn = insn_emulations[i];
bool enable = READ_ONCE(insn->current_mode) == INSN_HW;
if (insn->status == INSN_UNAVAILABLE)
continue;
if (insn->set_hw_mode && insn->set_hw_mode(enable)) {
pr_warn("CPU[%u] cannot support the emulation of %s",
cpu, insn->name);

31
arch/arm64/kernel/cpu_errata.c
View File

@ -448,6 +448,30 @@ static const struct midr_range erratum_spec_unpriv_load_list[] = {
};
#endif
#ifdef CONFIG_ARM64_ERRATUM_3194386
static const struct midr_range erratum_spec_ssbs_list[] = {
MIDR_ALL_VERSIONS(MIDR_CORTEX_A76),
MIDR_ALL_VERSIONS(MIDR_CORTEX_A77),
MIDR_ALL_VERSIONS(MIDR_CORTEX_A78),
MIDR_ALL_VERSIONS(MIDR_CORTEX_A78C),
MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
MIDR_ALL_VERSIONS(MIDR_CORTEX_A720),
MIDR_ALL_VERSIONS(MIDR_CORTEX_A725),
MIDR_ALL_VERSIONS(MIDR_CORTEX_X1),
MIDR_ALL_VERSIONS(MIDR_CORTEX_X1C),
MIDR_ALL_VERSIONS(MIDR_CORTEX_X2),
MIDR_ALL_VERSIONS(MIDR_CORTEX_X3),
MIDR_ALL_VERSIONS(MIDR_CORTEX_X4),
MIDR_ALL_VERSIONS(MIDR_CORTEX_X925),
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1),
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1),
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2),
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3),
{}
};
#endif
const struct arm64_cpu_capabilities arm64_errata[] = {
#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
{
@ -746,6 +770,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
.cpu_enable = cpu_clear_bf16_from_user_emulation,
},
#endif
#ifdef CONFIG_ARM64_ERRATUM_3194386
{
.desc = "SSBS not fully self-synchronizing",
.capability = ARM64_WORKAROUND_SPECULATIVE_SSBS,
ERRATA_MIDR_RANGE_LIST(erratum_spec_ssbs_list),
},
#endif
#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD
{
.desc = "ARM errata 2966298, 3117295",

12
arch/arm64/kernel/cpufeature.c
View File

@ -2203,6 +2203,17 @@ static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap)
}
#endif /* CONFIG_ARM64_MTE */
static void user_feature_fixup(void)
{
if (cpus_have_cap(ARM64_WORKAROUND_SPECULATIVE_SSBS)) {
struct arm64_ftr_reg *regp;
regp = get_arm64_ftr_reg(SYS_ID_AA64PFR1_EL1);
if (regp)
regp->user_mask &= ~ID_AA64PFR1_EL1_SSBS_MASK;
}
}
static void elf_hwcap_fixup(void)
{
#ifdef CONFIG_ARM64_ERRATUM_1742098
@ -3358,6 +3369,7 @@ void __init setup_cpu_features(void)
u32 cwg;
setup_system_capabilities();
user_feature_fixup();
setup_elf_hwcaps(arm64_elf_hwcaps);
if (system_supports_32bit_el0()) {

11
arch/arm64/kernel/jump_label.c
View File

@ -7,11 +7,12 @@
*/
#include <linux/kernel.h>
#include <linux/jump_label.h>
#include <linux/smp.h>
#include <asm/insn.h>
#include <asm/patching.h>
void arch_jump_label_transform(struct jump_entry *entry,
enum jump_label_type type)
bool arch_jump_label_transform_queue(struct jump_entry *entry,
enum jump_label_type type)
{
void *addr = (void *)jump_entry_code(entry);
u32 insn;
@ -25,4 +26,10 @@ void arch_jump_label_transform(struct jump_entry *entry,
}
aarch64_insn_patch_text_nosync(addr, insn);
return true;
}
void arch_jump_label_transform_apply(void)
{
kick_all_cpus_sync();
}

12
arch/arm64/kernel/proton-pack.c
View File

@ -558,6 +558,18 @@ static enum mitigation_state spectre_v4_enable_hw_mitigation(void)
/* SCTLR_EL1.DSSBS was initialised to 0 during boot */
set_pstate_ssbs(0);
/*
* SSBS is self-synchronizing and is intended to affect subsequent
* speculative instructions, but some CPUs can speculate with a stale
* value of SSBS.
*
* Mitigate this with an unconditional speculation barrier, as CPUs
* could mis-speculate branches and bypass a conditional barrier.
*/
if (IS_ENABLED(CONFIG_ARM64_ERRATUM_3194386))
spec_bar();
return SPECTRE_MITIGATED;
}

3
arch/arm64/kernel/setup.c
View File

@ -371,9 +371,6 @@ void __init __no_sanitize_address setup_arch(char **cmdline_p)
smp_init_cpus();
smp_build_mpidr_hash();
/* Init percpu seeds for random tags after cpus are set up. */
kasan_init_sw_tags();
#ifdef CONFIG_ARM64_SW_TTBR0_PAN
/*
* Make sure init_thread_info.ttbr0 always generates translation

2
arch/arm64/kernel/smp.c
View File

@ -459,6 +459,8 @@ void __init smp_prepare_boot_cpu(void)
init_gic_priority_masking();
kasan_init_hw_tags();
/* Init percpu seeds for random tags after cpus are set up. */
kasan_init_sw_tags();
}
/*

16
arch/arm64/kernel/syscall.c
View File

@ -56,17 +56,15 @@ static void invoke_syscall(struct pt_regs *regs, unsigned int scno,
syscall_set_return_value(current, regs, 0, ret);
/*
* Ultimately, this value will get limited by KSTACK_OFFSET_MAX(),
* but not enough for arm64 stack utilization comfort. To keep
* reasonable stack head room, reduce the maximum offset to 9 bits.
* This value will get limited by KSTACK_OFFSET_MAX(), which is 10
* bits. The actual entropy will be further reduced by the compiler
* when applying stack alignment constraints: the AAPCS mandates a
* 16-byte aligned SP at function boundaries, which will remove the
* 4 low bits from any entropy chosen here.
*
* The actual entropy will be further reduced by the compiler when
* applying stack alignment constraints: the AAPCS mandates a
* 16-byte (i.e. 4-bit) aligned SP at function boundaries.
*
* The resulting 5 bits of entropy is seen in SP[8:4].
* The resulting 6 bits of entropy is seen in SP[9:4].
*/
choose_random_kstack_offset(get_random_u16() & 0x1FF);
choose_random_kstack_offset(get_random_u16());
}
static inline bool has_syscall_work(unsigned long flags)

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