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drm/amd/display: Disable error correction if it's not supported

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[ Upstream commit a8ac994cf0 ]

[Why]
Error correction was enabled in a monitor which doesn't support.

[How]
Disable error correction if it's not supported

Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Cruise <cruise.hung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Stable-dep-of: a8baec4623 ("drm/amd/display: Fix FEC_READY write on DP LT")
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Cruise 2024-04-12 09:51:29 +08:00 committed by Greg Kroah-Hartman
parent d72432755b
commit 27bbf0b1ca
1 changed files with 21 additions and 26 deletions
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47
drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c
View File

@ -143,32 +143,27 @@ enum dc_status dp_set_fec_ready(struct dc_link *link, const struct link_resource
link_enc = link_enc_cfg_get_link_enc(link); link_enc = link_enc_cfg_get_link_enc(link);
ASSERT(link_enc); ASSERT(link_enc);
if (link_enc->funcs->fec_set_ready == NULL)
return DC_NOT_SUPPORTED;
if (!dp_should_enable_fec(link)) if (ready && dp_should_enable_fec(link)) {
return status; if (link->fec_state == dc_link_fec_not_ready) {
if (link_enc->funcs->fec_set_ready &&
link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
if (ready) {
fec_config = 1; fec_config = 1;
status = core_link_write_dpcd(link,
DP_FEC_CONFIGURATION, status = core_link_write_dpcd(link, DP_FEC_CONFIGURATION,
&fec_config, &fec_config, sizeof(fec_config));
sizeof(fec_config));
if (status == DC_OK) { if (status == DC_OK) {
link_enc->funcs->fec_set_ready(link_enc, true); link_enc->funcs->fec_set_ready(link_enc, true);
link->fec_state = dc_link_fec_ready; link->fec_state = dc_link_fec_ready;
} else {
link_enc->funcs->fec_set_ready(link_enc, false);
link->fec_state = dc_link_fec_not_ready;
dm_error("dpcd write failed to set fec_ready");
} }
} else if (link->fec_state == dc_link_fec_ready) { }
} else {
if (link->fec_state == dc_link_fec_ready) {
fec_config = 0; fec_config = 0;
status = core_link_write_dpcd(link, core_link_write_dpcd(link, DP_FEC_CONFIGURATION,
DP_FEC_CONFIGURATION, &fec_config, sizeof(fec_config));
&fec_config,
sizeof(fec_config));
link_enc->funcs->fec_set_ready(link_enc, false); link_enc->funcs->fec_set_ready(link_enc, false);
link->fec_state = dc_link_fec_not_ready; link->fec_state = dc_link_fec_not_ready;
} }
@ -183,14 +178,12 @@ void dp_set_fec_enable(struct dc_link *link, bool enable)
link_enc = link_enc_cfg_get_link_enc(link); link_enc = link_enc_cfg_get_link_enc(link);
ASSERT(link_enc); ASSERT(link_enc);
if (link_enc->funcs->fec_set_enable == NULL)
if (!dp_should_enable_fec(link))
return; return;
if (link_enc->funcs->fec_set_enable && if (enable && dp_should_enable_fec(link)) {
link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) { if (link->fec_state == dc_link_fec_ready) {
if (link->fec_state == dc_link_fec_ready && enable) { /* According to DP spec, FEC enable sequence can first
/* Accord to DP spec, FEC enable sequence can first
* be transmitted anytime after 1000 LL codes have * be transmitted anytime after 1000 LL codes have
* been transmitted on the link after link training * been transmitted on the link after link training
* completion. Using 1 lane RBR should have the maximum * completion. Using 1 lane RBR should have the maximum
@ -200,7 +193,9 @@ void dp_set_fec_enable(struct dc_link *link, bool enable)
udelay(7); udelay(7);
link_enc->funcs->fec_set_enable(link_enc, true); link_enc->funcs->fec_set_enable(link_enc, true);
link->fec_state = dc_link_fec_enabled; link->fec_state = dc_link_fec_enabled;
} else if (link->fec_state == dc_link_fec_enabled && !enable) { }
} else {
if (link->fec_state == dc_link_fec_enabled) {
link_enc->funcs->fec_set_enable(link_enc, false); link_enc->funcs->fec_set_enable(link_enc, false);
link->fec_state = dc_link_fec_ready; link->fec_state = dc_link_fec_ready;
} }