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clk: qcom: gpucc-sm8350: Park RCG's clk source at XO during disable
[ Upstream commit313e290902
] The RCG's clk src has to be parked at XO while disabling as per the HW recommendation, hence use clk_rcg2_shared_ops to achieve the same. Fixes:160758b05a
("clk: qcom: add support for SM8350 GPUCC") Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # SM8350-HDK Link: https://lore.kernel.org/r/20240621-sm8350-gpucc-fixes-v1-1-22db60c7c5d3@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -2,6 +2,7 @@
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/*
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* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
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* Copyright (c) 2022, Linaro Limited
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* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <linux/clk.h>
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@ -147,7 +148,7 @@ static struct clk_rcg2 gpu_cc_gmu_clk_src = {
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.parent_data = gpu_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_ops,
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.ops = &clk_rcg2_shared_ops,
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},
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};
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@ -169,7 +170,7 @@ static struct clk_rcg2 gpu_cc_hub_clk_src = {
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.parent_data = gpu_cc_parent_data_1,
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.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_ops,
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.ops = &clk_rcg2_shared_ops,
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},
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};
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