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mfd: cros_ec: Add SCP Core-1 as a new CrOS EC MCU

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MT8195 System Companion Processors(SCP) is a dual-core RISC-V MCU.
Add a new CrOS feature ID to represent the SCP's 2nd core.

The 1st core is referred to as 'core 0', and the 2nd core is referred
to as 'core 1'.

Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20220601112201.15510-16-tinghan.shen@mediatek.com
This commit is contained in:
Tinghan Shen 2022-06-01 19:22:01 +08:00 committed by Lee Jones
parent 738654be3c
commit 66ee379d74
3 changed files with 8 additions and 0 deletions
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5
drivers/mfd/cros_ec_dev.c
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@ -64,6 +64,11 @@ static const struct cros_feature_to_name cros_mcu_devices[] = {
.name = CROS_EC_DEV_SCP_NAME, .name = CROS_EC_DEV_SCP_NAME,
.desc = "System Control Processor", .desc = "System Control Processor",
}, },
{
.id = EC_FEATURE_SCP_C1,
.name = CROS_EC_DEV_SCP_C1_NAME,
.desc = "System Control Processor 2nd Core",
},
{ {
.id = EC_FEATURE_TOUCHPAD, .id = EC_FEATURE_TOUCHPAD,
.name = CROS_EC_DEV_TP_NAME, .name = CROS_EC_DEV_TP_NAME,

2
include/linux/platform_data/cros_ec_commands.h
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@ -1300,6 +1300,8 @@ enum ec_feature_code {
* mux. * mux.
*/ */
EC_FEATURE_TYPEC_MUX_REQUIRE_AP_ACK = 43, EC_FEATURE_TYPEC_MUX_REQUIRE_AP_ACK = 43,
/* The MCU is a System Companion Processor (SCP) 2nd Core. */
EC_FEATURE_SCP_C1 = 45,
}; };
#define EC_FEATURE_MASK_0(event_code) BIT(event_code % 32) #define EC_FEATURE_MASK_0(event_code) BIT(event_code % 32)

1
include/linux/platform_data/cros_ec_proto.h
View File

@ -19,6 +19,7 @@
#define CROS_EC_DEV_ISH_NAME "cros_ish" #define CROS_EC_DEV_ISH_NAME "cros_ish"
#define CROS_EC_DEV_PD_NAME "cros_pd" #define CROS_EC_DEV_PD_NAME "cros_pd"
#define CROS_EC_DEV_SCP_NAME "cros_scp" #define CROS_EC_DEV_SCP_NAME "cros_scp"
#define CROS_EC_DEV_SCP_C1_NAME "cros_scp_c1"
#define CROS_EC_DEV_TP_NAME "cros_tp" #define CROS_EC_DEV_TP_NAME "cros_tp"
/* /*