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clk: starfive: jh7110-sys: Add notifier for PLL0 clock

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commit 538d5477b2 upstream.

Add notifier function for PLL0 clock. In the function, the cpu_root clock
should be operated by saving its current parent and setting a new safe
parent (osc clock) before setting the PLL0 clock rate. After setting PLL0
rate, it should be switched back to the original parent clock.

Fixes: e2c510d6d6 ("riscv: dts: starfive: Add cpu scaling for JH7110 SoC")
Cc: stable@vger.kernel.org
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Link: https://lore.kernel.org/r/20240826080430.179788-2-xingyu.wu@starfivetech.com
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
Tested-by: Michael Jeanson <mjeanson@efficios.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Xingyu Wu 2024-08-26 16:04:29 +08:00 committed by Greg Kroah-Hartman
parent f36df5cc86
commit 72f4fc5fb2
2 changed files with 32 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

31
drivers/clk/starfive/clk-starfive-jh7110-sys.c
View File

@ -385,6 +385,32 @@ int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv,
} }
EXPORT_SYMBOL_GPL(jh7110_reset_controller_register); EXPORT_SYMBOL_GPL(jh7110_reset_controller_register);
/*
* This clock notifier is called when the rate of PLL0 clock is to be changed.
* The cpu_root clock should save the curent parent clock and switch its parent
* clock to osc before PLL0 rate will be changed. Then switch its parent clock
* back after the PLL0 rate is completed.
*/
static int jh7110_pll0_clk_notifier_cb(struct notifier_block *nb,
unsigned long action, void *data)
{
struct jh71x0_clk_priv *priv = container_of(nb, struct jh71x0_clk_priv, pll_clk_nb);
struct clk *cpu_root = priv->reg[JH7110_SYSCLK_CPU_ROOT].hw.clk;
int ret = 0;
if (action == PRE_RATE_CHANGE) {
struct clk *osc = clk_get(priv->dev, "osc");
priv->original_clk = clk_get_parent(cpu_root);
ret = clk_set_parent(cpu_root, osc);
clk_put(osc);
} else if (action == POST_RATE_CHANGE) {
ret = clk_set_parent(cpu_root, priv->original_clk);
}
return notifier_from_errno(ret);
}
static int __init jh7110_syscrg_probe(struct platform_device *pdev) static int __init jh7110_syscrg_probe(struct platform_device *pdev)
{ {
struct jh71x0_clk_priv *priv; struct jh71x0_clk_priv *priv;
@ -413,7 +439,10 @@ static int __init jh7110_syscrg_probe(struct platform_device *pdev)
if (IS_ERR(priv->pll[0])) if (IS_ERR(priv->pll[0]))
return PTR_ERR(priv->pll[0]); return PTR_ERR(priv->pll[0]);
} else { } else {
clk_put(pllclk); priv->pll_clk_nb.notifier_call = jh7110_pll0_clk_notifier_cb;
ret = clk_notifier_register(pllclk, &priv->pll_clk_nb);
if (ret)
return ret;
priv->pll[0] = NULL; priv->pll[0] = NULL;
} }

2
drivers/clk/starfive/clk-starfive-jh71x0.h
View File

@ -114,6 +114,8 @@ struct jh71x0_clk_priv {
spinlock_t rmw_lock; spinlock_t rmw_lock;
struct device *dev; struct device *dev;
void __iomem *base; void __iomem *base;
struct clk *original_clk;
struct notifier_block pll_clk_nb;
struct clk_hw *pll[3]; struct clk_hw *pll[3];
struct jh71x0_clk reg[]; struct jh71x0_clk reg[];
}; };