MIRRORS/linux-imx
1
0
Fork 0
mirror of https://github.com/nxp-imx/linux-imx.git synced 2025-07-06 17:35:20 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity

drm/amdgpu: Block MMR_READ IOCTL in reset

Browse Source 
[ Upstream commit 9e823f3070 ]

Register access from userspace should be blocked until
reset is complete.

Signed-off-by: Victor Skvortsov <victor.skvortsov@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Victor Skvortsov 2024-08-08 13:40:23 -04:00 committed by Greg Kroah-Hartman
parent c474a1a755
commit 8361e3f788
1 changed files with 32 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

45
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
View File

@ -43,6 +43,7 @@
#include "amdgpu_gem.h" #include "amdgpu_gem.h"
#include "amdgpu_display.h" #include "amdgpu_display.h"
#include "amdgpu_ras.h" #include "amdgpu_ras.h"
#include "amdgpu_reset.h"
#include "amd_pcie.h" #include "amd_pcie.h"
void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev) void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev)
@ -722,6 +723,7 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
? -EFAULT : 0; ? -EFAULT : 0;
} }
case AMDGPU_INFO_READ_MMR_REG: { case AMDGPU_INFO_READ_MMR_REG: {
int ret = 0;
unsigned int n, alloc_size; unsigned int n, alloc_size;
uint32_t *regs; uint32_t *regs;
unsigned int se_num = (info->read_mmr_reg.instance >> unsigned int se_num = (info->read_mmr_reg.instance >>
@ -731,24 +733,37 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
AMDGPU_INFO_MMR_SH_INDEX_MASK; AMDGPU_INFO_MMR_SH_INDEX_MASK;
if (!down_read_trylock(&adev->reset_domain->sem))
return -ENOENT;
/* set full masks if the userspace set all bits /* set full masks if the userspace set all bits
* in the bitfields * in the bitfields
*/ */
if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) {
se_num = 0xffffffff; se_num = 0xffffffff;
else if (se_num >= AMDGPU_GFX_MAX_SE) } else if (se_num >= AMDGPU_GFX_MAX_SE) {
return -EINVAL; ret = -EINVAL;
if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) goto out;
sh_num = 0xffffffff; }
else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE)
return -EINVAL;
if (info->read_mmr_reg.count > 128) if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) {
return -EINVAL; sh_num = 0xffffffff;
} else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) {
ret = -EINVAL;
goto out;
}
if (info->read_mmr_reg.count > 128) {
ret = -EINVAL;
goto out;
}
regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
if (!regs) if (!regs) {
return -ENOMEM; ret = -ENOMEM;
goto out;
}
alloc_size = info->read_mmr_reg.count * sizeof(*regs); alloc_size = info->read_mmr_reg.count * sizeof(*regs);
amdgpu_gfx_off_ctrl(adev, false); amdgpu_gfx_off_ctrl(adev, false);
@ -760,13 +775,17 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
info->read_mmr_reg.dword_offset + i); info->read_mmr_reg.dword_offset + i);
kfree(regs); kfree(regs);
amdgpu_gfx_off_ctrl(adev, true); amdgpu_gfx_off_ctrl(adev, true);
return -EFAULT; ret = -EFAULT;
goto out;
} }
} }
amdgpu_gfx_off_ctrl(adev, true); amdgpu_gfx_off_ctrl(adev, true);
n = copy_to_user(out, regs, min(size, alloc_size)); n = copy_to_user(out, regs, min(size, alloc_size));
kfree(regs); kfree(regs);
return n ? -EFAULT : 0; ret = (n ? -EFAULT : 0);
out:
up_read(&adev->reset_domain->sem);
return ret;
} }
case AMDGPU_INFO_DEV_INFO: { case AMDGPU_INFO_DEV_INFO: {
struct drm_amdgpu_info_device *dev_info; struct drm_amdgpu_info_device *dev_info;