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LF-15511: arm64: dts: imx8mq: set NAND_USDHC_BUS_CLK_ROOT source clock to SYSTEM_PLL1_DIV6

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When do system suspend/resume test, uSDHC may meet timeout during eMMC
initialization. This is caused by the uSDHC AHB_BUS and IPG_CLK being
out of sync.

ERR011232 requires that uSDHC AHB_BUS and IPG_CLK must be synchronized.
Need to ensure uSDHC AHB_BUS and IPG_CLK come form same clock source to
maintain clock sync.

Signed-off-by: Luke Wang <ziniu.wang_1@nxp.com>
Reviewed-by: Haibo Chen <haibo.chen@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
This commit is contained in:
Luke Wang 2025-09-01 17:51:42 +08:00 committed by Jason Liu
parent c1943c45a4
commit 8555a7698a
1 changed files with 1 additions and 1 deletions
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2
arch/arm64/boot/dts/freescale/imx8mq.dtsi
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@ -728,7 +728,7 @@
<&clk IMX8MQ_AUDIO_PLL2>,
<0>,
<0>,
<&clk IMX8MQ_SYS1_PLL_266M>;
<&clk IMX8MQ_SYS1_PLL_133M>;
};
src: reset-controller@30390000 {