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drm/msm: fix the highest_bank_bit for sc7180

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[ Upstream commit 3e30296b37 ]

sc7180 programs the ubwc settings as 0x1e as that would mean a
highest bank bit of 14 which matches what the GPU sets as well.

However, the highest_bank_bit field of the msm_mdss_data which is
being used to program the SSPP's fetch configuration is programmed
to a highest bank bit of 16 as 0x3 translates to 16 and not 14.

Fix the highest bank bit field used for the SSPP to match the mdss
and gpu settings.

Fixes: 6f410b2462 ("drm/msm/mdss: populate missing data")
Reviewed-by: Rob Clark <robdclark@gmail.com>
Tested-by: Stephen Boyd <swboyd@chromium.org> # Trogdor.Lazor
Patchwork: https://patchwork.freedesktop.org/patch/607625/
Link: https://lore.kernel.org/r/20240808235227.2701479-1-quic_abhinavk@quicinc.com
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Abhinav Kumar 2024-08-08 16:52:27 -07:00 committed by Greg Kroah-Hartman
parent aba7569333
commit 88c232fd06
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/msm/msm_mdss.c
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@ -531,7 +531,7 @@ static const struct msm_mdss_data sc7180_data = {
.ubwc_enc_version = UBWC_2_0, .ubwc_enc_version = UBWC_2_0,
.ubwc_dec_version = UBWC_2_0, .ubwc_dec_version = UBWC_2_0,
.ubwc_static = 0x1e, .ubwc_static = 0x1e,
.highest_bank_bit = 0x3, .highest_bank_bit = 0x1,
.reg_bus_bw = 76800, .reg_bus_bw = 76800,
}; };