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KVM: arm64: AArch32: Fix spurious trapping of conditional instructions
commitc92e8b9eac
upstream. We recently upgraded the view of ESR_EL2 to 64bit, in keeping with the requirements of the architecture. However, the AArch32 emulation code was left unaudited, and the (already dodgy) code that triages whether a trap is spurious or not (because the condition code failed) broke in a subtle way: If ESR_EL2.ISS2 is ever non-zero (unlikely, but hey, this is the ARM architecture we're talking about), the hack that tests the top bits of ESR_EL2.EC will break in an interesting way. Instead, use kvm_vcpu_trap_get_class() to obtain the EC, and list all the possible ECs that can fail a condition code check. While we're at it, add SMC32 to the list, as it is explicitly listed as being allowed to trap despite failing a condition code check (as described in the HCR_EL2.TSC documentation). Fixes:0b12620fdd
("KVM: arm64: Treat ESR_EL2 as a 64-bit register") Cc: stable@vger.kernel.org Acked-by: Oliver Upton <oliver.upton@linux.dev> Link: https://lore.kernel.org/r/20240524141956.1450304-4-maz@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -50,9 +50,23 @@ bool kvm_condition_valid32(const struct kvm_vcpu *vcpu)
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u32 cpsr_cond;
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u32 cpsr_cond;
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int cond;
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int cond;
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/* Top two bits non-zero? Unconditional. */
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/*
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if (kvm_vcpu_get_esr(vcpu) >> 30)
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* These are the exception classes that could fire with a
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* conditional instruction.
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*/
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switch (kvm_vcpu_trap_get_class(vcpu)) {
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case ESR_ELx_EC_CP15_32:
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case ESR_ELx_EC_CP15_64:
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case ESR_ELx_EC_CP14_MR:
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case ESR_ELx_EC_CP14_LS:
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case ESR_ELx_EC_FP_ASIMD:
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case ESR_ELx_EC_CP10_ID:
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case ESR_ELx_EC_CP14_64:
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case ESR_ELx_EC_SVC32:
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break;
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default:
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return true;
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return true;
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}
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/* Is condition field valid? */
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/* Is condition field valid? */
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cond = kvm_vcpu_get_condition(vcpu);
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cond = kvm_vcpu_get_condition(vcpu);
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