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LF-10640-6 ptp: add NETC PTP driver support for i.MX95
The i.MX95 NETC's Timer is different from the LS1028A NETC's Timer. In addition to swapping the offsets of the upper 32-bit register and the lower 32-bit register and adding ALRAM and FIPER control registers, there are some main registers (such as the TMR_CTRL and TMR_ADD) that are used in different ways even though they have the same functionality. Yes, we can reuse the PTP driver of LS1028A and make some modifications to support i.MX95 NETC's Timer, but this will undoubtedly increase the complexity of the code and make the driver difficult to maintain. So we have added a new driver named ptp_netc to support NETC Timer of i.MX95 and future i.MX SoCs such as i.MX943, i.MX952, etc. Signed-off-by: Wei Fang <wei.fang@nxp.com> Acked-by: Clark Wang <xiaoning.wang@nxp.com>
This commit is contained in:
Wei Fang
parent
3580b08f76
commit
9eb53327f2
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@ -211,4 +211,18 @@ config PTP_DFL_TOD
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To compile this driver as a module, choose M here: the module
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will be called ptp_dfl_tod.
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config PTP_1588_CLOCK_NETC
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tristate "NXP NETC Timer as PTP clock"
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depends on FSL_NETC_PRB_IERB && (FSL_ENETC4 || FSL_ENETC_VF)
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depends on PTP_1588_CLOCK
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default y
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help
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This driver adds support for using the NXP NETC Timer as a
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PTP clock. This clock is only useful if your PTP programs
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are getting hardware time stamps on the PTP Ethernet packets
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using the SO_TIMESTAMPING API.
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To compile this driver as a module, choose M here: the module
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will be called ptp_netc.
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endmenu
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@ -20,3 +20,4 @@ obj-$(CONFIG_PTP_1588_CLOCK_MOCK) += ptp_mock.o
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obj-$(CONFIG_PTP_1588_CLOCK_VMW) += ptp_vmw.o
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obj-$(CONFIG_PTP_1588_CLOCK_OCP) += ptp_ocp.o
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obj-$(CONFIG_PTP_DFL_TOD) += ptp_dfl_tod.o
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obj-$(CONFIG_PTP_1588_CLOCK_NETC) += ptp_netc.o
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737
drivers/ptp/ptp_netc.c
Normal file
737
drivers/ptp/ptp_netc.c
Normal file
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@ -0,0 +1,737 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* NXP NETC Timer driver
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* Copyright 2023 NXP
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* Copyright (C) 2023 Wei Fang <wei.fang@nxp.com>
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*/
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#include <linux/module.h>
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#include <linux/of_platform.h>
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#include <linux/pci.h>
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#include <linux/ptp_clock_kernel.h>
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#include <linux/fsl/netc_prb_ierb.h>
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#include <linux/fsl/ptp_netc.h>
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#define NETC_TMR_CTRL 0x0080
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#define TMR_CTRL_CK_SEL GENMASK(1, 0)
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#define TMR_CTRL_TE BIT(2)
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#define TMR_COMP_MODE BIT(15)
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#define TMR_CTRL_TCLK_PERIOD GENMASK(25, 16)
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#define TMR_CTRL_FS BIT(28)
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#define TMR_ALARM1P BIT(31)
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#define NETC_TMR_TEVENT 0x0084
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#define TMR_TEVNET_PPEN(a) BIT(7 - (a))
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#define TMR_TEVENT_PPEN_ALL GENMASK(7, 5)
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#define TMR_TEVENT_ALM1EN BIT(16)
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#define TMR_TEVENT_ALM2EN BIT(17)
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#define TMR_TEVENT_ETS1_THREN BIT(20)
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#define TMR_TEVENT_ETS2_THREN BIT(21)
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#define TMR_TEVENT_ETS1EN BIT(24)
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#define TMR_TEVENT_ETS2EN BIT(25)
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#define TMR_TEVENT_ETS1_OVEN BIT(28)
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#define TMR_TEVENT_ETS2_OVEN BIT(29)
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#define NETC_TMR_TEMASK 0x0088
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#define NETC_TMR_STAT 0x0094
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#define NETC_TMR_CNT_L 0x0098
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#define NETC_TMR_CNT_H 0x009c
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#define NETC_TMR_ADD 0x00a0
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#define NETC_TMR_ACC 0x00a4
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#define NETC_TMR_PRSC 0x00a8
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#define NETC_TMR_ECTRL 0x00ac
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#define NETC_TMR_OFF_L 0x00b0
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#define NETC_TMR_OFF_H 0x00b4
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/* a = 0 or 1, a = 0 indicates TMR_ALARM1, a = 1 indicates TMR_ALARM2 */
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#define NETC_TMR_ALARM_L(a) (0x00b8 + (a) * 8)
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#define NETC_TMR_ALARM_H(a) (0x00bc + (a) * 8)
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#define NETC_TMR_ALARM_CTRL 0x00cc
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#define ALARM_CTRL_PW(a) (GENMASK(4, 0) << (a) * 8)
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#define ALARM_CTRL_PG(a) (BIT(7) << (a) * 8)
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/* a = 0, 1, 2. a = 0 indicates TMR_FIPER1, a = 1 indicates TMR_FIPER2,
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* a = 2 indicates TMR_FIPER3.
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*/
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#define NETC_TMR_FIPER(a) (0x00d0 + (a) * 4)
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#define NETC_TMR_FIPER_CTRL 0x00dc
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#define FIPER_CTRL_PW(a) (GENMASK(4, 0) << (a) * 8)
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#define FIPER_CTRL_PG(a) (BIT(6) << (a) * 8)
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#define FIPER_CTRL_DIS(a) (BIT(7) << (a) * 8)
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#define NETC_TMR_ETTS1_L 0x00e0
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#define NETC_TMR_ETTS1_H 0x00e4
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#define NETC_TMR_ETTS2_L 0x00e8
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#define NETC_TMR_ETTS2_H 0x00ec
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#define NETC_TMR_PARAM 0x00f8
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#define NETC_TMR_REGS_BAR 0
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#define NETC_TMR_FIPER_NUM 3
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#define NETC_TMR_DEFAULT_PRSC 2
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#define NETC_TMR_DEFAULT_ALARM 0xffffffffffffffffULL
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#define NETC_TMR_DEFAULT_FIPER 0xffffffff
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/* 1588 timer reference clock source select */
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#define NETC_TMR_CCM_TIMER1 0 /* enet_timer1_clk_root, from CCM */
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#define NETC_TMR_SYSTEM_CLK 1 /* enet_clk_root/2, from CCM */
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#define NETC_TMR_EXT_OSC 2 /* tmr_1588_clk, from IO pins */
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#define NETC_TMR_FIPER_PW 0x1f
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struct netc_timer {
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void __iomem *base;
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struct device *dev;
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struct pci_dev *pci_dev;
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struct platform_device *ierb_pdev;
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int irq;
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char irq_name[64];
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spinlock_t lock; /* protect regs */
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struct ptp_clock *clock;
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struct ptp_clock_info caps;
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int phc_index;
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u32 clk_select;
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u32 clk_freq;
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u32 period_int;
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/* fractional part of clock period * BIT(32) */
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u32 period_frac;
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u32 oclk_prsc; /* must be an even value */
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u32 fiper[NETC_TMR_FIPER_NUM];
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};
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static inline u32 netc_timer_read(void __iomem *reg)
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{
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return ioread32(reg);
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}
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static inline void netc_timer_write(void __iomem *reg, u32 val)
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{
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iowrite32(val, reg);
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}
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#define netc_timer_read_reg(p, o) netc_timer_read((p)->base + (o))
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#define netc_timer_write_reg(p, o, v) netc_timer_write((p)->base + (o), v)
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static u64 netc_timer_cnt_read(struct netc_timer *priv)
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{
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u32 tmr_cnt_l, tmr_cnt_h;
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u64 ns;
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/* The user must read the TMR_CNC_L register first to get
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* correct 64-bit TMR_CNT_H/L counter values.
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*/
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tmr_cnt_l = netc_timer_read_reg(priv, NETC_TMR_CNT_L);
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tmr_cnt_h = netc_timer_read_reg(priv, NETC_TMR_CNT_H);
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ns = (((u64)tmr_cnt_h) << 32) | tmr_cnt_l;
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return ns;
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}
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static void netc_timer_cnt_write(struct netc_timer *priv, u64 ns)
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{
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u32 tmr_cnt_h = upper_32_bits(ns);
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u32 tmr_cnt_l = lower_32_bits(ns);
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/* The user must write to TMR_CNT_L register first. */
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netc_timer_write_reg(priv, NETC_TMR_CNT_L, tmr_cnt_l);
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netc_timer_write_reg(priv, NETC_TMR_CNT_H, tmr_cnt_h);
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}
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static void netc_timer_alarm_write(struct netc_timer *priv,
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u64 alarm, int index)
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{
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u32 alarm_h = upper_32_bits(alarm);
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u32 alarm_l = lower_32_bits(alarm);
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netc_timer_write_reg(priv, NETC_TMR_ALARM_L(index), alarm_l);
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netc_timer_write_reg(priv, NETC_TMR_ALARM_H(index), alarm_h);
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}
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static u32 netc_timer_calculate_fiper_pulse_width(struct netc_timer *priv,
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u32 fiper)
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{
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u64 pw;
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/* Set the FIPER pulse width to half FIPER interval by default.
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* pulse_width = (fiper / 2) / TMR_GCLK_period,
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* TMR_GCLK_period = 1000000000ns / TMR_GCLK_freq,
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* TMR_GCLK_freq = (clk_freq / oclk_prsc) MHz,
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* so pulse_width = fiper * clk_freq / (2000 * oclk_prsc).
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*/
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pw = fiper * priv->clk_freq;
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pw = div_u64(pw, 2000 * priv->oclk_prsc);
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/* The FIPER_PW field only has 5 bits */
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return pw & NETC_TMR_FIPER_PW;
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}
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static void netc_timer_adjust_period(struct netc_timer *priv, u64 period)
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{
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u32 period_frac = lower_32_bits(period);
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/*
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* u32 period_int = upper_32_bits(period);
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* u32 tmr_ctrl, old_tmr_ctrl;
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* old_tmr_ctrl = netc_timer_read_reg(priv, NETC_TMR_CTRL);
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* tmr_ctrl = u32_replace_bits(old_tmr_ctrl, period_int,
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* TMR_CTRL_TCLK_PERIOD);
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* if (unlikely(old_tmr_ctrl != tmr_ctrl))
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* netc_timer_write_reg(priv, NETC_TMR_CTRL, tmr_ctrl);
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*/
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netc_timer_write_reg(priv, NETC_TMR_ADD, period_frac);
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}
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static irqreturn_t netc_timer_isr(int irq, void *data)
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{
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struct netc_timer *priv = data;
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struct ptp_clock_event event;
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u32 tmr_event, tmr_emask;
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unsigned long flags;
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spin_lock_irqsave(&priv->lock, flags);
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tmr_event = netc_timer_read_reg(priv, NETC_TMR_TEVENT);
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tmr_emask = netc_timer_read_reg(priv, NETC_TMR_TEMASK);
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/* Clear interrupts status */
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netc_timer_write_reg(priv, NETC_TMR_TEVENT, tmr_event);
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tmr_event &= tmr_emask;
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if (tmr_event & TMR_TEVENT_PPEN_ALL) {
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event.type = PTP_CLOCK_PPS;
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ptp_clock_event(priv->clock, &event);
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}
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if (tmr_event & TMR_TEVENT_ALM1EN) {
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tmr_emask &= ~TMR_TEVENT_ALM1EN;
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netc_timer_write_reg(priv, NETC_TMR_TEMASK, tmr_emask);
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netc_timer_alarm_write(priv, NETC_TMR_DEFAULT_ALARM, 0);
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}
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if (tmr_event & TMR_TEVENT_ETS1EN) {
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/* TODO */
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event.type = PTP_CLOCK_EXTTS;
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event.index = 0;
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//event.timestamp = ;
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ptp_clock_event(priv->clock, &event);
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}
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spin_unlock_irqrestore(&priv->lock, flags);
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return IRQ_HANDLED;
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}
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static int netc_timer_get_clk_config(struct netc_timer *priv)
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{
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struct device_node *node = priv->dev->of_node;
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u32 clk_cfg[3];
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u64 clk_info;
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int err;
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err = of_property_read_u32_array(node, "fsl,clk-cfg", clk_cfg,
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ARRAY_SIZE(clk_cfg));
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if (!err) {
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priv->clk_freq = clk_cfg[0];
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priv->period_int = clk_cfg[1];
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priv->period_frac = clk_cfg[2];
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return 0;
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}
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/* If "fsl,clk-cfg" property does not exist, then get the period
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* from IERB NETCCLKFR[FRAC] and NETCCLKCR[PERIOD]. And get clock
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* frequency from NETCCLKCR[FREQ].
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*/
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clk_info = netc_ierb_get_clk_config();
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if (!clk_info) {
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dev_err(priv->dev, "Clock period from NETC IERB is invalid\n");
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return -EINVAL;
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}
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priv->clk_freq = (clk_info >> 32) & NETCCLKCR_FREQ;
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priv->period_int = ((clk_info >> 32) & NETCCLKCR_PERIOD) >> 16;
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priv->period_frac = clk_info & NETCCLKCR_FRAC;
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return 0;
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}
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/* ppm: parts per million, ppb: parts per billion */
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static int netc_timer_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
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{
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struct netc_timer *priv;
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u64 clk_period, diff;
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unsigned long flags;
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bool neg_adj;
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if (!scaled_ppm)
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return 0;
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priv = container_of(ptp, struct netc_timer, caps);
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clk_period = ((u64)priv->period_int << 32) | priv->period_frac;
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neg_adj = diff_by_scaled_ppm(clk_period, scaled_ppm, &diff);
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clk_period = neg_adj ? clk_period - diff : clk_period + diff;
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spin_lock_irqsave(&priv->lock, flags);
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netc_timer_adjust_period(priv, clk_period);
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spin_unlock_irqrestore(&priv->lock, flags);
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return 0;
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}
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static int netc_timer_adjtime(struct ptp_clock_info *ptp, s64 delta)
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{
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struct netc_timer *priv;
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unsigned long flags;
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u64 ns, adj_ns;
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priv = container_of(ptp, struct netc_timer, caps);
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adj_ns = abs(delta);
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spin_lock_irqsave(&priv->lock, flags);
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ns = netc_timer_cnt_read(priv);
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if (delta < 0)
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ns -= adj_ns;
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else
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ns += adj_ns;
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netc_timer_cnt_write(priv, ns);
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spin_unlock_irqrestore(&priv->lock, flags);
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return 0;
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}
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static int netc_timer_gettimex64(struct ptp_clock_info *ptp,
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struct timespec64 *ts,
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struct ptp_system_timestamp *sts)
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{
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struct netc_timer *priv;
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unsigned long flags;
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u64 ns;
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priv = container_of(ptp, struct netc_timer, caps);
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spin_lock_irqsave(&priv->lock, flags);
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ptp_read_system_prets(sts);
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ns = netc_timer_cnt_read(priv);
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ptp_read_system_postts(sts);
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spin_unlock_irqrestore(&priv->lock, flags);
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*ts = ns_to_timespec64(ns);
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return 0;
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}
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static int netc_timer_settime64(struct ptp_clock_info *ptp,
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const struct timespec64 *ts)
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{
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struct netc_timer *priv;
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unsigned long flags;
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u64 ns;
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priv = container_of(ptp, struct netc_timer, caps);
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ns = timespec64_to_ns(ts);
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spin_lock_irqsave(&priv->lock, flags);
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netc_timer_cnt_write(priv, ns);
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spin_unlock_irqrestore(&priv->lock, flags);
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return 0;
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}
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static int netc_timer_enable_pps(struct netc_timer *priv,
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struct ptp_clock_request *rq, int on)
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{
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u32 tmr_emask, fiper, fiper_ctrl, fiper_pw;
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unsigned long flags;
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spin_lock_irqsave(&priv->lock, flags);
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tmr_emask = netc_timer_read_reg(priv, NETC_TMR_TEMASK);
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fiper_ctrl = netc_timer_read_reg(priv, NETC_TMR_FIPER_CTRL);
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if (on) {
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fiper = div_u64(NSEC_PER_SEC, priv->period_int) - 1;
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fiper = fiper * priv->period_int;
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fiper_pw = netc_timer_calculate_fiper_pulse_width(priv, fiper);
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fiper_ctrl &= ~(FIPER_CTRL_DIS(0) | FIPER_CTRL_PW(0));
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fiper_ctrl |= fiper_pw & FIPER_CTRL_PW(0);
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tmr_emask |= TMR_TEVNET_PPEN(0);
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} else {
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fiper = NETC_TMR_DEFAULT_FIPER;
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tmr_emask &= ~TMR_TEVNET_PPEN(0);
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fiper_ctrl |= FIPER_CTRL_DIS(0);
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}
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netc_timer_write_reg(priv, NETC_TMR_TEMASK, tmr_emask);
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netc_timer_write_reg(priv, NETC_TMR_FIPER(0), fiper);
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netc_timer_write_reg(priv, NETC_TMR_FIPER_CTRL, fiper_ctrl);
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spin_unlock_irqrestore(&priv->lock, flags);
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|
||||
return 0;
|
||||
}
|
||||
|
||||
static int net_timer_enable_perout(struct netc_timer *priv,
|
||||
struct ptp_clock_request *rq, int on)
|
||||
{
|
||||
u32 tmr_emask, tmr_ctrl, fiper, fiper_ctrl;
|
||||
struct timespec64 period, stime;
|
||||
u64 alarm, period_ns, cur_time;
|
||||
u32 channel, fiper_pw;
|
||||
unsigned long flags;
|
||||
|
||||
if (rq->perout.flags)
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
channel = rq->perout.index;
|
||||
if (channel >= NETC_TMR_FIPER_NUM)
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&priv->lock, flags);
|
||||
|
||||
tmr_ctrl = netc_timer_read_reg(priv, NETC_TMR_CTRL);
|
||||
tmr_emask = netc_timer_read_reg(priv, NETC_TMR_TEMASK);
|
||||
fiper_ctrl = netc_timer_read_reg(priv, NETC_TMR_FIPER_CTRL);
|
||||
if (!on) {
|
||||
tmr_emask &= ~(TMR_TEVNET_PPEN(channel) |
|
||||
TMR_TEVENT_ALM1EN);
|
||||
tmr_ctrl &= ~TMR_CTRL_FS;
|
||||
alarm = NETC_TMR_DEFAULT_ALARM;
|
||||
fiper = NETC_TMR_DEFAULT_FIPER;
|
||||
fiper_ctrl |= FIPER_CTRL_DIS(channel);
|
||||
} else {
|
||||
period.tv_sec = rq->perout.period.sec;
|
||||
period.tv_nsec = rq->perout.period.nsec;
|
||||
period_ns = timespec64_to_ns(&period);
|
||||
stime.tv_sec = rq->perout.start.sec;
|
||||
stime.tv_nsec = rq->perout.start.nsec;
|
||||
|
||||
tmr_emask |= TMR_TEVNET_PPEN(channel) | TMR_TEVENT_ALM1EN;
|
||||
tmr_ctrl |= TMR_CTRL_FS;
|
||||
tmr_ctrl &= ~TMR_ALARM1P;
|
||||
|
||||
/* fiper is set to desired FIPER interval in ns - TCLK_PERIOD
|
||||
* and should be an integer multiple of TCLK_PERIOD.
|
||||
*/
|
||||
fiper = div_u64(period_ns, priv->period_int) - 1;
|
||||
fiper = fiper * priv->period_int;
|
||||
fiper_pw = netc_timer_calculate_fiper_pulse_width(priv, fiper);
|
||||
fiper_ctrl &= ~(FIPER_CTRL_DIS(channel) | FIPER_CTRL_PW(channel));
|
||||
fiper_ctrl |= (fiper_pw << 8 * channel) & FIPER_CTRL_PW(channel);
|
||||
|
||||
/* alarm must be an integer multiple of TCLK_PERIOD in order
|
||||
* to get correct result. In addtion, In FS mode the alarm
|
||||
* trigger is used as an indication to the fiper start down
|
||||
* counting. Only TMR_ALARM1 supports this mode.
|
||||
*/
|
||||
alarm = timespec64_to_ns(&stime);
|
||||
cur_time = netc_timer_cnt_read(priv);
|
||||
if (cur_time >= alarm) {
|
||||
dev_err(priv->dev, "Start time must greater than current time!\n");
|
||||
spin_unlock_irqrestore(&priv->lock, flags);
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
alarm = div_u64(alarm, priv->period_int);
|
||||
alarm = alarm * priv->period_int;
|
||||
}
|
||||
|
||||
netc_timer_write_reg(priv, NETC_TMR_CTRL, tmr_ctrl);
|
||||
netc_timer_write_reg(priv, NETC_TMR_TEMASK, tmr_emask);
|
||||
netc_timer_write_reg(priv, NETC_TMR_FIPER(channel), fiper);
|
||||
netc_timer_alarm_write(priv, alarm, 0);
|
||||
netc_timer_write_reg(priv, NETC_TMR_FIPER_CTRL, fiper_ctrl);
|
||||
|
||||
spin_unlock_irqrestore(&priv->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int netc_timer_enable(struct ptp_clock_info *ptp,
|
||||
struct ptp_clock_request *rq, int on)
|
||||
{
|
||||
struct netc_timer *priv;
|
||||
|
||||
priv = container_of(ptp, struct netc_timer, caps);
|
||||
|
||||
switch (rq->type) {
|
||||
case PTP_CLK_REQ_PEROUT:
|
||||
return net_timer_enable_perout(priv, rq, on);
|
||||
case PTP_CLK_REQ_PPS:
|
||||
return netc_timer_enable_pps(priv, rq, on);
|
||||
case PTP_CLK_REQ_EXTTS:
|
||||
/* TODO */
|
||||
default:
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
}
|
||||
|
||||
static const struct ptp_clock_info netc_timer_ptp_caps = {
|
||||
.owner = THIS_MODULE,
|
||||
.name = "NETC Timer PTP clock",
|
||||
.max_adj = 1000000,
|
||||
.n_alarm = 2,
|
||||
.n_ext_ts = 2,
|
||||
.n_per_out = 3,
|
||||
.n_pins = 0,
|
||||
.pps = 1,
|
||||
.adjfine = netc_timer_adjfine,
|
||||
.adjtime = netc_timer_adjtime,
|
||||
.gettimex64 = netc_timer_gettimex64,
|
||||
.settime64 = netc_timer_settime64,
|
||||
.enable = netc_timer_enable,
|
||||
};
|
||||
|
||||
int netc_timer_get_phc_index(int domain, unsigned int bus, unsigned int devfn)
|
||||
{
|
||||
struct pci_dev *timer_pdev;
|
||||
struct netc_timer *priv;
|
||||
|
||||
timer_pdev = pci_get_domain_bus_and_slot(domain, bus, devfn);
|
||||
if (!timer_pdev)
|
||||
return -EINVAL;
|
||||
|
||||
priv = pci_get_drvdata(timer_pdev);
|
||||
if (!priv)
|
||||
return -EINVAL;
|
||||
|
||||
return priv->phc_index;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(netc_timer_get_phc_index);
|
||||
|
||||
static int netc_timer_init(struct netc_timer *priv)
|
||||
{
|
||||
struct device_node *node = priv->dev->of_node;
|
||||
u32 tmr_ctrl, alarm_ctrl, fiper_ctrl;
|
||||
struct timespec64 now;
|
||||
unsigned long flags;
|
||||
int i, err;
|
||||
u64 ns;
|
||||
|
||||
priv->caps = netc_timer_ptp_caps;
|
||||
|
||||
if (of_property_read_u32(node, "fsl,clk-select", &priv->clk_select))
|
||||
priv->clk_select = NETC_TMR_SYSTEM_CLK;
|
||||
|
||||
/* Check whether the clock source is valid */
|
||||
if (priv->clk_select != NETC_TMR_SYSTEM_CLK &&
|
||||
priv->clk_select != NETC_TMR_CCM_TIMER1 &&
|
||||
priv->clk_select != NETC_TMR_EXT_OSC) {
|
||||
dev_err(priv->dev, "Wrong clock source %d\n", priv->clk_select);
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Get the output clock division prescale factor, it must be an even value. */
|
||||
if (of_property_read_u32(node, "fsl,oclk-prsc", &priv->oclk_prsc))
|
||||
priv->oclk_prsc = NETC_TMR_DEFAULT_PRSC;
|
||||
if (priv->oclk_prsc % 2) {
|
||||
dev_warn(priv->dev, "PRSC_OCK should be an even value (PRSC_OCK: %d -> %d)\n",
|
||||
priv->oclk_prsc, priv->oclk_prsc + 1);
|
||||
priv->oclk_prsc += 1;
|
||||
}
|
||||
|
||||
err = netc_timer_get_clk_config(priv);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
alarm_ctrl = ALARM_CTRL_PG(0) | ALARM_CTRL_PG(1);
|
||||
|
||||
spin_lock_init(&priv->lock);
|
||||
spin_lock_irqsave(&priv->lock, flags);
|
||||
|
||||
/* Software must enable timer first and the clock selected must be
|
||||
* active, otherwise, the registers which are in the timer clock
|
||||
* domain are not accesdible.
|
||||
*/
|
||||
tmr_ctrl = (priv->clk_select & TMR_CTRL_CK_SEL) | TMR_CTRL_TE;
|
||||
netc_timer_write_reg(priv, NETC_TMR_CTRL, tmr_ctrl);
|
||||
|
||||
/* Output FIPER pulse clock (TMR_GCLK) is generated by dividing the
|
||||
* input clock of Timer by priv->oclk_prsc. For example, if input
|
||||
* clock of Timer is 200MHz, and priv->oclk_prsc is 2, then TMR_GCLK
|
||||
* is 100MHz.
|
||||
*/
|
||||
netc_timer_write_reg(priv, NETC_TMR_PRSC, priv->oclk_prsc);
|
||||
netc_timer_write_reg(priv, NETC_TMR_ALARM_CTRL, alarm_ctrl);
|
||||
fiper_ctrl = netc_timer_read_reg(priv, NETC_TMR_FIPER_CTRL);
|
||||
for (i = 0; i < NETC_TMR_FIPER_NUM; i++)
|
||||
fiper_ctrl |= FIPER_CTRL_DIS(i);
|
||||
netc_timer_write_reg(priv, NETC_TMR_FIPER_CTRL, fiper_ctrl);
|
||||
|
||||
ktime_get_real_ts64(&now);
|
||||
ns = timespec64_to_ns(&now);
|
||||
netc_timer_cnt_write(priv, ns);
|
||||
|
||||
tmr_ctrl |= ((priv->period_int << 16) & TMR_CTRL_TCLK_PERIOD);
|
||||
netc_timer_write_reg(priv, NETC_TMR_ADD, priv->period_frac);
|
||||
netc_timer_write_reg(priv, NETC_TMR_CTRL, tmr_ctrl);
|
||||
|
||||
spin_unlock_irqrestore(&priv->lock, flags);
|
||||
|
||||
priv->clock = ptp_clock_register(&priv->caps, priv->dev);
|
||||
if (IS_ERR(priv->clock))
|
||||
return PTR_ERR(priv->clock);
|
||||
|
||||
priv->phc_index = ptp_clock_index(priv->clock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void netc_timer_deinit(struct netc_timer *priv)
|
||||
{
|
||||
unsigned long flags;
|
||||
u32 fiper_ctrl;
|
||||
int i;
|
||||
|
||||
spin_lock_irqsave(&priv->lock, flags);
|
||||
|
||||
netc_timer_write_reg(priv, NETC_TMR_TEMASK, 0);
|
||||
netc_timer_alarm_write(priv, NETC_TMR_DEFAULT_ALARM, 0);
|
||||
fiper_ctrl = netc_timer_read_reg(priv, NETC_TMR_FIPER_CTRL);
|
||||
for (i = 0; i < NETC_TMR_FIPER_NUM; i++) {
|
||||
netc_timer_write_reg(priv, NETC_TMR_FIPER(i),
|
||||
NETC_TMR_DEFAULT_FIPER);
|
||||
fiper_ctrl |= FIPER_CTRL_DIS(i);
|
||||
}
|
||||
netc_timer_write_reg(priv, NETC_TMR_FIPER_CTRL, fiper_ctrl);
|
||||
|
||||
spin_unlock_irqrestore(&priv->lock, flags);
|
||||
}
|
||||
|
||||
static int netc_timer_probe(struct pci_dev *pdev,
|
||||
const struct pci_device_id *id)
|
||||
{
|
||||
struct platform_device *ierb_pdev;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct netc_timer *priv;
|
||||
int err, len, n;
|
||||
|
||||
err = netc_ierb_get_init_status();
|
||||
if (err) {
|
||||
if (err != -EPROBE_DEFER)
|
||||
dev_err(dev, "Can't get IERB init status: %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
err = pci_enable_device_mem(pdev);
|
||||
if (err)
|
||||
return dev_err_probe(dev, err, "device enable failed\n");
|
||||
|
||||
err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
|
||||
if (err) {
|
||||
dev_err(dev, "DMA configuration failed: 0x%x\n", err);
|
||||
goto disable_dev;
|
||||
}
|
||||
|
||||
err = pci_request_mem_regions(pdev, KBUILD_MODNAME);
|
||||
if (err) {
|
||||
dev_err(dev, "pci_request_regions failed err=%d\n", err);
|
||||
goto disable_dev;
|
||||
}
|
||||
|
||||
pci_set_master(pdev);
|
||||
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv) {
|
||||
err = -ENOMEM;
|
||||
goto release_mem_regions;
|
||||
}
|
||||
priv->dev = dev;
|
||||
priv->pci_dev = pdev;
|
||||
priv->ierb_pdev = ierb_pdev;
|
||||
priv->phc_index = -1; /* initialize it as an invalid index */
|
||||
|
||||
len = pci_resource_len(pdev, NETC_TMR_REGS_BAR);
|
||||
priv->base = ioremap(pci_resource_start(pdev, NETC_TMR_REGS_BAR), len);
|
||||
if (!priv->base) {
|
||||
err = -ENXIO;
|
||||
dev_err(dev, "ioremap() failed\n");
|
||||
goto free_priv;
|
||||
}
|
||||
|
||||
n = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
|
||||
if (n != 1) {
|
||||
err = -EPERM;
|
||||
goto unmap_resource;
|
||||
}
|
||||
priv->irq = pci_irq_vector(pdev, 0);
|
||||
snprintf(priv->irq_name, sizeof(priv->irq_name),
|
||||
"ptp-netc %s", pci_name(pdev));
|
||||
err = request_irq(priv->irq, netc_timer_isr, 0, priv->irq_name, priv);
|
||||
if (err) {
|
||||
dev_err(dev, "request_irq() failed!\n");
|
||||
goto free_irq_vectors;
|
||||
}
|
||||
|
||||
err = netc_timer_init(priv);
|
||||
if (err) {
|
||||
dev_err(dev, "NETC Timer initialization failed\n");
|
||||
goto free_irq;
|
||||
}
|
||||
pci_set_drvdata(pdev, priv);
|
||||
|
||||
return 0;
|
||||
|
||||
free_irq:
|
||||
free_irq(priv->irq, priv);
|
||||
free_irq_vectors:
|
||||
pci_free_irq_vectors(pdev);
|
||||
unmap_resource:
|
||||
iounmap(priv->base);
|
||||
free_priv:
|
||||
kfree(priv);
|
||||
release_mem_regions:
|
||||
pci_release_mem_regions(pdev);
|
||||
disable_dev:
|
||||
pci_disable_device(pdev);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static void netc_timer_remove(struct pci_dev *pdev)
|
||||
{
|
||||
struct netc_timer *priv = pci_get_drvdata(pdev);
|
||||
|
||||
netc_timer_deinit(priv);
|
||||
|
||||
ptp_clock_unregister(priv->clock);
|
||||
iounmap(priv->base);
|
||||
free_irq(priv->irq, priv);
|
||||
|
||||
pci_free_irq_vectors(pdev);
|
||||
kfree(priv);
|
||||
|
||||
pci_release_mem_regions(pdev);
|
||||
pci_disable_device(pdev);
|
||||
}
|
||||
|
||||
static const struct pci_device_id netc_timer_id_table[] = {
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_NXP2, PCI_DEVICE_ID_NXP2_NETC_TIMER) },
|
||||
{ 0, } /* End of table. */
|
||||
};
|
||||
MODULE_DEVICE_TABLE(pci, netc_timer_id_table);
|
||||
|
||||
static struct pci_driver netc_timer_driver = {
|
||||
.name = KBUILD_MODNAME,
|
||||
.id_table = netc_timer_id_table,
|
||||
.probe = netc_timer_probe,
|
||||
.remove = netc_timer_remove,
|
||||
};
|
||||
module_pci_driver(netc_timer_driver);
|
||||
|
||||
MODULE_AUTHOR("Wei Fang <wei.fang@nxp.com>");
|
||||
MODULE_DESCRIPTION("NXP NETC Timer Driver");
|
||||
MODULE_LICENSE("Dual BSD/GPL");
|
||||
18
include/linux/fsl/ptp_netc.h
Normal file
18
include/linux/fsl/ptp_netc.h
Normal file
|
|
@ -0,0 +1,18 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
|
||||
/* Copyright 2023 NXP
|
||||
* Copyright (c) 2023 Wei Fang <wei.fang@nxp.com>
|
||||
*/
|
||||
#ifndef _PTP_NETC_H
|
||||
#define _PTP_NETC_H
|
||||
|
||||
#if IS_ENABLED(CONFIG_PTP_1588_CLOCK_NETC)
|
||||
int netc_timer_get_phc_index(int domain, unsigned int bus, unsigned int devfn);
|
||||
#else
|
||||
static inline int netc_timer_get_phc_index(int domain, unsigned int bus,
|
||||
unsigned int devfn)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user