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https://github.com/nxp-imx/linux-imx.git
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lguest: use the PCI console device's emerg_wr for early boot messages.
This involves manually checking the console device (which is always in slot 1 of bus 0) and using the window in VIRTIO_PCI_CAP_PCI_CFG to program it (as we can't map the BAR yet). We could in fact do this much earlier, but we wait for the first write from the virtio_cons_early_init() facility. Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
This commit is contained in:
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713e3f7224
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@ -57,6 +57,7 @@
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#include <linux/pm.h>
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#include <linux/pm.h>
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#include <linux/export.h>
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#include <linux/export.h>
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#include <linux/pci.h>
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#include <linux/pci.h>
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#include <linux/virtio_pci.h>
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#include <asm/acpi.h>
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#include <asm/acpi.h>
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#include <asm/apic.h>
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#include <asm/apic.h>
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#include <asm/lguest.h>
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#include <asm/lguest.h>
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@ -74,6 +75,7 @@
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#include <asm/reboot.h> /* for struct machine_ops */
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#include <asm/reboot.h> /* for struct machine_ops */
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#include <asm/kvm_para.h>
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#include <asm/kvm_para.h>
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#include <asm/pci_x86.h>
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#include <asm/pci_x86.h>
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#include <asm/pci-direct.h>
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/*G:010
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/*G:010
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* Welcome to the Guest!
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* Welcome to the Guest!
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@ -1202,25 +1204,145 @@ static __init char *lguest_memory_setup(void)
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return "LGUEST";
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return "LGUEST";
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}
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}
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/* Offset within PCI config space of BAR access capability. */
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static int console_cfg_offset = 0;
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static int console_access_cap;
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/* Set up so that we access off in bar0 (on bus 0, device 1, function 0) */
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static void set_cfg_window(u32 cfg_offset, u32 off)
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{
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write_pci_config_byte(0, 1, 0,
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cfg_offset + offsetof(struct virtio_pci_cap, bar),
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0);
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write_pci_config(0, 1, 0,
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cfg_offset + offsetof(struct virtio_pci_cap, length),
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4);
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write_pci_config(0, 1, 0,
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cfg_offset + offsetof(struct virtio_pci_cap, offset),
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off);
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}
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static u32 read_bar_via_cfg(u32 cfg_offset, u32 off)
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{
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set_cfg_window(cfg_offset, off);
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return read_pci_config(0, 1, 0,
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cfg_offset + sizeof(struct virtio_pci_cap));
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}
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static void write_bar_via_cfg(u32 cfg_offset, u32 off, u32 val)
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{
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set_cfg_window(cfg_offset, off);
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write_pci_config(0, 1, 0,
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cfg_offset + sizeof(struct virtio_pci_cap), val);
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}
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static void probe_pci_console(void)
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{
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u8 cap, common_cap = 0, device_cap = 0;
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/* Offsets within BAR0 */
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u32 common_offset, device_offset;
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/* Avoid recursive printk into here. */
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console_cfg_offset = -1;
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if (!early_pci_allowed()) {
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printk(KERN_ERR "lguest: early PCI access not allowed!\n");
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return;
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}
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/* We expect a console PCI device at BUS0, slot 1. */
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if (read_pci_config(0, 1, 0, 0) != 0x10431AF4) {
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printk(KERN_ERR "lguest: PCI device is %#x!\n",
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read_pci_config(0, 1, 0, 0));
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return;
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}
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/* Find the capabilities we need (must be in bar0) */
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cap = read_pci_config_byte(0, 1, 0, PCI_CAPABILITY_LIST);
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while (cap) {
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u8 vndr = read_pci_config_byte(0, 1, 0, cap);
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if (vndr == PCI_CAP_ID_VNDR) {
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u8 type, bar;
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u32 offset;
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type = read_pci_config_byte(0, 1, 0,
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cap + offsetof(struct virtio_pci_cap, cfg_type));
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bar = read_pci_config_byte(0, 1, 0,
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cap + offsetof(struct virtio_pci_cap, bar));
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offset = read_pci_config(0, 1, 0,
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cap + offsetof(struct virtio_pci_cap, offset));
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switch (type) {
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case VIRTIO_PCI_CAP_COMMON_CFG:
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if (bar == 0) {
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common_cap = cap;
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common_offset = offset;
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}
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break;
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case VIRTIO_PCI_CAP_DEVICE_CFG:
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if (bar == 0) {
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device_cap = cap;
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device_offset = offset;
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}
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break;
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case VIRTIO_PCI_CAP_PCI_CFG:
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console_access_cap = cap;
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break;
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}
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}
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cap = read_pci_config_byte(0, 1, 0, cap + PCI_CAP_LIST_NEXT);
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}
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if (!common_cap || !device_cap || !console_access_cap) {
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printk(KERN_ERR "lguest: No caps (%u/%u/%u) in console!\n",
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common_cap, device_cap, console_access_cap);
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return;
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}
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#define write_common_config(reg, val) \
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write_bar_via_cfg(console_access_cap, \
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common_offset+offsetof(struct virtio_pci_common_cfg,reg),\
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val)
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#define read_common_config(reg) \
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read_bar_via_cfg(console_access_cap, \
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common_offset+offsetof(struct virtio_pci_common_cfg,reg))
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/* Check features: they must offer EMERG_WRITE */
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write_common_config(device_feature_select, 0);
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if (!(read_common_config(device_feature)
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& (1 << VIRTIO_CONSOLE_F_EMERG_WRITE))) {
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printk(KERN_ERR "lguest: console missing EMERG_WRITE\n");
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return;
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}
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console_cfg_offset = device_offset;
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}
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/*
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/*
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* We will eventually use the virtio console device to produce console output,
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* We will eventually use the virtio console device to produce console output,
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* but before that is set up we use LHCALL_NOTIFY on normal memory to produce
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* but before that is set up we use the virtio PCI console's backdoor mmio
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* console output.
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* access and the "emergency" write facility (which is legal even before the
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* device is configured).
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*/
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*/
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static __init int early_put_chars(u32 vtermno, const char *buf, int count)
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static __init int early_put_chars(u32 vtermno, const char *buf, int count)
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{
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{
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char scratch[17];
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/* If we couldn't find PCI console, forget it. */
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unsigned int len = count;
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if (console_cfg_offset < 0)
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return count;
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/* We use a nul-terminated string, so we make a copy. Icky, huh? */
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if (unlikely(!console_cfg_offset)) {
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if (len > sizeof(scratch) - 1)
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probe_pci_console();
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len = sizeof(scratch) - 1;
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if (console_cfg_offset < 0)
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scratch[len] = '\0';
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return count;
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memcpy(scratch, buf, len);
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}
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hcall(LHCALL_NOTIFY, __pa(scratch), 0, 0, 0);
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/* This routine returns the number of bytes actually written. */
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write_bar_via_cfg(console_access_cap,
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return len;
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console_cfg_offset
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+ offsetof(struct virtio_console_config, emerg_wr),
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buf[0]);
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return 1;
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}
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}
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/*
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/*
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