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dt-bindings: PCI: Convert Rockchip RK3399 PCIe to DT schema
Convert the Rockchip RK3399 PCIe Host/Endpoint controller to DT schema format. Like most dual mode PCI controllers, we need to split the schema into common, host and endpoint schemas. Link: https://lore.kernel.org/r/20221219191209.1975834-1-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Rob Herring
parent
eb2b4ecf72
commit
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie-common.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Rockchip AXI PCIe Bridge Common Properties
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maintainers:
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- Shawn Lin <shawn.lin@rock-chips.com>
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properties:
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reg:
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maxItems: 2
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clocks:
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maxItems: 4
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clock-names:
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items:
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- const: aclk
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- const: aclk-perf
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- const: hclk
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- const: pm
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num-lanes:
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maximum: 4
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phys:
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oneOf:
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- maxItems: 1
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- maxItems: 4
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phy-names:
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oneOf:
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- const: pcie-phy
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- items:
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- const: pcie-phy-0
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- const: pcie-phy-1
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- const: pcie-phy-2
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- const: pcie-phy-3
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resets:
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maxItems: 7
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reset-names:
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items:
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- const: core
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- const: mgmt
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- const: mgmt-sticky
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- const: pipe
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- const: pm
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- const: pclk
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- const: aclk
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required:
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- compatible
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- reg
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- reg-names
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- clocks
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- clock-names
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- phys
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- phy-names
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- resets
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- reset-names
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additionalProperties: true
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...
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie-ep.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Rockchip AXI PCIe Endpoint
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maintainers:
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- Shawn Lin <shawn.lin@rock-chips.com>
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allOf:
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- $ref: /schemas/pci/pci-ep.yaml#
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- $ref: rockchip,rk3399-pcie-common.yaml#
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properties:
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compatible:
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const: rockchip,rk3399-pcie-ep
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reg: true
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reg-names:
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items:
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- const: apb-base
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- const: mem-base
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rockchip,max-outbound-regions:
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description: Maximum number of outbound regions
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 32
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default: 32
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required:
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- rockchip,max-outbound-regions
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/rk3399-cru.h>
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie-ep@f8000000 {
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compatible = "rockchip,rk3399-pcie-ep";
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reg = <0x0 0xfd000000 0x0 0x1000000>, <0x0 0x80000000 0x0 0x20000>;
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reg-names = "apb-base", "mem-base";
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clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
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<&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
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clock-names = "aclk", "aclk-perf",
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"hclk", "pm";
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max-functions = /bits/ 8 <8>;
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num-lanes = <4>;
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resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
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<&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
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<&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
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reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
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"pm", "pclk", "aclk";
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phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;
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phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";
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rockchip,max-outbound-regions = <16>;
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};
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};
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...
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132
Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie.yaml
Normal file
132
Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie.yaml
Normal file
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@ -0,0 +1,132 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Rockchip AXI PCIe Root Port Bridge Host
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maintainers:
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- Shawn Lin <shawn.lin@rock-chips.com>
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allOf:
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- $ref: /schemas/pci/pci-bus.yaml#
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- $ref: rockchip,rk3399-pcie-common.yaml#
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properties:
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compatible:
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const: rockchip,rk3399-pcie
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reg: true
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reg-names:
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items:
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- const: axi-base
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- const: apb-base
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interrupts:
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maxItems: 3
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interrupt-names:
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items:
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- const: sys
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- const: legacy
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- const: client
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aspm-no-l0s:
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description: This property is needed if using 24MHz OSC for RC's PHY.
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ep-gpios:
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description: pre-reset GPIO
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vpcie12v-supply:
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description: The 12v regulator to use for PCIe.
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vpcie3v3-supply:
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description: The 3.3v regulator to use for PCIe.
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vpcie1v8-supply:
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description: The 1.8v regulator to use for PCIe.
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vpcie0v9-supply:
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description: The 0.9v regulator to use for PCIe.
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interrupt-controller:
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type: object
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additionalProperties: false
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properties:
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'#address-cells':
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const: 0
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'#interrupt-cells':
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const: 1
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interrupt-controller: true
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required:
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- ranges
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- "#interrupt-cells"
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- interrupts
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- interrupt-controller
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- interrupt-map
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- interrupt-map-mask
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- msi-map
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/rk3399-cru.h>
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie@f8000000 {
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compatible = "rockchip,rk3399-pcie";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
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<&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
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clock-names = "aclk", "aclk-perf",
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"hclk", "pm";
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interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "sys", "legacy", "client";
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ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
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ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
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0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
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num-lanes = <4>;
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msi-map = <0x0 &its 0x0 0x1000>;
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reg = <0x0 0xf8000000 0x0 0x2000000>, <0x0 0xfd000000 0x0 0x1000000>;
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reg-names = "axi-base", "apb-base";
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resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
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<&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
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<&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
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reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
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"pm", "pclk", "aclk";
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/* deprecated legacy PHY model */
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phys = <&pcie_phy>;
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phy-names = "pcie-phy";
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pinctrl-names = "default";
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pinctrl-0 = <&pcie_clkreq>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie0_intc 0>,
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<0 0 0 2 &pcie0_intc 1>,
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<0 0 0 3 &pcie0_intc 2>,
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<0 0 0 4 &pcie0_intc 3>;
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pcie0_intc: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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};
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...
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@ -1,62 +0,0 @@
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* Rockchip AXI PCIe Endpoint Controller DT description
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Required properties:
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- compatible: Should contain "rockchip,rk3399-pcie-ep"
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- reg: Two register ranges as listed in the reg-names property
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- reg-names: Must include the following names
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- "apb-base"
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- "mem-base"
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- clocks: Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Must include the following entries:
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- "aclk"
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- "aclk-perf"
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- "hclk"
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- "pm"
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- resets: Must contain seven entries for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names: Must include the following names
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- "core"
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- "mgmt"
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- "mgmt-sticky"
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- "pipe"
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- "pm"
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- "aclk"
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- "pclk"
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- pinctrl-names : The pin control state names
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- pinctrl-0: The "default" pinctrl state
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- phys: Must contain an phandle to a PHY for each entry in phy-names.
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- phy-names: Must include 4 entries for all 4 lanes even if some of
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them won't be used for your cases. Entries are of the form "pcie-phy-N":
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where N ranges from 0 to 3.
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(see example below and you MUST also refer to ../phy/rockchip-pcie-phy.txt
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for changing the #phy-cells of phy node to support it)
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- rockchip,max-outbound-regions: Maximum number of outbound regions
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Optional Property:
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- num-lanes: number of lanes to use
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- max-functions: Maximum number of functions that can be configured (default 1).
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pcie0-ep: pcie@f8000000 {
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compatible = "rockchip,rk3399-pcie-ep";
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#address-cells = <3>;
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#size-cells = <2>;
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rockchip,max-outbound-regions = <16>;
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clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
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<&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
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clock-names = "aclk", "aclk-perf",
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"hclk", "pm";
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max-functions = /bits/ 8 <8>;
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num-lanes = <4>;
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reg = <0x0 0xfd000000 0x0 0x1000000>, <0x0 0x80000000 0x0 0x20000>;
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reg-names = "apb-base", "mem-base";
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resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
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<&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
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||||||
<&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
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reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
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"pm", "pclk", "aclk";
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||||||
phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;
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|
||||||
phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";
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pinctrl-names = "default";
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pinctrl-0 = <&pcie_clkreq>;
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};
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@ -1,135 +0,0 @@
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* Rockchip AXI PCIe Root Port Bridge DT description
|
|
||||||
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|
||||||
Required properties:
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- #address-cells: Address representation for root ports, set to <3>
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||||||
- #size-cells: Size representation for root ports, set to <2>
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- #interrupt-cells: specifies the number of cells needed to encode an
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interrupt source. The value must be 1.
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- compatible: Should contain "rockchip,rk3399-pcie"
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|
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- reg: Two register ranges as listed in the reg-names property
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|
||||||
- reg-names: Must include the following names
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- "axi-base"
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- "apb-base"
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- clocks: Must contain an entry for each entry in clock-names.
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|
||||||
See ../clocks/clock-bindings.txt for details.
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|
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- clock-names: Must include the following entries:
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- "aclk"
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- "aclk-perf"
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- "hclk"
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||||||
- "pm"
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|
||||||
- msi-map: Maps a Requester ID to an MSI controller and associated
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|
||||||
msi-specifier data. See ./pci-msi.txt
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|
||||||
- interrupts: Three interrupt entries must be specified.
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|
||||||
- interrupt-names: Must include the following names
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|
||||||
- "sys"
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|
||||||
- "legacy"
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|
||||||
- "client"
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|
||||||
- resets: Must contain seven entries for each entry in reset-names.
|
|
||||||
See ../reset/reset.txt for details.
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|
||||||
- reset-names: Must include the following names
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|
||||||
- "core"
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|
||||||
- "mgmt"
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|
||||||
- "mgmt-sticky"
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|
||||||
- "pipe"
|
|
||||||
- "pm"
|
|
||||||
- "aclk"
|
|
||||||
- "pclk"
|
|
||||||
- pinctrl-names : The pin control state names
|
|
||||||
- pinctrl-0: The "default" pinctrl state
|
|
||||||
- #interrupt-cells: specifies the number of cells needed to encode an
|
|
||||||
interrupt source. The value must be 1.
|
|
||||||
- interrupt-map-mask and interrupt-map: standard PCI properties
|
|
||||||
|
|
||||||
Required properties for legacy PHY model (deprecated):
|
|
||||||
- phys: From PHY bindings: Phandle for the Generic PHY for PCIe.
|
|
||||||
- phy-names: MUST be "pcie-phy".
|
|
||||||
|
|
||||||
Required properties for per-lane PHY model (preferred):
|
|
||||||
- phys: Must contain an phandle to a PHY for each entry in phy-names.
|
|
||||||
- phy-names: Must include 4 entries for all 4 lanes even if some of
|
|
||||||
them won't be used for your cases. Entries are of the form "pcie-phy-N":
|
|
||||||
where N ranges from 0 to 3.
|
|
||||||
(see example below and you MUST also refer to ../phy/rockchip-pcie-phy.txt
|
|
||||||
for changing the #phy-cells of phy node to support it)
|
|
||||||
|
|
||||||
Optional Property:
|
|
||||||
- aspm-no-l0s: RC won't support ASPM L0s. This property is needed if
|
|
||||||
using 24MHz OSC for RC's PHY.
|
|
||||||
- ep-gpios: contain the entry for pre-reset GPIO
|
|
||||||
- num-lanes: number of lanes to use
|
|
||||||
- vpcie12v-supply: The phandle to the 12v regulator to use for PCIe.
|
|
||||||
- vpcie3v3-supply: The phandle to the 3.3v regulator to use for PCIe.
|
|
||||||
- vpcie1v8-supply: The phandle to the 1.8v regulator to use for PCIe.
|
|
||||||
- vpcie0v9-supply: The phandle to the 0.9v regulator to use for PCIe.
|
|
||||||
|
|
||||||
*Interrupt controller child node*
|
|
||||||
The core controller provides a single interrupt for legacy INTx. The PCIe node
|
|
||||||
should contain an interrupt controller node as a target for the PCI
|
|
||||||
'interrupt-map' property. This node represents the domain at which the four
|
|
||||||
INTx interrupts are decoded and routed.
|
|
||||||
|
|
||||||
|
|
||||||
Required properties for Interrupt controller child node:
|
|
||||||
- interrupt-controller: identifies the node as an interrupt controller
|
|
||||||
- #address-cells: specifies the number of cells needed to encode an
|
|
||||||
address. The value must be 0.
|
|
||||||
- #interrupt-cells: specifies the number of cells needed to encode an
|
|
||||||
interrupt source. The value must be 1.
|
|
||||||
|
|
||||||
Example:
|
|
||||||
|
|
||||||
pcie0: pcie@f8000000 {
|
|
||||||
compatible = "rockchip,rk3399-pcie";
|
|
||||||
#address-cells = <3>;
|
|
||||||
#size-cells = <2>;
|
|
||||||
clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
|
|
||||||
<&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
|
|
||||||
clock-names = "aclk", "aclk-perf",
|
|
||||||
"hclk", "pm";
|
|
||||||
bus-range = <0x0 0x1>;
|
|
||||||
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
||||||
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
||||||
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
||||||
interrupt-names = "sys", "legacy", "client";
|
|
||||||
assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
|
|
||||||
assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
|
|
||||||
assigned-clock-rates = <100000000>;
|
|
||||||
ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
|
|
||||||
ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
|
|
||||||
0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
|
|
||||||
num-lanes = <4>;
|
|
||||||
msi-map = <0x0 &its 0x0 0x1000>;
|
|
||||||
reg = <0x0 0xf8000000 0x0 0x2000000>, <0x0 0xfd000000 0x0 0x1000000>;
|
|
||||||
reg-names = "axi-base", "apb-base";
|
|
||||||
resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
|
|
||||||
<&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
|
|
||||||
<&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
|
|
||||||
reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
|
|
||||||
"pm", "pclk", "aclk";
|
|
||||||
/* deprecated legacy PHY model */
|
|
||||||
phys = <&pcie_phy>;
|
|
||||||
phy-names = "pcie-phy";
|
|
||||||
pinctrl-names = "default";
|
|
||||||
pinctrl-0 = <&pcie_clkreq>;
|
|
||||||
#interrupt-cells = <1>;
|
|
||||||
interrupt-map-mask = <0 0 0 7>;
|
|
||||||
interrupt-map = <0 0 0 1 &pcie0_intc 0>,
|
|
||||||
<0 0 0 2 &pcie0_intc 1>,
|
|
||||||
<0 0 0 3 &pcie0_intc 2>,
|
|
||||||
<0 0 0 4 &pcie0_intc 3>;
|
|
||||||
pcie0_intc: interrupt-controller {
|
|
||||||
interrupt-controller;
|
|
||||||
#address-cells = <0>;
|
|
||||||
#interrupt-cells = <1>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
pcie0: pcie@f8000000 {
|
|
||||||
...
|
|
||||||
|
|
||||||
/* preferred per-lane PHY model */
|
|
||||||
phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;
|
|
||||||
phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";
|
|
||||||
|
|
||||||
...
|
|
||||||
};
|
|
||||||
|
|
@ -16307,7 +16307,7 @@ M: Shawn Lin <shawn.lin@rock-chips.com>
|
||||||
L: linux-pci@vger.kernel.org
|
L: linux-pci@vger.kernel.org
|
||||||
L: linux-rockchip@lists.infradead.org
|
L: linux-rockchip@lists.infradead.org
|
||||||
S: Maintained
|
S: Maintained
|
||||||
F: Documentation/devicetree/bindings/pci/rockchip-pcie*
|
F: Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie*
|
||||||
F: drivers/pci/controller/pcie-rockchip*
|
F: drivers/pci/controller/pcie-rockchip*
|
||||||
|
|
||||||
PCIE DRIVER FOR SOCIONEXT UNIPHIER
|
PCIE DRIVER FOR SOCIONEXT UNIPHIER
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue
Block a user