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ASoC: meson: axg-fifo: use FIELD helpers

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[ Upstream commit 9e6f39535c ]

Use FIELD_GET() and FIELD_PREP() helpers instead of doing it manually.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://msgid.link/r/20240227150826.573581-1-jbrunet@baylibre.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Stable-dep-of: b11d26660d ("ASoC: meson: axg-fifo: use threaded irq to check periods")
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Jerome Brunet 2024-02-27 16:08:25 +01:00 committed by Greg Kroah-Hartman
parent 0ba4fd4599
commit af8e6bbf66
4 changed files with 31 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
sound/soc/meson/axg-fifo.c
View File

@ -3,6 +3,7 @@
// Copyright (c) 2018 BayLibre, SAS. // Copyright (c) 2018 BayLibre, SAS.
// Author: Jerome Brunet <jbrunet@baylibre.com> // Author: Jerome Brunet <jbrunet@baylibre.com>
#include <linux/bitfield.h>
#include <linux/clk.h> #include <linux/clk.h>
#include <linux/of_irq.h> #include <linux/of_irq.h>
#include <linux/of_platform.h> #include <linux/of_platform.h>
@ -145,8 +146,8 @@ int axg_fifo_pcm_hw_params(struct snd_soc_component *component,
/* Enable irq if necessary */ /* Enable irq if necessary */
irq_en = runtime->no_period_wakeup ? 0 : FIFO_INT_COUNT_REPEAT; irq_en = runtime->no_period_wakeup ? 0 : FIFO_INT_COUNT_REPEAT;
regmap_update_bits(fifo->map, FIFO_CTRL0, regmap_update_bits(fifo->map, FIFO_CTRL0,
CTRL0_INT_EN(FIFO_INT_COUNT_REPEAT), CTRL0_INT_EN,
CTRL0_INT_EN(irq_en)); FIELD_PREP(CTRL0_INT_EN, irq_en));
return 0; return 0;
} }
@ -176,9 +177,9 @@ int axg_fifo_pcm_hw_free(struct snd_soc_component *component,
{ {
struct axg_fifo *fifo = axg_fifo_data(ss); struct axg_fifo *fifo = axg_fifo_data(ss);
/* Disable the block count irq */ /* Disable irqs */
regmap_update_bits(fifo->map, FIFO_CTRL0, regmap_update_bits(fifo->map, FIFO_CTRL0,
CTRL0_INT_EN(FIFO_INT_COUNT_REPEAT), 0); CTRL0_INT_EN, 0);
return 0; return 0;
} }
@ -187,13 +188,13 @@ EXPORT_SYMBOL_GPL(axg_fifo_pcm_hw_free);
static void axg_fifo_ack_irq(struct axg_fifo *fifo, u8 mask) static void axg_fifo_ack_irq(struct axg_fifo *fifo, u8 mask)
{ {
regmap_update_bits(fifo->map, FIFO_CTRL1, regmap_update_bits(fifo->map, FIFO_CTRL1,
CTRL1_INT_CLR(FIFO_INT_MASK), CTRL1_INT_CLR,
CTRL1_INT_CLR(mask)); FIELD_PREP(CTRL1_INT_CLR, mask));
/* Clear must also be cleared */ /* Clear must also be cleared */
regmap_update_bits(fifo->map, FIFO_CTRL1, regmap_update_bits(fifo->map, FIFO_CTRL1,
CTRL1_INT_CLR(FIFO_INT_MASK), CTRL1_INT_CLR,
0); FIELD_PREP(CTRL1_INT_CLR, 0));
} }
static irqreturn_t axg_fifo_pcm_irq_block(int irq, void *dev_id) static irqreturn_t axg_fifo_pcm_irq_block(int irq, void *dev_id)
@ -204,7 +205,7 @@ static irqreturn_t axg_fifo_pcm_irq_block(int irq, void *dev_id)
regmap_read(fifo->map, FIFO_STATUS1, &status); regmap_read(fifo->map, FIFO_STATUS1, &status);
status = STATUS1_INT_STS(status) & FIFO_INT_MASK; status = FIELD_GET(STATUS1_INT_STS, status);
if (status & FIFO_INT_COUNT_REPEAT) if (status & FIFO_INT_COUNT_REPEAT)
snd_pcm_period_elapsed(ss); snd_pcm_period_elapsed(ss);
else else
@ -254,15 +255,15 @@ int axg_fifo_pcm_open(struct snd_soc_component *component,
/* Setup status2 so it reports the memory pointer */ /* Setup status2 so it reports the memory pointer */
regmap_update_bits(fifo->map, FIFO_CTRL1, regmap_update_bits(fifo->map, FIFO_CTRL1,
CTRL1_STATUS2_SEL_MASK, CTRL1_STATUS2_SEL,
CTRL1_STATUS2_SEL(STATUS2_SEL_DDR_READ)); FIELD_PREP(CTRL1_STATUS2_SEL, STATUS2_SEL_DDR_READ));
/* Make sure the dma is initially disabled */ /* Make sure the dma is initially disabled */
__dma_enable(fifo, false); __dma_enable(fifo, false);
/* Disable irqs until params are ready */ /* Disable irqs until params are ready */
regmap_update_bits(fifo->map, FIFO_CTRL0, regmap_update_bits(fifo->map, FIFO_CTRL0,
CTRL0_INT_EN(FIFO_INT_MASK), 0); CTRL0_INT_EN, 0);
/* Clear any pending interrupt */ /* Clear any pending interrupt */
axg_fifo_ack_irq(fifo, FIFO_INT_MASK); axg_fifo_ack_irq(fifo, FIFO_INT_MASK);

12
sound/soc/meson/axg-fifo.h
View File

@ -42,21 +42,19 @@ struct snd_soc_pcm_runtime;
#define FIFO_CTRL0 0x00 #define FIFO_CTRL0 0x00
#define CTRL0_DMA_EN BIT(31) #define CTRL0_DMA_EN BIT(31)
#define CTRL0_INT_EN(x) ((x) << 16) #define CTRL0_INT_EN GENMASK(23, 16)
#define CTRL0_SEL_MASK GENMASK(2, 0) #define CTRL0_SEL_MASK GENMASK(2, 0)
#define CTRL0_SEL_SHIFT 0 #define CTRL0_SEL_SHIFT 0
#define FIFO_CTRL1 0x04 #define FIFO_CTRL1 0x04
#define CTRL1_INT_CLR(x) ((x) << 0) #define CTRL1_INT_CLR GENMASK(7, 0)
#define CTRL1_STATUS2_SEL_MASK GENMASK(11, 8) #define CTRL1_STATUS2_SEL GENMASK(11, 8)
#define CTRL1_STATUS2_SEL(x) ((x) << 8)
#define STATUS2_SEL_DDR_READ 0 #define STATUS2_SEL_DDR_READ 0
#define CTRL1_FRDDR_DEPTH_MASK GENMASK(31, 24) #define CTRL1_FRDDR_DEPTH GENMASK(31, 24)
#define CTRL1_FRDDR_DEPTH(x) ((x) << 24)
#define FIFO_START_ADDR 0x08 #define FIFO_START_ADDR 0x08
#define FIFO_FINISH_ADDR 0x0c #define FIFO_FINISH_ADDR 0x0c
#define FIFO_INT_ADDR 0x10 #define FIFO_INT_ADDR 0x10
#define FIFO_STATUS1 0x14 #define FIFO_STATUS1 0x14
#define STATUS1_INT_STS(x) ((x) << 0) #define STATUS1_INT_STS GENMASK(7, 0)
#define FIFO_STATUS2 0x18 #define FIFO_STATUS2 0x18
#define FIFO_INIT_ADDR 0x24 #define FIFO_INIT_ADDR 0x24
#define FIFO_CTRL2 0x28 #define FIFO_CTRL2 0x28

5
sound/soc/meson/axg-frddr.c
View File

@ -7,6 +7,7 @@
* This driver implements the frontend playback DAI of AXG and G12A based SoCs * This driver implements the frontend playback DAI of AXG and G12A based SoCs
*/ */
#include <linux/bitfield.h>
#include <linux/clk.h> #include <linux/clk.h>
#include <linux/regmap.h> #include <linux/regmap.h>
#include <linux/module.h> #include <linux/module.h>
@ -59,8 +60,8 @@ static int axg_frddr_dai_hw_params(struct snd_pcm_substream *substream,
/* Trim the FIFO depth if the period is small to improve latency */ /* Trim the FIFO depth if the period is small to improve latency */
depth = min(period, fifo->depth); depth = min(period, fifo->depth);
val = (depth / AXG_FIFO_BURST) - 1; val = (depth / AXG_FIFO_BURST) - 1;
regmap_update_bits(fifo->map, FIFO_CTRL1, CTRL1_FRDDR_DEPTH_MASK, regmap_update_bits(fifo->map, FIFO_CTRL1, CTRL1_FRDDR_DEPTH,
CTRL1_FRDDR_DEPTH(val)); FIELD_PREP(CTRL1_FRDDR_DEPTH, val));
return 0; return 0;
} }

22
sound/soc/meson/axg-toddr.c
View File

@ -5,6 +5,7 @@
/* This driver implements the frontend capture DAI of AXG based SoCs */ /* This driver implements the frontend capture DAI of AXG based SoCs */
#include <linux/bitfield.h>
#include <linux/clk.h> #include <linux/clk.h>
#include <linux/regmap.h> #include <linux/regmap.h>
#include <linux/module.h> #include <linux/module.h>
@ -19,12 +20,9 @@
#define CTRL0_TODDR_EXT_SIGNED BIT(29) #define CTRL0_TODDR_EXT_SIGNED BIT(29)
#define CTRL0_TODDR_PP_MODE BIT(28) #define CTRL0_TODDR_PP_MODE BIT(28)
#define CTRL0_TODDR_SYNC_CH BIT(27) #define CTRL0_TODDR_SYNC_CH BIT(27)
#define CTRL0_TODDR_TYPE_MASK GENMASK(15, 13) #define CTRL0_TODDR_TYPE GENMASK(15, 13)
#define CTRL0_TODDR_TYPE(x) ((x) << 13) #define CTRL0_TODDR_MSB_POS GENMASK(12, 8)
#define CTRL0_TODDR_MSB_POS_MASK GENMASK(12, 8) #define CTRL0_TODDR_LSB_POS GENMASK(7, 3)
#define CTRL0_TODDR_MSB_POS(x) ((x) << 8)
#define CTRL0_TODDR_LSB_POS_MASK GENMASK(7, 3)
#define CTRL0_TODDR_LSB_POS(x) ((x) << 3)
#define CTRL1_TODDR_FORCE_FINISH BIT(25) #define CTRL1_TODDR_FORCE_FINISH BIT(25)
#define CTRL1_SEL_SHIFT 28 #define CTRL1_SEL_SHIFT 28
@ -76,12 +74,12 @@ static int axg_toddr_dai_hw_params(struct snd_pcm_substream *substream,
width = params_width(params); width = params_width(params);
regmap_update_bits(fifo->map, FIFO_CTRL0, regmap_update_bits(fifo->map, FIFO_CTRL0,
CTRL0_TODDR_TYPE_MASK | CTRL0_TODDR_TYPE |
CTRL0_TODDR_MSB_POS_MASK | CTRL0_TODDR_MSB_POS |
CTRL0_TODDR_LSB_POS_MASK, CTRL0_TODDR_LSB_POS,
CTRL0_TODDR_TYPE(type) | FIELD_PREP(CTRL0_TODDR_TYPE, type) |
CTRL0_TODDR_MSB_POS(TODDR_MSB_POS) | FIELD_PREP(CTRL0_TODDR_MSB_POS, TODDR_MSB_POS) |
CTRL0_TODDR_LSB_POS(TODDR_MSB_POS - (width - 1))); FIELD_PREP(CTRL0_TODDR_LSB_POS, TODDR_MSB_POS - (width - 1)));
return 0; return 0;
} }