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RDMA/bnxt_re: Update the BAR offsets
[ Upstream commita62d685814
] Update the BAR offsets for handling GenP7 adapters. Use the values populated by L2 driver for getting the Doorbell offsets. Signed-off-by: Selvin Xavier <selvin.xavier@broadcom.com> Link: https://lore.kernel.org/r/1701946060-13931-3-git-send-email-selvin.xavier@broadcom.com Signed-off-by: Leon Romanovsky <leon@kernel.org> Stable-dep-of:dc5006cfcf
("RDMA/bnxt_re: Fix the GID table length") Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -107,8 +107,11 @@ static void bnxt_re_set_db_offset(struct bnxt_re_dev *rdev)
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dev_info(rdev_to_dev(rdev),
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dev_info(rdev_to_dev(rdev),
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"Couldn't get DB bar size, Low latency framework is disabled\n");
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"Couldn't get DB bar size, Low latency framework is disabled\n");
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/* set register offsets for both UC and WC */
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/* set register offsets for both UC and WC */
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res->dpi_tbl.ucreg.offset = res->is_vf ? BNXT_QPLIB_DBR_VF_DB_OFFSET :
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if (bnxt_qplib_is_chip_gen_p7(cctx))
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BNXT_QPLIB_DBR_PF_DB_OFFSET;
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res->dpi_tbl.ucreg.offset = offset;
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else
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res->dpi_tbl.ucreg.offset = res->is_vf ? BNXT_QPLIB_DBR_VF_DB_OFFSET :
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BNXT_QPLIB_DBR_PF_DB_OFFSET;
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res->dpi_tbl.wcreg.offset = res->dpi_tbl.ucreg.offset;
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res->dpi_tbl.wcreg.offset = res->dpi_tbl.ucreg.offset;
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/* If WC mapping is disabled by L2 driver then en_dev->l2_db_size
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/* If WC mapping is disabled by L2 driver then en_dev->l2_db_size
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@ -1070,16 +1073,6 @@ static int bnxt_re_cqn_handler(struct bnxt_qplib_nq *nq,
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return 0;
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return 0;
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}
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}
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#define BNXT_RE_GEN_P5_PF_NQ_DB 0x10000
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#define BNXT_RE_GEN_P5_VF_NQ_DB 0x4000
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static u32 bnxt_re_get_nqdb_offset(struct bnxt_re_dev *rdev, u16 indx)
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{
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return bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx) ?
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(rdev->is_virtfn ? BNXT_RE_GEN_P5_VF_NQ_DB :
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BNXT_RE_GEN_P5_PF_NQ_DB) :
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rdev->en_dev->msix_entries[indx].db_offset;
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}
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static void bnxt_re_cleanup_res(struct bnxt_re_dev *rdev)
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static void bnxt_re_cleanup_res(struct bnxt_re_dev *rdev)
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{
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{
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int i;
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int i;
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@ -1100,7 +1093,7 @@ static int bnxt_re_init_res(struct bnxt_re_dev *rdev)
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bnxt_qplib_init_res(&rdev->qplib_res);
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bnxt_qplib_init_res(&rdev->qplib_res);
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for (i = 1; i < rdev->num_msix ; i++) {
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for (i = 1; i < rdev->num_msix ; i++) {
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db_offt = bnxt_re_get_nqdb_offset(rdev, i);
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db_offt = rdev->en_dev->msix_entries[i].db_offset;
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rc = bnxt_qplib_enable_nq(rdev->en_dev->pdev, &rdev->nq[i - 1],
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rc = bnxt_qplib_enable_nq(rdev->en_dev->pdev, &rdev->nq[i - 1],
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i - 1, rdev->en_dev->msix_entries[i].vector,
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i - 1, rdev->en_dev->msix_entries[i].vector,
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db_offt, &bnxt_re_cqn_handler,
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db_offt, &bnxt_re_cqn_handler,
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@ -1511,7 +1504,7 @@ static int bnxt_re_dev_init(struct bnxt_re_dev *rdev, u8 wqe_mode)
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ibdev_err(&rdev->ibdev, "Failed to allocate CREQ: %#x\n", rc);
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ibdev_err(&rdev->ibdev, "Failed to allocate CREQ: %#x\n", rc);
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goto free_rcfw;
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goto free_rcfw;
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}
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}
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db_offt = bnxt_re_get_nqdb_offset(rdev, BNXT_RE_AEQ_IDX);
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db_offt = rdev->en_dev->msix_entries[BNXT_RE_AEQ_IDX].db_offset;
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vid = rdev->en_dev->msix_entries[BNXT_RE_AEQ_IDX].vector;
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vid = rdev->en_dev->msix_entries[BNXT_RE_AEQ_IDX].vector;
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rc = bnxt_qplib_enable_rcfw_channel(&rdev->rcfw,
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rc = bnxt_qplib_enable_rcfw_channel(&rdev->rcfw,
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vid, db_offt,
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vid, db_offt,
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@ -153,8 +153,9 @@ int bnxt_qplib_get_dev_attr(struct bnxt_qplib_rcfw *rcfw,
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attr->max_srq_sges = sb->max_srq_sge;
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attr->max_srq_sges = sb->max_srq_sge;
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attr->max_pkey = 1;
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attr->max_pkey = 1;
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attr->max_inline_data = le32_to_cpu(sb->max_inline_data);
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attr->max_inline_data = le32_to_cpu(sb->max_inline_data);
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attr->l2_db_size = (sb->l2_db_space_size + 1) *
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if (!bnxt_qplib_is_chip_gen_p7(rcfw->res->cctx))
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(0x01 << RCFW_DBR_BASE_PAGE_SHIFT);
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attr->l2_db_size = (sb->l2_db_space_size + 1) *
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(0x01 << RCFW_DBR_BASE_PAGE_SHIFT);
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attr->max_sgid = BNXT_QPLIB_NUM_GIDS_SUPPORTED;
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attr->max_sgid = BNXT_QPLIB_NUM_GIDS_SUPPORTED;
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attr->dev_cap_flags = le16_to_cpu(sb->dev_cap_flags);
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attr->dev_cap_flags = le16_to_cpu(sb->dev_cap_flags);
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