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MGS-7531 [#mali] gpu: Integrate Mali DDK r47p0

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1. Disallows changing the sharability on the GPU of imported dma-bufs
to BASE_MEM_COHERENT_SYSTEM using KBASE_IOCTL_MEM_FLAGS_CHANGE.
2. Implement full block state support for hardware counters.
3. add imx platform instead of devicetree

Reviewed-by: Xianzhong Li <xianzhong.li@nxp.com>
Signed-off-by: Jiyu Yang <jiyu.yang@nxp.com>
This commit is contained in:
Jiyu Yang 2023-12-22 18:46:30 +08:00
parent b16e82b44a
commit cb5637f13a
219 changed files with 4289 additions and 8083 deletions
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2
drivers/gpu/arm/midgard/Kbuild
View File

@ -69,7 +69,7 @@ endif
#
# Driver version string which is returned to userspace via an ioctl
MALI_RELEASE_NAME ?= '"r46p0-01eac0"'
MALI_RELEASE_NAME ?= '"r47p0-01eac0"'
# Set up defaults if not defined by build system
ifeq ($(CONFIG_MALI_DEBUG), y)
MALI_UNIT_TEST = 1

12
drivers/gpu/arm/midgard/Kconfig
View File

@ -123,7 +123,7 @@ config MALI_MIDGARD_ENABLE_TRACE
config MALI_ARBITER_SUPPORT
bool "Enable arbiter support for Mali"
depends on MALI_MIDGARD && !MALI_CSF_SUPPORT
depends on MALI_MIDGARD
default n
help
Enable support for the arbiter interface in the driver.
@ -203,16 +203,6 @@ config PAGE_MIGRATION_SUPPORT
If in doubt, say Y. To strip out page migration symbols and support,
say N.
config MALI_MEMORY_FULLY_BACKED
bool "Enable memory fully physically-backed"
depends on MALI_MIDGARD && MALI_EXPERT
default n
help
This option enables full physical backing of all virtual
memory allocations in the kernel. Notice that this build
option only affects allocations of grow-on-GPU-page-fault
memory.
config MALI_CORESTACK
bool "Enable support of GPU core stack power control"
depends on MALI_MIDGARD && MALI_EXPERT

6
drivers/gpu/arm/midgard/Makefile
View File

@ -105,7 +105,6 @@ ifeq ($(MALI_KCONFIG_EXT_PREFIX),)
CONFIG_MALI_CORESTACK = n
CONFIG_LARGE_PAGE_SUPPORT = y
CONFIG_MALI_PWRSOFT_765 = n
CONFIG_MALI_MEMORY_FULLY_BACKED = n
CONFIG_MALI_JOB_DUMP = n
CONFIG_MALI_NO_MALI = n
CONFIG_MALI_REAL_HW = y
@ -170,7 +169,6 @@ ifeq ($(MALI_KCONFIG_EXT_PREFIX),)
CONFIG_MALI_CORESTACK \
CONFIG_LARGE_PAGE_SUPPORT \
CONFIG_MALI_PWRSOFT_765 \
CONFIG_MALI_MEMORY_FULLY_BACKED \
CONFIG_MALI_JOB_DUMP \
CONFIG_MALI_NO_MALI \
CONFIG_MALI_ERROR_INJECT \
@ -193,6 +191,7 @@ ifeq ($(MALI_KCONFIG_EXT_PREFIX),)
CONFIG_MALI_TRACE_POWER_GPU_WORK_PERIOD
endif
THIS_DIR := $(dir $(lastword $(MAKEFILE_LIST)))
@ -231,7 +230,8 @@ endif
#
# KBUILD_EXTRA_SYMBOLS to prevent warnings about unknown functions
#
BASE_SYMBOLS = $(M)/../../base/arm/Module.symvers
BASE_SYMBOLS =
EXTRA_SYMBOLS += \
$(BASE_SYMBOLS)

4
drivers/gpu/arm/midgard/arbiter/mali_kbase_arbif.c
View File

@ -183,7 +183,9 @@ int kbase_arbif_init(struct kbase_device *kbdev)
dev_dbg(kbdev->dev, "%s\n", __func__);
arbiter_if_node = of_parse_phandle(kbdev->dev->of_node, "arbiter_if", 0);
arbiter_if_node = of_parse_phandle(kbdev->dev->of_node, "arbiter-if", 0);
if (!arbiter_if_node)
arbiter_if_node = of_parse_phandle(kbdev->dev->of_node, "arbiter_if", 0);
if (!arbiter_if_node) {
dev_dbg(kbdev->dev, "No arbiter_if in Device Tree\n");
/* no arbiter interface defined in device tree */

2
drivers/gpu/arm/midgard/arbiter/mali_kbase_arbiter_pm.c
View File

@ -308,7 +308,7 @@ int kbase_arbiter_pm_early_init(struct kbase_device *kbdev)
err = wait_event_timeout(arb_vm_state->vm_state_wait,
arb_vm_state->vm_state ==
KBASE_VM_STATE_INITIALIZING_WITH_GPU,
msecs_to_jiffies(gpu_req_timeout));
msecs_to_jiffies((unsigned int)gpu_req_timeout));
if (!err) {
dev_dbg(kbdev->dev,

29
drivers/gpu/arm/midgard/backend/gpu/mali_kbase_backend_config.h
View File

@ -1,29 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
*
* (C) COPYRIGHT 2014-2023 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
* Foundation, and any use by you of this program is subject to the terms
* of such GNU license.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you can access it online at
* http://www.gnu.org/licenses/gpl-2.0.html.
*
*/
/*
* Backend specific configuration
*/
#ifndef _KBASE_BACKEND_CONFIG_H_
#define _KBASE_BACKEND_CONFIG_H_
#endif /* _KBASE_BACKEND_CONFIG_H_ */

5
drivers/gpu/arm/midgard/backend/gpu/mali_kbase_cache_policy_backend.h
View File

@ -22,8 +22,9 @@
#ifndef _KBASE_CACHE_POLICY_BACKEND_H_
#define _KBASE_CACHE_POLICY_BACKEND_H_
#include "mali_kbase.h"
#include <uapi/gpu/arm/midgard/mali_base_kernel.h>
#include <linux/types.h>
struct kbase_device;
/**
* kbase_cache_set_coherency_mode() - Sets the system coherency mode

46
drivers/gpu/arm/midgard/backend/gpu/mali_kbase_debug_job_fault_backend.c
View File

@ -27,34 +27,38 @@
#if IS_ENABLED(CONFIG_DEBUG_FS)
/*GPU_CONTROL_REG(r)*/
static int gpu_control_reg_snapshot[] = { GPU_CONTROL_ENUM(GPU_ID), GPU_CONTROL_ENUM(SHADER_READY),
GPU_CONTROL_ENUM(TILER_READY),
GPU_CONTROL_ENUM(L2_READY) };
static unsigned int gpu_control_reg_snapshot[] = { GPU_CONTROL_ENUM(GPU_ID),
GPU_CONTROL_ENUM(SHADER_READY),
GPU_CONTROL_ENUM(TILER_READY),
GPU_CONTROL_ENUM(L2_READY) };
/* JOB_CONTROL_REG(r) */
static int job_control_reg_snapshot[] = { JOB_CONTROL_ENUM(JOB_IRQ_MASK),
JOB_CONTROL_ENUM(JOB_IRQ_STATUS) };
static unsigned int job_control_reg_snapshot[] = { JOB_CONTROL_ENUM(JOB_IRQ_MASK),
JOB_CONTROL_ENUM(JOB_IRQ_STATUS) };
/* JOB_SLOT_REG(n,r) */
static int job_slot_reg_snapshot[] = { JOB_SLOT_ENUM(0, HEAD) - JOB_SLOT_BASE_ENUM(0),
JOB_SLOT_ENUM(0, TAIL) - JOB_SLOT_BASE_ENUM(0),
JOB_SLOT_ENUM(0, AFFINITY) - JOB_SLOT_BASE_ENUM(0),
JOB_SLOT_ENUM(0, CONFIG) - JOB_SLOT_BASE_ENUM(0),
JOB_SLOT_ENUM(0, STATUS) - JOB_SLOT_BASE_ENUM(0),
JOB_SLOT_ENUM(0, HEAD_NEXT) - JOB_SLOT_BASE_ENUM(0),
JOB_SLOT_ENUM(0, AFFINITY_NEXT) - JOB_SLOT_BASE_ENUM(0),
JOB_SLOT_ENUM(0, CONFIG_NEXT) - JOB_SLOT_BASE_ENUM(0) };
static unsigned int job_slot_reg_snapshot[] = {
JOB_SLOT_ENUM(0, HEAD) - JOB_SLOT_BASE_ENUM(0),
JOB_SLOT_ENUM(0, TAIL) - JOB_SLOT_BASE_ENUM(0),
JOB_SLOT_ENUM(0, AFFINITY) - JOB_SLOT_BASE_ENUM(0),
JOB_SLOT_ENUM(0, CONFIG) - JOB_SLOT_BASE_ENUM(0),
JOB_SLOT_ENUM(0, STATUS) - JOB_SLOT_BASE_ENUM(0),
JOB_SLOT_ENUM(0, HEAD_NEXT) - JOB_SLOT_BASE_ENUM(0),
JOB_SLOT_ENUM(0, AFFINITY_NEXT) - JOB_SLOT_BASE_ENUM(0),
JOB_SLOT_ENUM(0, CONFIG_NEXT) - JOB_SLOT_BASE_ENUM(0)
};
/*MMU_CONTROL_REG(r)*/
static int mmu_reg_snapshot[] = { MMU_CONTROL_ENUM(IRQ_MASK), MMU_CONTROL_ENUM(IRQ_STATUS) };
static unsigned int mmu_reg_snapshot[] = { MMU_CONTROL_ENUM(IRQ_MASK),
MMU_CONTROL_ENUM(IRQ_STATUS) };
/* MMU_AS_REG(n,r) */
static int as_reg_snapshot[] = { MMU_AS_ENUM(0, TRANSTAB) - MMU_AS_BASE_ENUM(0),
MMU_AS_ENUM(0, TRANSCFG) - MMU_AS_BASE_ENUM(0),
MMU_AS_ENUM(0, MEMATTR) - MMU_AS_BASE_ENUM(0),
MMU_AS_ENUM(0, FAULTSTATUS) - MMU_AS_BASE_ENUM(0),
MMU_AS_ENUM(0, FAULTADDRESS) - MMU_AS_BASE_ENUM(0),
MMU_AS_ENUM(0, STATUS) - MMU_AS_BASE_ENUM(0) };
static unsigned int as_reg_snapshot[] = { MMU_AS_ENUM(0, TRANSTAB) - MMU_AS_BASE_ENUM(0),
MMU_AS_ENUM(0, TRANSCFG) - MMU_AS_BASE_ENUM(0),
MMU_AS_ENUM(0, MEMATTR) - MMU_AS_BASE_ENUM(0),
MMU_AS_ENUM(0, FAULTSTATUS) - MMU_AS_BASE_ENUM(0),
MMU_AS_ENUM(0, FAULTADDRESS) - MMU_AS_BASE_ENUM(0),
MMU_AS_ENUM(0, STATUS) - MMU_AS_BASE_ENUM(0) };
bool kbase_debug_job_fault_reg_snapshot_init(struct kbase_context *kctx, int reg_range)
{
@ -132,7 +136,7 @@ bool kbase_debug_job_fault_reg_snapshot_init(struct kbase_context *kctx, int reg
bool kbase_job_fault_get_reg_snapshot(struct kbase_context *kctx)
{
int offset = 0;
int reg_enum;
u32 reg_enum;
u64 val64;
if (kctx->reg_dump == NULL)

4
drivers/gpu/arm/midgard/backend/gpu/mali_kbase_jm_defs.h → drivers/gpu/arm/midgard/backend/gpu/mali_kbase_defs.h
View File

@ -50,7 +50,7 @@ struct rb_entry {
* u64 for serving as tagged value.
* @kctx: Pointer to kbase context.
*/
#define SLOT_RB_TAG_KCTX(kctx) (u64)((uintptr_t)(kctx))
#define SLOT_RB_TAG_KCTX(kctx) ((u64)(uintptr_t)(kctx))
/**
* struct slot_rb - Slot ringbuffer
* @entries: Ringbuffer entries
@ -116,7 +116,7 @@ struct kbase_backend_data {
* within the timeout period
*/
#define KBASE_RESET_GPU_COMMITTED 2
/* The GPU reset process is currently occuring (timeout has expired or
/* The GPU reset process is currently occurring (timeout has expired or
* kbasep_try_reset_gpu_early was called)
*/
#define KBASE_RESET_GPU_HAPPENING 3

13
drivers/gpu/arm/midgard/backend/gpu/mali_kbase_devfreq.c
View File

@ -264,7 +264,7 @@ static int kbase_devfreq_status(struct device *dev, struct devfreq_dev_status *s
static int kbase_devfreq_init_freq_table(struct kbase_device *kbdev, struct devfreq_dev_profile *dp)
{
int count;
int i = 0;
unsigned int i = 0;
unsigned long freq;
struct dev_pm_opp *opp;
@ -278,14 +278,14 @@ static int kbase_devfreq_init_freq_table(struct kbase_device *kbdev, struct devf
if (count < 0)
return count;
dp->freq_table = kmalloc_array(count, sizeof(dp->freq_table[0]), GFP_KERNEL);
dp->freq_table = kmalloc_array((size_t)count, sizeof(dp->freq_table[0]), GFP_KERNEL);
if (!dp->freq_table)
return -ENOMEM;
#if KERNEL_VERSION(4, 11, 0) > LINUX_VERSION_CODE
rcu_read_lock();
#endif
for (i = 0, freq = ULONG_MAX; i < count; i++, freq--) {
for (i = 0, freq = ULONG_MAX; i < (unsigned int)count; i++, freq--) {
opp = dev_pm_opp_find_freq_floor(kbdev->dev, &freq);
if (IS_ERR(opp))
break;
@ -299,8 +299,8 @@ static int kbase_devfreq_init_freq_table(struct kbase_device *kbdev, struct devf
rcu_read_unlock();
#endif
if (count != i)
dev_warn(kbdev->dev, "Unable to enumerate all OPPs (%d!=%d\n", count, i);
if ((unsigned int)count != i)
dev_warn(kbdev->dev, "Unable to enumerate all OPPs (%d!=%u\n", count, i);
dp->max_state = i;
@ -401,7 +401,8 @@ static int kbase_devfreq_init_core_mask_table(struct kbase_device *kbdev)
return 0;
count = dev_pm_opp_get_opp_count(kbdev->dev);
kbdev->devfreq_table = kmalloc_array(count, sizeof(struct kbase_devfreq_opp), GFP_KERNEL);
kbdev->devfreq_table =
kmalloc_array((size_t)count, sizeof(struct kbase_devfreq_opp), GFP_KERNEL);
if (!kbdev->devfreq_table)
return -ENOMEM;

4
drivers/gpu/arm/midgard/backend/gpu/mali_kbase_gpuprops_backend.c
View File

@ -30,7 +30,7 @@
int kbase_backend_gpuprops_get(struct kbase_device *kbdev, struct kbasep_gpuprops_regdump *regdump)
{
int i;
uint i;
/* regdump is zero intiialized, individual entries do not need to be explicitly set */
regdump->gpu_id = KBASE_REG_READ(kbdev, GPU_CONTROL_ENUM(GPU_ID));
@ -122,7 +122,7 @@ int kbase_backend_gpuprops_get_l2_features(struct kbase_device *kbdev,
#if MALI_USE_CSF
if (kbase_hw_has_l2_slice_hash_feature(kbdev)) {
int i;
uint i;
for (i = 0; i < GPU_L2_SLICE_HASH_COUNT; i++)
regdump->l2_slice_hash[i] =
kbase_reg_read32(kbdev, GPU_L2_SLICE_HASH_OFFSET(i));

27
drivers/gpu/arm/midgard/backend/gpu/mali_kbase_instr_backend.c
View File

@ -31,17 +31,17 @@
static int wait_prfcnt_ready(struct kbase_device *kbdev)
{
u32 loops;
for (loops = 0; loops < KBASE_PRFCNT_ACTIVE_MAX_LOOPS; loops++) {
const u32 prfcnt_active = kbase_reg_read32(kbdev, GPU_CONTROL_ENUM(GPU_STATUS)) &
GPU_STATUS_PRFCNT_ACTIVE;
if (!prfcnt_active)
return 0;
u32 val;
const u32 timeout_us =
kbase_get_timeout_ms(kbdev, KBASE_PRFCNT_ACTIVE_TIMEOUT) * USEC_PER_MSEC;
const int err = kbase_reg_poll32_timeout(kbdev, GPU_CONTROL_ENUM(GPU_STATUS), val,
!(val & GPU_STATUS_PRFCNT_ACTIVE), 0, timeout_us,
false);
if (err) {
dev_err(kbdev->dev, "PRFCNT_ACTIVE bit stuck\n");
return -EBUSY;
}
dev_err(kbdev->dev, "PRFCNT_ACTIVE bit stuck\n");
return -EBUSY;
return 0;
}
int kbase_instr_hwcnt_enable_internal(struct kbase_device *kbdev, struct kbase_context *kctx,
@ -86,11 +86,12 @@ int kbase_instr_hwcnt_enable_internal(struct kbase_device *kbdev, struct kbase_c
spin_unlock_irqrestore(&kbdev->hwcnt.lock, flags);
/* Configure */
prfcnt_config = kctx->as_nr << PRFCNT_CONFIG_AS_SHIFT;
prfcnt_config = (u32)kctx->as_nr << PRFCNT_CONFIG_AS_SHIFT;
#ifdef CONFIG_MALI_PRFCNT_SET_SELECT_VIA_DEBUG_FS
prfcnt_config |= kbdev->hwcnt.backend.override_counter_set << PRFCNT_CONFIG_SETSELECT_SHIFT;
prfcnt_config |= (u32)kbdev->hwcnt.backend.override_counter_set
<< PRFCNT_CONFIG_SETSELECT_SHIFT;
#else
prfcnt_config |= enable->counter_set << PRFCNT_CONFIG_SETSELECT_SHIFT;
prfcnt_config |= (u32)enable->counter_set << PRFCNT_CONFIG_SETSELECT_SHIFT;
#endif
/* Wait until prfcnt config register can be written */

69
drivers/gpu/arm/midgard/backend/gpu/mali_kbase_irq_internal.h
View File

@ -26,8 +26,29 @@
#ifndef _KBASE_IRQ_INTERNAL_H_
#define _KBASE_IRQ_INTERNAL_H_
/* GPU IRQ Tags */
#define JOB_IRQ_TAG 0
#define MMU_IRQ_TAG 1
#define GPU_IRQ_TAG 2
/**
* kbase_install_interrupts - Install IRQs handlers.
*
* @kbdev: The kbase device
*
* This function must be called once only when a kbase device is initialized.
*
* Return: 0 on success. Error code (negative) on failure.
*/
int kbase_install_interrupts(struct kbase_device *kbdev);
/**
* kbase_release_interrupts - Uninstall IRQs handlers.
*
* @kbdev: The kbase device
*
* This function needs to be called when a kbase device is terminated.
*/
void kbase_release_interrupts(struct kbase_device *kbdev);
/**
@ -37,10 +58,52 @@ void kbase_release_interrupts(struct kbase_device *kbdev);
*/
void kbase_synchronize_irqs(struct kbase_device *kbdev);
int kbasep_common_test_interrupt_handlers(struct kbase_device *const kbdev);
#ifdef CONFIG_MALI_DEBUG
#if IS_ENABLED(CONFIG_MALI_REAL_HW)
/**
* kbase_validate_interrupts - Validate interrupts
*
* @kbdev: The kbase device
*
* This function will be called once when a kbase device is initialized
* to check whether interrupt handlers are configured appropriately.
* If interrupt numbers and/or flags defined in the device tree are
* incorrect, then the validation might fail.
* The whold device initialization will fail if it returns error code.
*
* Return: 0 on success. Error code (negative) on failure.
*/
int kbase_validate_interrupts(struct kbase_device *const kbdev);
#endif /* CONFIG_MALI_REAL_HW */
#endif /* CONFIG_MALI_DEBUG */
irqreturn_t kbase_gpu_irq_test_handler(int irq, void *data, u32 val);
/**
* kbase_get_interrupt_handler - Return default interrupt handler
* @kbdev: Kbase device
* @irq_tag: Tag to choose the handler
*
* If single interrupt line is used the combined interrupt handler
* will be returned regardless of irq_tag. Otherwise the corresponding
* interrupt handler will be returned.
*
* Return: Interrupt handler corresponding to the tag. NULL on failure.
*/
irq_handler_t kbase_get_interrupt_handler(struct kbase_device *kbdev, u32 irq_tag);
/**
* kbase_set_custom_irq_handler - Set a custom IRQ handler
*
* @kbdev: The kbase device for which the handler is to be registered
* @custom_handler: Handler to be registered
* @irq_tag: Interrupt tag
*
* Register given interrupt handler for requested interrupt tag
* In the case where irq handler is not specified, the default handler shall be
* registered
*
* Return: 0 case success, error code otherwise
*/
int kbase_set_custom_irq_handler(struct kbase_device *kbdev, irq_handler_t custom_handler,
int irq_type);
u32 irq_tag);
#endif /* _KBASE_IRQ_INTERNAL_H_ */

243
drivers/gpu/arm/midgard/backend/gpu/mali_kbase_irq_linux.c
View File

@ -26,20 +26,15 @@
#include <linux/interrupt.h>
#if IS_ENABLED(CONFIG_MALI_REAL_HW)
/* GPU IRQ Tags */
#define JOB_IRQ_TAG 0
#define MMU_IRQ_TAG 1
#define GPU_IRQ_TAG 2
static void *kbase_tag(void *ptr, u32 tag)
{
return (void *)(((uintptr_t)ptr) | tag);
}
#endif
static void *kbase_untag(void *ptr)
{
return (void *)(((uintptr_t)ptr) & ~3);
return (void *)(((uintptr_t)ptr) & ~(uintptr_t)3);
}
static irqreturn_t kbase_job_irq_handler(int irq, void *data)
@ -58,12 +53,6 @@ static irqreturn_t kbase_job_irq_handler(int irq, void *data)
val = kbase_reg_read32(kbdev, JOB_CONTROL_ENUM(JOB_IRQ_STATUS));
#ifdef CONFIG_MALI_DEBUG
if (!kbdev->pm.backend.driver_ready_for_irqs)
dev_warn(kbdev->dev, "%s: irq %d irqstatus 0x%x before driver is ready\n", __func__,
irq, val);
#endif /* CONFIG_MALI_DEBUG */
if (!val) {
spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags);
return IRQ_NONE;
@ -101,11 +90,6 @@ static irqreturn_t kbase_mmu_irq_handler(int irq, void *data)
val = kbase_reg_read32(kbdev, MMU_CONTROL_ENUM(IRQ_STATUS));
#ifdef CONFIG_MALI_DEBUG
if (!kbdev->pm.backend.driver_ready_for_irqs)
dev_warn(kbdev->dev, "%s: irq %d irqstatus 0x%x before driver is ready\n", __func__,
irq, val);
#endif /* CONFIG_MALI_DEBUG */
spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags);
if (!val) {
@ -122,7 +106,8 @@ static irqreturn_t kbase_mmu_irq_handler(int irq, void *data)
return IRQ_HANDLED;
}
static irqreturn_t kbase_gpu_irq_handler(int irq, void *data)
static irqreturn_t kbase_gpuonly_irq_handler(int irq, void *data)
{
unsigned long flags;
struct kbase_device *kbdev = kbase_untag(data);
@ -139,13 +124,6 @@ static irqreturn_t kbase_gpu_irq_handler(int irq, void *data)
gpu_irq_status = kbase_reg_read32(kbdev, GPU_CONTROL_ENUM(GPU_IRQ_STATUS));
#ifdef CONFIG_MALI_DEBUG
if (!kbdev->pm.backend.driver_ready_for_irqs) {
dev_dbg(kbdev->dev, "%s: irq %d irqstatus 0x%x before driver is ready\n", __func__,
irq, gpu_irq_status);
}
#endif /* CONFIG_MALI_DEBUG */
spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags);
if (gpu_irq_status) {
@ -158,82 +136,91 @@ static irqreturn_t kbase_gpu_irq_handler(int irq, void *data)
return irq_state;
}
/**
* kbase_gpu_irq_handler - GPU interrupt handler
* @irq: IRQ number
* @data: Data associated with this IRQ (i.e. kbdev)
*
* Return: IRQ_HANDLED if any interrupt request has been successfully handled.
* IRQ_NONE otherwise.
*/
static irqreturn_t kbase_gpu_irq_handler(int irq, void *data)
{
irqreturn_t irq_state = kbase_gpuonly_irq_handler(irq, data);
return irq_state;
}
/**
* kbase_combined_irq_handler - Combined interrupt handler for all interrupts
* @irq: IRQ number
* @data: Data associated with this IRQ (i.e. kbdev)
*
* This handler will be used for the GPU with single interrupt line.
*
* Return: IRQ_HANDLED if any interrupt request has been successfully handled.
* IRQ_NONE otherwise.
*/
static irqreturn_t kbase_combined_irq_handler(int irq, void *data)
{
irqreturn_t irq_state = IRQ_NONE;
if (kbase_job_irq_handler(irq, data) == IRQ_HANDLED)
irq_state = IRQ_HANDLED;
if (kbase_mmu_irq_handler(irq, data) == IRQ_HANDLED)
irq_state = IRQ_HANDLED;
if (kbase_gpu_irq_handler(irq, data) == IRQ_HANDLED)
irq_state = IRQ_HANDLED;
return irq_state;
}
static irq_handler_t kbase_handler_table[] = {
[JOB_IRQ_TAG] = kbase_job_irq_handler,
[MMU_IRQ_TAG] = kbase_mmu_irq_handler,
[GPU_IRQ_TAG] = kbase_gpu_irq_handler,
};
#ifdef CONFIG_MALI_DEBUG
#define JOB_IRQ_HANDLER JOB_IRQ_TAG
#define GPU_IRQ_HANDLER GPU_IRQ_TAG
/**
* kbase_gpu_irq_test_handler - Variant (for test) of kbase_gpu_irq_handler()
* @irq: IRQ number
* @data: Data associated with this IRQ (i.e. kbdev)
* @val: Value of the GPU_CONTROL_ENUM(GPU_IRQ_STATUS)
*
* Handle the GPU device interrupt source requests reflected in the
* given source bit-pattern. The test code caller is responsible for
* undertaking the required device power maintenace.
*
* Return: IRQ_HANDLED if the requests are from the GPU device,
* IRQ_NONE otherwise
*/
irqreturn_t kbase_gpu_irq_test_handler(int irq, void *data, u32 val)
irq_handler_t kbase_get_interrupt_handler(struct kbase_device *kbdev, u32 irq_tag)
{
struct kbase_device *kbdev = kbase_untag(data);
if (!val)
return IRQ_NONE;
dev_dbg(kbdev->dev, "%s: irq %d irqstatus 0x%x\n", __func__, irq, val);
kbase_gpu_interrupt(kbdev, val);
return IRQ_HANDLED;
if (kbdev->nr_irqs == 1)
return kbase_combined_irq_handler;
else if (irq_tag < ARRAY_SIZE(kbase_handler_table))
return kbase_handler_table[irq_tag];
else
return NULL;
}
KBASE_EXPORT_TEST_API(kbase_gpu_irq_test_handler);
/**
* kbase_set_custom_irq_handler - Set a custom IRQ handler
* @kbdev: Device for which the handler is to be registered
* @custom_handler: Handler to be registered
* @irq_type: Interrupt type
*
* Registers given interrupt handler for requested interrupt type
* In the case where irq handler is not specified, the default handler shall be
* registered
*
* Return: 0 case success, error code otherwise
*/
#if IS_ENABLED(CONFIG_MALI_REAL_HW)
#ifdef CONFIG_MALI_DEBUG
int kbase_set_custom_irq_handler(struct kbase_device *kbdev, irq_handler_t custom_handler,
int irq_type)
u32 irq_tag)
{
int result = 0;
irq_handler_t requested_irq_handler = NULL;
irq_handler_t handler = custom_handler;
const int irq = (kbdev->nr_irqs == 1) ? 0 : irq_tag;
KBASE_DEBUG_ASSERT((irq_type >= JOB_IRQ_HANDLER) && (irq_type <= GPU_IRQ_HANDLER));
if (unlikely(!((irq_tag >= JOB_IRQ_TAG) && (irq_tag <= GPU_IRQ_TAG)))) {
dev_err(kbdev->dev, "Invalid irq_tag (%d)\n", irq_tag);
return -EINVAL;
}
/* Release previous handler */
if (kbdev->irqs[irq_type].irq)
free_irq(kbdev->irqs[irq_type].irq, kbase_tag(kbdev, irq_type));
if (kbdev->irqs[irq].irq)
free_irq(kbdev->irqs[irq].irq, kbase_tag(kbdev, irq));
requested_irq_handler = (custom_handler != NULL) ? custom_handler :
kbase_handler_table[irq_type];
/* If a custom handler isn't provided use the default handler */
if (!handler)
handler = kbase_get_interrupt_handler(kbdev, irq_tag);
if (request_irq(kbdev->irqs[irq_type].irq, requested_irq_handler,
kbdev->irqs[irq_type].flags | IRQF_SHARED, dev_name(kbdev->dev),
kbase_tag(kbdev, irq_type)) != 0) {
if (request_irq(kbdev->irqs[irq].irq, handler,
kbdev->irqs[irq].flags | ((kbdev->nr_irqs == 1) ? 0 : IRQF_SHARED),
dev_name(kbdev->dev), kbase_tag(kbdev, irq)) != 0) {
result = -EINVAL;
dev_err(kbdev->dev, "Can't request interrupt %d (index %d)\n",
kbdev->irqs[irq_type].irq, irq_type);
#if IS_ENABLED(CONFIG_SPARSE_IRQ)
dev_err(kbdev->dev,
"You have CONFIG_SPARSE_IRQ support enabled - is the interrupt number correct for this configuration?\n");
#endif /* CONFIG_SPARSE_IRQ */
dev_err(kbdev->dev, "Can't request interrupt %u (index %u)\n", kbdev->irqs[irq].irq,
irq_tag);
if (IS_ENABLED(CONFIG_SPARSE_IRQ))
dev_err(kbdev->dev,
"CONFIG_SPARSE_IRQ enabled - is the interrupt number correct for this config?\n");
}
return result;
@ -325,30 +312,43 @@ static enum hrtimer_restart kbasep_test_interrupt_timeout(struct hrtimer *timer)
return HRTIMER_NORESTART;
}
static int kbasep_common_test_interrupt(struct kbase_device *const kbdev, u32 tag)
/**
* validate_interrupt - Validate an interrupt
* @kbdev: Kbase device
* @tag: Tag to choose the interrupt
*
* To validate the settings for the interrupt, write a value on RAWSTAT
* register to trigger interrupt. Then with custom interrupt handler
* check whether the interrupt happens within reasonable time.
*
* Return: 0 if validating interrupt succeeds.
*/
static int validate_interrupt(struct kbase_device *const kbdev, u32 tag)
{
int err = 0;
irq_handler_t test_handler;
irq_handler_t handler;
const int irq = (kbdev->nr_irqs == 1) ? 0 : tag;
u32 old_mask_val;
u16 mask_offset;
u16 rawstat_offset;
switch (tag) {
case JOB_IRQ_TAG:
test_handler = kbase_job_irq_test_handler;
handler = kbase_job_irq_test_handler;
rawstat_offset = JOB_CONTROL_ENUM(JOB_IRQ_RAWSTAT);
mask_offset = JOB_CONTROL_ENUM(JOB_IRQ_MASK);
break;
case MMU_IRQ_TAG:
test_handler = kbase_mmu_irq_test_handler;
handler = kbase_mmu_irq_test_handler;
rawstat_offset = MMU_CONTROL_ENUM(IRQ_RAWSTAT);
mask_offset = MMU_CONTROL_ENUM(IRQ_MASK);
break;
case GPU_IRQ_TAG:
/* already tested by pm_driver - bail out */
default:
return 0;
default:
dev_err(kbdev->dev, "Invalid tag (%d)\n", tag);
return -EINVAL;
}
/* store old mask */
@ -356,9 +356,9 @@ static int kbasep_common_test_interrupt(struct kbase_device *const kbdev, u32 ta
/* mask interrupts */
kbase_reg_write32(kbdev, mask_offset, 0x0);
if (kbdev->irqs[tag].irq) {
if (kbdev->irqs[irq].irq) {
/* release original handler and install test handler */
if (kbase_set_custom_irq_handler(kbdev, test_handler, tag) != 0) {
if (kbase_set_custom_irq_handler(kbdev, handler, tag) != 0) {
err = -EINVAL;
} else {
kbasep_irq_test_data.timeout = 0;
@ -376,12 +376,12 @@ static int kbasep_common_test_interrupt(struct kbase_device *const kbdev, u32 ta
wait_event(kbasep_irq_test_data.wait, kbasep_irq_test_data.triggered != 0);
if (kbasep_irq_test_data.timeout != 0) {
dev_err(kbdev->dev, "Interrupt %d (index %d) didn't reach CPU.\n",
kbdev->irqs[tag].irq, tag);
dev_err(kbdev->dev, "Interrupt %u (index %u) didn't reach CPU.\n",
kbdev->irqs[irq].irq, irq);
err = -EINVAL;
} else {
dev_dbg(kbdev->dev, "Interrupt %d (index %d) reached CPU.\n",
kbdev->irqs[tag].irq, tag);
dev_dbg(kbdev->dev, "Interrupt %u (index %u) reached CPU.\n",
kbdev->irqs[irq].irq, irq);
}
hrtimer_cancel(&kbasep_irq_test_data.timer);
@ -391,15 +391,15 @@ static int kbasep_common_test_interrupt(struct kbase_device *const kbdev, u32 ta
kbase_reg_write32(kbdev, mask_offset, 0x0);
/* release test handler */
free_irq(kbdev->irqs[tag].irq, kbase_tag(kbdev, tag));
free_irq(kbdev->irqs[irq].irq, kbase_tag(kbdev, irq));
}
/* restore original interrupt */
if (request_irq(kbdev->irqs[tag].irq, kbase_handler_table[tag],
kbdev->irqs[tag].flags | IRQF_SHARED, dev_name(kbdev->dev),
kbase_tag(kbdev, tag))) {
dev_err(kbdev->dev, "Can't restore original interrupt %d (index %d)\n",
kbdev->irqs[tag].irq, tag);
if (request_irq(kbdev->irqs[irq].irq, kbase_get_interrupt_handler(kbdev, tag),
kbdev->irqs[irq].flags | ((kbdev->nr_irqs == 1) ? 0 : IRQF_SHARED),
dev_name(kbdev->dev), kbase_tag(kbdev, irq))) {
dev_err(kbdev->dev, "Can't restore original interrupt %u (index %u)\n",
kbdev->irqs[irq].irq, tag);
err = -EINVAL;
}
}
@ -409,7 +409,8 @@ static int kbasep_common_test_interrupt(struct kbase_device *const kbdev, u32 ta
return err;
}
int kbasep_common_test_interrupt_handlers(struct kbase_device *const kbdev)
#if IS_ENABLED(CONFIG_MALI_REAL_HW)
int kbase_validate_interrupts(struct kbase_device *const kbdev)
{
int err;
@ -419,14 +420,14 @@ int kbasep_common_test_interrupt_handlers(struct kbase_device *const kbdev)
/* A suspend won't happen during startup/insmod */
kbase_pm_context_active(kbdev);
err = kbasep_common_test_interrupt(kbdev, JOB_IRQ_TAG);
err = validate_interrupt(kbdev, JOB_IRQ_TAG);
if (err) {
dev_err(kbdev->dev,
"Interrupt JOB_IRQ didn't reach CPU. Check interrupt assignments.\n");
goto out;
}
err = kbasep_common_test_interrupt(kbdev, MMU_IRQ_TAG);
err = validate_interrupt(kbdev, MMU_IRQ_TAG);
if (err) {
dev_err(kbdev->dev,
"Interrupt MMU_IRQ didn't reach CPU. Check interrupt assignments.\n");
@ -440,25 +441,21 @@ out:
return err;
}
#endif /* CONFIG_MALI_REAL_HW */
#endif /* CONFIG_MALI_DEBUG */
int kbase_install_interrupts(struct kbase_device *kbdev)
{
u32 nr = ARRAY_SIZE(kbase_handler_table);
int err;
u32 i;
for (i = 0; i < nr; i++) {
err = request_irq(kbdev->irqs[i].irq, kbase_handler_table[i],
kbdev->irqs[i].flags | IRQF_SHARED, dev_name(kbdev->dev),
kbase_tag(kbdev, i));
if (err) {
dev_err(kbdev->dev, "Can't request interrupt %d (index %d)\n",
for (i = 0; i < kbdev->nr_irqs; i++) {
const int result = request_irq(
kbdev->irqs[i].irq, kbase_get_interrupt_handler(kbdev, i),
kbdev->irqs[i].flags | ((kbdev->nr_irqs == 1) ? 0 : IRQF_SHARED),
dev_name(kbdev->dev), kbase_tag(kbdev, i));
if (result) {
dev_err(kbdev->dev, "Can't request interrupt %u (index %u)\n",
kbdev->irqs[i].irq, i);
#if IS_ENABLED(CONFIG_SPARSE_IRQ)
dev_err(kbdev->dev,
"You have CONFIG_SPARSE_IRQ support enabled - is the interrupt number correct for this configuration?\n");
#endif /* CONFIG_SPARSE_IRQ */
goto release;
}
}
@ -466,18 +463,21 @@ int kbase_install_interrupts(struct kbase_device *kbdev)
return 0;
release:
if (IS_ENABLED(CONFIG_SPARSE_IRQ))
dev_err(kbdev->dev,
"CONFIG_SPARSE_IRQ enabled - is the interrupt number correct for this config?\n");
while (i-- > 0)
free_irq(kbdev->irqs[i].irq, kbase_tag(kbdev, i));
return err;
return -EINVAL;
}
void kbase_release_interrupts(struct kbase_device *kbdev)
{
u32 nr = ARRAY_SIZE(kbase_handler_table);
u32 i;
for (i = 0; i < nr; i++) {
for (i = 0; i < kbdev->nr_irqs; i++) {
if (kbdev->irqs[i].irq)
free_irq(kbdev->irqs[i].irq, kbase_tag(kbdev, i));
}
@ -485,10 +485,9 @@ void kbase_release_interrupts(struct kbase_device *kbdev)
void kbase_synchronize_irqs(struct kbase_device *kbdev)
{
u32 nr = ARRAY_SIZE(kbase_handler_table);
u32 i;
for (i = 0; i < nr; i++) {
for (i = 0; i < kbdev->nr_irqs; i++) {
if (kbdev->irqs[i].irq)
synchronize_irq(kbdev->irqs[i].irq);
}

62
drivers/gpu/arm/midgard/backend/gpu/mali_kbase_jm_hw.c
View File

@ -177,17 +177,14 @@ static u64 select_job_chain(struct kbase_jd_atom *katom)
static inline bool kbasep_jm_wait_js_free(struct kbase_device *kbdev, unsigned int js,
struct kbase_context *kctx)
{
const ktime_t wait_loop_start = ktime_get_raw();
const s64 max_timeout = (s64)kbdev->js_data.js_free_wait_time_ms;
s64 diff = 0;
u32 val;
const u32 timeout_us = kbdev->js_data.js_free_wait_time_ms * USEC_PER_MSEC;
/* wait for the JS_COMMAND_NEXT register to reach the given status value */
do {
if (!kbase_reg_read32(kbdev, JOB_SLOT_OFFSET(js, COMMAND_NEXT)))
return true;
const int err = kbase_reg_poll32_timeout(kbdev, JOB_SLOT_OFFSET(js, COMMAND_NEXT), val,
!val, 0, timeout_us, false);
diff = ktime_to_ms(ktime_sub(ktime_get_raw(), wait_loop_start));
} while (diff < max_timeout);
if (!err)
return true;
dev_err(kbdev->dev, "Timeout in waiting for job slot %u to become free for ctx %d_%u", js,
kctx->tgid, kctx->id);
@ -221,7 +218,7 @@ int kbase_job_hw_submit(struct kbase_device *kbdev, struct kbase_jd_atom *katom,
/* start MMU, medium priority, cache clean/flush on end, clean/flush on
* start
*/
cfg = kctx->as_nr;
cfg = (u32)kctx->as_nr;
if (kbase_hw_has_feature(kbdev, BASE_HW_FEATURE_FLUSH_REDUCTION) &&
!(kbdev->serialize_jobs & KBASE_SERIALIZE_RESET))
@ -386,10 +383,10 @@ void kbase_job_done(struct kbase_device *kbdev, u32 done)
/* Note: This is inherently unfair, as we always check for lower
* numbered interrupts before the higher numbered ones.
*/
i = ffs(finished) - 1;
i = (unsigned int)ffs((int)finished) - 1u;
do {
int nr_done;
u32 nr_done;
u32 active;
u32 completion_code = BASE_JD_EVENT_DONE; /* assume OK */
u64 job_tail = 0;
@ -453,7 +450,7 @@ void kbase_job_done(struct kbase_device *kbdev, u32 done)
}
kbase_reg_write32(kbdev, JOB_CONTROL_ENUM(JOB_IRQ_CLEAR),
done & ((1 << i) | (1 << (i + 16))));
done & ((1u << i) | (1u << (i + 16))));
active = kbase_reg_read32(kbdev, JOB_CONTROL_ENUM(JOB_IRQ_JS_STATE));
if (((active >> i) & 1) == 0 && (((done >> (i + 16)) & 1) == 0)) {
@ -514,8 +511,8 @@ void kbase_job_done(struct kbase_device *kbdev, u32 done)
nr_done -= (active >> i) & 1;
nr_done -= (active >> (i + 16)) & 1;
if (nr_done <= 0) {
dev_warn(kbdev->dev, "Spurious interrupt on slot %d", i);
if (nr_done == 0 || nr_done > SLOT_RB_SIZE) {
dev_warn(kbdev->dev, "Spurious interrupt on slot %u", i);
goto spurious;
}
@ -556,7 +553,7 @@ spurious:
finished = (done & 0xFFFF) | failed;
if (done)
end_timestamp = ktime_get_raw();
} while (finished & (1 << i));
} while (finished & (1u << i));
kbasep_job_slot_update_head_start_timestamp(kbdev, i, end_timestamp);
}
@ -580,7 +577,7 @@ void kbasep_job_slot_soft_or_hard_stop_do_action(struct kbase_device *kbdev, uns
u64 job_in_head_before;
u32 status_reg_after;
WARN_ON(action & (~JS_COMMAND_MASK));
WARN_ON(action & (~(u32)JS_COMMAND_MASK));
/* Check the head pointer */
job_in_head_before = kbase_reg_read64(kbdev, JOB_SLOT_OFFSET(js, HEAD));
@ -808,11 +805,12 @@ void kbase_jm_wait_for_zero_jobs(struct kbase_context *kctx)
struct kbase_device *kbdev = kctx->kbdev;
unsigned long timeout = msecs_to_jiffies(ZAP_TIMEOUT);
timeout = wait_event_timeout(kctx->jctx.zero_jobs_wait, kctx->jctx.job_nr == 0, timeout);
timeout = wait_event_timeout(kctx->jctx.zero_jobs_wait, kctx->jctx.job_nr == 0,
(long)timeout);
if (timeout != 0)
timeout = wait_event_timeout(kctx->jctx.sched_info.ctx.is_scheduled_wait,
!kbase_ctx_flag(kctx, KCTX_SCHEDULED), timeout);
!kbase_ctx_flag(kctx, KCTX_SCHEDULED), (long)timeout);
/* Neither wait timed out; all done! */
if (timeout != 0)
@ -899,7 +897,8 @@ void kbase_job_slot_softstop_swflags(struct kbase_device *kbdev, unsigned int js
JS_COMMAND_SOFT_STOP | sw_flags);
}
void kbase_job_slot_softstop(struct kbase_device *kbdev, int js, struct kbase_jd_atom *target_katom)
void kbase_job_slot_softstop(struct kbase_device *kbdev, unsigned int js,
struct kbase_jd_atom *target_katom)
{
kbase_job_slot_softstop_swflags(kbdev, js, target_katom, 0u);
}
@ -979,7 +978,7 @@ void kbase_reset_gpu_assert_failed_or_prevented(struct kbase_device *kbdev)
static void kbase_debug_dump_registers(struct kbase_device *kbdev)
{
int i;
unsigned int i;
kbase_io_history_dump(kbdev);
@ -991,7 +990,7 @@ static void kbase_debug_dump_registers(struct kbase_device *kbdev)
kbase_reg_read32(kbdev, JOB_CONTROL_ENUM(JOB_IRQ_RAWSTAT)),
kbase_reg_read32(kbdev, JOB_CONTROL_ENUM(JOB_IRQ_JS_STATE)));
for (i = 0; i < 3; i++) {
dev_err(kbdev->dev, " JS%d_STATUS=0x%08x JS%d_HEAD=0x%016llx", i,
dev_err(kbdev->dev, " JS%u_STATUS=0x%08x JS%u_HEAD=0x%016llx", i,
kbase_reg_read32(kbdev, JOB_SLOT_OFFSET(i, STATUS)), i,
kbase_reg_read64(kbdev, JOB_SLOT_OFFSET(i, HEAD)));
}
@ -1020,7 +1019,6 @@ static void kbasep_reset_timeout_worker(struct work_struct *data)
ktime_t end_timestamp = ktime_get_raw();
struct kbasep_js_device_data *js_devdata;
bool silent = false;
u32 max_loops = KBASE_CLEAN_CACHE_MAX_LOOPS;
kbdev = container_of(data, struct kbase_device, hwaccess.backend.reset_work);
@ -1085,13 +1083,15 @@ static void kbasep_reset_timeout_worker(struct work_struct *data)
kbdev->irq_reset_flush = false;
if (kbase_hw_has_issue(kbdev, BASE_HW_ISSUE_TMIX_8463)) {
/* Ensure that L2 is not transitioning when we send the reset
* command
*/
while (--max_loops && kbase_pm_get_trans_cores(kbdev, KBASE_PM_CORE_L2))
;
u64 val;
const u32 timeout_us =
kbase_get_timeout_ms(kbdev, KBASE_CLEAN_CACHE_TIMEOUT) * USEC_PER_MSEC;
/* Ensure that L2 is not transitioning when we send the reset command */
const int err = read_poll_timeout_atomic(kbase_pm_get_trans_cores, val, !val, 0,
timeout_us, false, kbdev,
KBASE_PM_CORE_L2);
WARN(!max_loops, "L2 power transition timed out while trying to reset\n");
WARN(err, "L2 power transition timed out while trying to reset\n");
}
mutex_lock(&kbdev->pm.lock);
@ -1209,7 +1209,7 @@ static enum hrtimer_restart kbasep_reset_timer_callback(struct hrtimer *timer)
static void kbasep_try_reset_gpu_early_locked(struct kbase_device *kbdev)
{
unsigned int i;
int pending_jobs = 0;
u32 pending_jobs = 0;
/* Count the number of jobs */
for (i = 0; i < kbdev->gpu_props.num_job_slots; i++)
@ -1263,7 +1263,7 @@ static void kbasep_try_reset_gpu_early(struct kbase_device *kbdev)
*/
bool kbase_prepare_to_reset_gpu_locked(struct kbase_device *kbdev, unsigned int flags)
{
int i;
unsigned int i;
#ifdef CONFIG_MALI_ARBITER_SUPPORT
if (kbase_pm_is_gpu_lost(kbdev)) {

23
drivers/gpu/arm/midgard/backend/gpu/mali_kbase_jm_rb.c
View File

@ -159,9 +159,9 @@ bool kbase_gpu_atoms_submitted_any(struct kbase_device *kbdev)
return false;
}
int kbase_backend_nr_atoms_submitted(struct kbase_device *kbdev, unsigned int js)
u32 kbase_backend_nr_atoms_submitted(struct kbase_device *kbdev, unsigned int js)
{
int nr = 0;
u32 nr = 0;
int i;
lockdep_assert_held(&kbdev->hwaccess_lock);
@ -539,7 +539,7 @@ static int kbase_gpu_protected_mode_reset(struct kbase_device *kbdev)
}
static int kbase_jm_protected_entry(struct kbase_device *kbdev, struct kbase_jd_atom **katom,
int idx, int js)
int idx, unsigned int js)
{
int err = 0;
@ -594,7 +594,7 @@ static int kbase_jm_protected_entry(struct kbase_device *kbdev, struct kbase_jd_
}
static int kbase_jm_enter_protected_mode(struct kbase_device *kbdev, struct kbase_jd_atom **katom,
int idx, int js)
int idx, unsigned int js)
{
int err = 0;
@ -758,7 +758,7 @@ static int kbase_jm_enter_protected_mode(struct kbase_device *kbdev, struct kbas
}
static int kbase_jm_exit_protected_mode(struct kbase_device *kbdev, struct kbase_jd_atom **katom,
int idx, int js)
int idx, unsigned int js)
{
int err = 0;
@ -1274,7 +1274,8 @@ void kbase_gpu_complete_hw(struct kbase_device *kbdev, unsigned int js, u32 comp
struct kbasep_js_device_data *js_devdata = &kbdev->js_data;
unsigned int i;
if (!kbase_ctx_flag(katom->kctx, KCTX_DYING)) {
if (!kbase_ctx_flag(katom->kctx, KCTX_DYING) &&
!kbase_ctx_flag(katom->kctx, KCTX_PAGE_FAULT_REPORT_SKIP)) {
dev_warn(kbdev->dev, "error detected from slot %d, job status 0x%08x (%s)",
js, completion_code, kbase_gpu_exception_name(completion_code));
@ -1383,7 +1384,7 @@ void kbase_gpu_complete_hw(struct kbase_device *kbdev, unsigned int js, u32 comp
/* Check if there are lower priority jobs to soft stop */
kbase_job_slot_ctx_priority_check_locked(kctx, katom);
kbase_jm_try_kick(kbdev, 1 << katom->slot_nr);
kbase_jm_try_kick(kbdev, 1UL << katom->slot_nr);
}
/* For partial shader core off L2 cache flush */
@ -1535,7 +1536,7 @@ static int should_stop_x_dep_slot(struct kbase_jd_atom *katom)
if (dep_atom->gpu_rb_state != KBASE_ATOM_GPU_RB_NOT_IN_SLOT_RB &&
dep_atom->gpu_rb_state != KBASE_ATOM_GPU_RB_RETURN_TO_JS)
return dep_atom->slot_nr;
return (int)dep_atom->slot_nr;
}
return -1;
}
@ -1714,10 +1715,12 @@ bool kbase_backend_soft_hard_stop_slot(struct kbase_device *kbdev, struct kbase_
}
if (stop_x_dep_idx0 != -1)
kbase_backend_soft_hard_stop_slot(kbdev, kctx, stop_x_dep_idx0, NULL, action);
kbase_backend_soft_hard_stop_slot(kbdev, kctx, (unsigned int)stop_x_dep_idx0, NULL,
action);
if (stop_x_dep_idx1 != -1)
kbase_backend_soft_hard_stop_slot(kbdev, kctx, stop_x_dep_idx1, NULL, action);
kbase_backend_soft_hard_stop_slot(kbdev, kctx, (unsigned int)stop_x_dep_idx1, NULL,
action);
return ret;
}

12
drivers/gpu/arm/midgard/backend/gpu/mali_kbase_js_backend.c
View File

@ -169,11 +169,11 @@ static enum hrtimer_restart timer_callback(struct hrtimer *timer)
* now. Hard stop the slot.
*/
#if !KBASE_DISABLE_SCHEDULING_HARD_STOPS
int ms = js_devdata->scheduling_period_ns / 1000000u;
u32 ms = js_devdata->scheduling_period_ns / 1000000u;
dev_warn(
kbdev->dev,
"JS: Job Hard-Stopped (took more than %lu ticks at %lu ms/tick)",
(unsigned long)ticks, (unsigned long)ms);
"JS: Job Hard-Stopped (took more than %u ticks at %u ms/tick)",
ticks, ms);
kbase_job_slot_hardstop(atom->kctx, s, atom);
#endif
} else if (ticks == gpu_reset_ticks) {
@ -204,11 +204,11 @@ static enum hrtimer_restart timer_callback(struct hrtimer *timer)
* ticks. Hard stop the slot.
*/
#if !KBASE_DISABLE_SCHEDULING_HARD_STOPS
int ms = js_devdata->scheduling_period_ns / 1000000u;
u32 ms = js_devdata->scheduling_period_ns / 1000000u;
dev_warn(
kbdev->dev,
"JS: Job Hard-Stopped (took more than %lu ticks at %lu ms/tick)",
(unsigned long)ticks, (unsigned long)ms);
"JS: Job Hard-Stopped (took more than %u ticks at %u ms/tick)",
ticks, ms);
kbase_job_slot_hardstop(atom->kctx, s, atom);
#endif
} else if (ticks == js_devdata->gpu_reset_ticks_dumping) {

73
drivers/gpu/arm/midgard/backend/gpu/mali_kbase_model_dummy.c
View File

@ -68,6 +68,8 @@
#include <backend/gpu/mali_kbase_model_linux.h>
#include <mali_kbase_mem_linux.h>
#include <asm/arch_timer.h>
#if MALI_USE_CSF
#include <csf/mali_kbase_csf_firmware.h>
@ -78,7 +80,7 @@
/* Array for storing the value of SELECT register for each type of core */
static u64 ipa_ctl_select_config[KBASE_IPA_CORE_TYPE_NUM];
static bool ipa_control_timer_enabled;
static u32 ipa_control_timer_enabled;
#endif
#if MALI_USE_CSF
@ -142,8 +144,8 @@ struct control_reg_values_t {
struct job_slot {
int job_active;
int job_queued;
int job_complete_irq_asserted;
int job_irq_mask;
u32 job_complete_irq_asserted;
u32 job_irq_mask;
int job_disabled;
};
@ -512,7 +514,7 @@ void *gpu_device_get_data(void *model)
return dummy->kbdev;
}
#define signal_int(m, s) m->slots[(s)].job_complete_irq_asserted = 1
#define signal_int(m, s) m->slots[(s)].job_complete_irq_asserted = 1u
static char *no_mali_gpu = CONFIG_MALI_NO_MALI_DEFAULT_GPU;
module_param(no_mali_gpu, charp, 0000);
@ -650,7 +652,7 @@ static void gpu_model_dump_prfcnt_blocks(u64 *values, u32 *out_index, u32 block_
for (block_idx = 0; block_idx < block_count; block_idx++) {
/* only dump values if core is present */
if (!(blocks_present & (1 << block_idx))) {
if (!(blocks_present & (1U << block_idx))) {
#if MALI_USE_CSF
/* if CSF dump zeroed out block */
memset(&prfcnt_base[*out_index], 0, KBASE_DUMMY_MODEL_BLOCK_SIZE);
@ -712,6 +714,11 @@ static void gpu_model_dump_nolock(void)
performance_counters.time += 10;
}
static void gpu_model_raise_irq(void *model, u32 irq)
{
gpu_device_raise_irq(model, irq);
}
#if !MALI_USE_CSF
static void midgard_model_dump_prfcnt(void)
{
@ -743,7 +750,7 @@ void gpu_model_glb_request_job_irq(void *model)
spin_lock_irqsave(&hw_error_status.access_lock, flags);
hw_error_status.job_irq_status |= JOB_IRQ_GLOBAL_IF;
spin_unlock_irqrestore(&hw_error_status.access_lock, flags);
gpu_device_raise_irq(model, MODEL_LINUX_JOB_IRQ);
gpu_model_raise_irq(model, MODEL_LINUX_JOB_IRQ);
}
#endif /* !MALI_USE_CSF */
@ -767,13 +774,13 @@ static void init_register_statuses(struct dummy_model_t *dummy)
for (i = 0; i < NUM_MMU_AS; i++) {
hw_error_status.as_command[i] = 0;
hw_error_status.as_faultstatus[i] = 0;
hw_error_status.mmu_irq_mask |= 1 << i;
hw_error_status.mmu_irq_mask |= (1u << i);
}
performance_counters.time = 0;
}
static void update_register_statuses(struct dummy_model_t *dummy, unsigned int job_slot)
static void update_register_statuses(struct dummy_model_t *dummy, u32 job_slot)
{
lockdep_assert_held(&hw_error_status.access_lock);
@ -915,7 +922,7 @@ static void update_register_statuses(struct dummy_model_t *dummy, unsigned int j
} /* end of job register statuses */
if (hw_error_status.errors_mask & IS_A_MMU_ERROR) {
int i;
u32 i;
for (i = 0; i < NUM_MMU_AS; i++) {
if (i == hw_error_status.faulty_mmu_as) {
@ -965,9 +972,10 @@ static void update_register_statuses(struct dummy_model_t *dummy, unsigned int j
if (hw_error_status.errors_mask & KBASE_TRANSTAB_BUS_FAULT)
hw_error_status.mmu_irq_rawstat |=
1 << (16 + i); /* bus error */
1u << (16 + i); /* bus error */
else
hw_error_status.mmu_irq_rawstat |= 1 << i; /* page fault */
hw_error_status.mmu_irq_rawstat |=
(1u << i); /* page fault */
}
}
} /*end of mmu register statuses */
@ -979,11 +987,11 @@ static void update_register_statuses(struct dummy_model_t *dummy, unsigned int j
hw_error_status.gpu_error_irq |= 1;
switch (hw_error_status.errors_mask & IS_A_GPU_ERROR) {
case KBASE_DELAYED_BUS_FAULT:
hw_error_status.gpu_fault_status = (1 << 7);
hw_error_status.gpu_fault_status = (1u << 7);
break;
case KBASE_SHAREABILITY_FAULT:
hw_error_status.gpu_fault_status = (1 << 7) | (1 << 3);
hw_error_status.gpu_fault_status = (1u << 7) | (1u << 3);
break;
default:
@ -1119,7 +1127,7 @@ static void midgard_model_get_outputs(void *h)
lockdep_assert_held(&hw_error_status.access_lock);
if (hw_error_status.job_irq_status)
gpu_device_raise_irq(dummy, MODEL_LINUX_JOB_IRQ);
gpu_model_raise_irq(dummy, MODEL_LINUX_JOB_IRQ);
if ((dummy->power_changed && dummy->power_changed_mask) ||
(dummy->reset_completed & dummy->reset_completed_mask) ||
@ -1130,16 +1138,16 @@ static void midgard_model_get_outputs(void *h)
(dummy->flush_pa_range_completed && dummy->flush_pa_range_completed_irq_enabled) ||
#endif
(dummy->clean_caches_completed && dummy->clean_caches_completed_irq_enabled))
gpu_device_raise_irq(dummy, MODEL_LINUX_GPU_IRQ);
gpu_model_raise_irq(dummy, MODEL_LINUX_GPU_IRQ);
if (hw_error_status.mmu_irq_rawstat & hw_error_status.mmu_irq_mask)
gpu_device_raise_irq(dummy, MODEL_LINUX_MMU_IRQ);
gpu_model_raise_irq(dummy, MODEL_LINUX_MMU_IRQ);
}
static void midgard_model_update(void *h)
{
struct dummy_model_t *dummy = (struct dummy_model_t *)h;
int i;
u32 i;
lockdep_assert_held(&hw_error_status.access_lock);
@ -1157,8 +1165,8 @@ static void midgard_model_update(void *h)
* as we will overwrite the register status of the job in
* the head registers - which has not yet been read
*/
if ((hw_error_status.job_irq_rawstat & (1 << (i + 16))) ||
(hw_error_status.job_irq_rawstat & (1 << i))) {
if ((hw_error_status.job_irq_rawstat & (1u << (i + 16))) ||
(hw_error_status.job_irq_rawstat & (1u << i))) {
continue;
}
@ -1169,7 +1177,7 @@ static void midgard_model_update(void *h)
#endif /* CONFIG_MALI_ERROR_INJECT */
update_register_statuses(dummy, i);
/*if this job slot returned failures we cannot use it */
if (hw_error_status.job_irq_rawstat & (1 << (i + 16))) {
if (hw_error_status.job_irq_rawstat & (1u << (i + 16))) {
dummy->slots[i].job_active = 0;
continue;
}
@ -1177,7 +1185,7 @@ static void midgard_model_update(void *h)
dummy->slots[i].job_active = dummy->slots[i].job_queued;
dummy->slots[i].job_queued = 0;
if (dummy->slots[i].job_active) {
if (hw_error_status.job_irq_rawstat & (1 << (i + 16)))
if (hw_error_status.job_irq_rawstat & (1u << (i + 16)))
model_error_log(KBASE_CORE,
"\natom %lld running a job on a dirty slot",
hw_error_status.current_jc);
@ -1193,7 +1201,7 @@ static void invalidate_active_jobs(struct dummy_model_t *dummy)
for (i = 0; i < NUM_SLOTS; i++) {
if (dummy->slots[i].job_active) {
hw_error_status.job_irq_rawstat |= (1 << (16 + i));
hw_error_status.job_irq_rawstat |= (1u << (16 + i));
hw_error_status.js_status[i] = 0x7f; /*UNKNOWN*/
}
@ -1256,7 +1264,7 @@ void midgard_model_write_reg(void *h, u32 addr, u32 value)
int i;
for (i = 0; i < NUM_SLOTS; i++) {
if (value & ((1 << i) | (1 << (i + 16))))
if (value & ((1u << i) | (1u << (i + 16))))
dummy->slots[i].job_complete_irq_asserted = 0;
/* hw_error_status.js_status[i] is cleared in
* update_job_irq_js_state
@ -1279,6 +1287,9 @@ void midgard_model_write_reg(void *h, u32 addr, u32 value)
hw_error_status.job_irq_rawstat &= ~(value);
hw_error_status.job_irq_status &= ~(value);
} else if (addr == JOB_CONTROL_REG(JOB_IRQ_RAWSTAT)) {
hw_error_status.job_irq_rawstat |= value;
hw_error_status.job_irq_status |= value;
} else if (addr == JOB_CONTROL_REG(JOB_IRQ_MASK)) {
/* ignore JOB_IRQ_MASK as it is handled by CSFFW */
#endif /* !MALI_USE_CSF */
@ -1378,7 +1389,7 @@ void midgard_model_write_reg(void *h, u32 addr, u32 value)
pr_debug("Received IPA_CONTROL command");
} else if (addr == IPA_CONTROL_REG(TIMER)
) {
ipa_control_timer_enabled = value ? true : false;
ipa_control_timer_enabled = value ? 1U : 0U;
} else if ((addr >= IPA_CONTROL_REG(SELECT_CSHW_LO)) &&
(addr <= IPA_CONTROL_REG(SELECT_SHADER_HI))) {
enum kbase_ipa_core_type core_type =
@ -1399,7 +1410,7 @@ void midgard_model_write_reg(void *h, u32 addr, u32 value)
hw_error_status.mmu_irq_rawstat &= (~value);
} else if ((addr >= MMU_STAGE1_REG(MMU_AS_REG(0, AS_TRANSTAB_LO))) &&
(addr <= MMU_STAGE1_REG(MMU_AS_REG(15, AS_STATUS)))) {
int mem_addr_space = (addr - MMU_STAGE1_REG(MMU_AS_REG(0, AS_TRANSTAB_LO))) >> 6;
u32 mem_addr_space = (addr - MMU_STAGE1_REG(MMU_AS_REG(0, AS_TRANSTAB_LO))) >> 6;
switch (addr & 0x3F) {
case AS_COMMAND:
@ -1622,7 +1633,7 @@ void midgard_model_read_reg(void *h, u32 addr, u32 *const value)
#if MALI_USE_CSF
((dummy->flush_pa_range_completed_irq_enabled ? 1u : 0u) << 20) |
#endif
(dummy->power_changed_mask << 9) | (1 << 7) | 1;
(dummy->power_changed_mask << 9) | (1u << 7) | 1u;
pr_debug("GPU_IRQ_MASK read %x", *value);
} else if (addr == GPU_CONTROL_REG(GPU_IRQ_RAWSTAT)) {
*value = ((dummy->clean_caches_completed ? 1u : 0u) << 17) |
@ -1891,7 +1902,7 @@ void midgard_model_read_reg(void *h, u32 addr, u32 *const value)
*value = 0;
} else if (addr >= MMU_STAGE1_REG(MMU_AS_REG(0, AS_TRANSTAB_LO)) &&
addr <= MMU_STAGE1_REG(MMU_AS_REG(15, AS_STATUS))) {
int mem_addr_space = (addr - MMU_STAGE1_REG(MMU_AS_REG(0, AS_TRANSTAB_LO))) >> 6;
u32 mem_addr_space = (addr - MMU_STAGE1_REG(MMU_AS_REG(0, AS_TRANSTAB_LO))) >> 6;
switch (addr & 0x3F) {
case AS_TRANSTAB_LO:
@ -1927,7 +1938,7 @@ void midgard_model_read_reg(void *h, u32 addr, u32 *const value)
default:
model_error_log(
KBASE_CORE,
"Dummy model register access: Reading unsupported MMU #%d register 0x%x. Returning 0\n",
"Dummy model register access: Reading unsupported MMU #%u register 0x%x. Returning 0\n",
mem_addr_space, addr);
*value = 0;
break;
@ -2155,3 +2166,9 @@ int gpu_model_control(void *model, struct kbase_model_control_params *params)
return 0;
}
u64 midgard_model_arch_timer_get_cntfrq(void *h)
{
CSTD_UNUSED(h);
return arch_timer_get_cntfrq();
}

6
drivers/gpu/arm/midgard/backend/gpu/mali_kbase_model_dummy.h
View File

@ -134,10 +134,10 @@ struct error_status_t {
u32 errors_mask;
u32 mmu_table_level;
int faulty_mmu_as;
u32 faulty_mmu_as;
u64 current_jc;
int current_job_slot;
u32 current_job_slot;
u32 job_irq_rawstat;
u32 job_irq_status;
@ -168,7 +168,7 @@ struct gpu_model_prfcnt_en {
u32 shader;
};
void midgard_set_error(int job_slot);
void midgard_set_error(u32 job_slot);
int job_atom_inject_error(struct kbase_error_params *params);
int gpu_model_control(void *h, struct kbase_model_control_params *params);

2
drivers/gpu/arm/midgard/backend/gpu/mali_kbase_model_error_generator.c
View File

@ -131,7 +131,7 @@ int job_atom_inject_error(struct kbase_error_params *params)
return 0;
}
void midgard_set_error(int job_slot)
void midgard_set_error(u32 job_slot)
{
#ifdef CONFIG_MALI_ERROR_INJECT_RANDOM
gpu_generate_error();

92
drivers/gpu/arm/midgard/backend/gpu/mali_kbase_model_linux.c
View File

@ -37,68 +37,39 @@ struct model_irq_data {
struct work_struct work;
};
static void serve_job_irq(struct work_struct *work)
{
struct model_irq_data *data = container_of(work, struct model_irq_data, work);
struct kbase_device *kbdev = data->kbdev;
/* Make sure no worker is already serving this IRQ */
while (atomic_cmpxchg(&kbdev->serving_job_irq, 1, 0) == 1) {
u32 val;
while ((val = kbase_reg_read32(kbdev, JOB_CONTROL_ENUM(JOB_IRQ_STATUS)))) {
unsigned long flags;
/* Handle the IRQ */
spin_lock_irqsave(&kbdev->hwaccess_lock, flags);
#if MALI_USE_CSF
kbase_csf_interrupt(kbdev, val);
#else
kbase_job_done(kbdev, val);
#endif
spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags);
}
#define DEFINE_SERVE_IRQ(irq_handler) \
static void serve_##irq_handler(struct work_struct *work) \
{ \
struct model_irq_data *data = container_of(work, struct model_irq_data, work); \
struct kbase_device *kbdev = data->kbdev; \
irq_handler(kbdev); \
kmem_cache_free(kbdev->irq_slab, data); \
}
kmem_cache_free(kbdev->irq_slab, data);
}
static void serve_gpu_irq(struct work_struct *work)
static void job_irq(struct kbase_device *kbdev)
{
struct model_irq_data *data = container_of(work, struct model_irq_data, work);
struct kbase_device *kbdev = data->kbdev;
/* Make sure no worker is already serving this IRQ */
while (atomic_cmpxchg(&kbdev->serving_gpu_irq, 1, 0) == 1) {
u32 val;
while ((val = kbase_reg_read32(kbdev, GPU_CONTROL_ENUM(GPU_IRQ_STATUS)))) {
/* Handle the GPU_IRQ */
kbase_gpu_interrupt(kbdev, val);
}
}
kmem_cache_free(kbdev->irq_slab, data);
while (atomic_cmpxchg(&kbdev->serving_job_irq, 1, 0) == 1)
kbase_get_interrupt_handler(kbdev, JOB_IRQ_TAG)(0, kbdev);
}
DEFINE_SERVE_IRQ(job_irq)
static void serve_mmu_irq(struct work_struct *work)
static void gpu_irq(struct kbase_device *kbdev)
{
struct model_irq_data *data = container_of(work, struct model_irq_data, work);
struct kbase_device *kbdev = data->kbdev;
/* Make sure no worker is already serving this IRQ */
if (atomic_cmpxchg(&kbdev->serving_mmu_irq, 1, 0) == 1) {
u32 val;
while ((val = kbase_reg_read32(kbdev, MMU_CONTROL_ENUM(IRQ_STATUS)))) {
/* Handle the IRQ */
kbase_mmu_interrupt(kbdev, val);
}
}
kmem_cache_free(kbdev->irq_slab, data);
while (atomic_cmpxchg(&kbdev->serving_gpu_irq, 1, 0) == 1)
kbase_get_interrupt_handler(kbdev, GPU_IRQ_TAG)(0, kbdev);
}
DEFINE_SERVE_IRQ(gpu_irq)
static void mmu_irq(struct kbase_device *kbdev)
{
/* Make sure no worker is already serving this IRQ */
while (atomic_cmpxchg(&kbdev->serving_mmu_irq, 1, 0) == 1)
kbase_get_interrupt_handler(kbdev, MMU_IRQ_TAG)(0, kbdev);
}
DEFINE_SERVE_IRQ(mmu_irq)
void gpu_device_raise_irq(void *model, u32 irq)
{
@ -156,6 +127,9 @@ int kbase_install_interrupts(struct kbase_device *kbdev)
return -ENOMEM;
}
kbdev->nr_irqs = 3;
return 0;
}
@ -175,23 +149,13 @@ void kbase_synchronize_irqs(struct kbase_device *kbdev)
KBASE_EXPORT_TEST_API(kbase_synchronize_irqs);
int kbase_set_custom_irq_handler(struct kbase_device *kbdev, irq_handler_t custom_handler,
int irq_type)
u32 irq_tag)
{
return 0;
}
KBASE_EXPORT_TEST_API(kbase_set_custom_irq_handler);
irqreturn_t kbase_gpu_irq_test_handler(int irq, void *data, u32 val)
{
if (!val)
return IRQ_NONE;
return IRQ_HANDLED;
}
KBASE_EXPORT_TEST_API(kbase_gpu_irq_test_handler);
int kbase_gpu_device_create(struct kbase_device *kbdev)
{
kbdev->model = midgard_model_create(kbdev);

11
drivers/gpu/arm/midgard/backend/gpu/mali_kbase_model_linux.h
View File

@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
*
* (C) COPYRIGHT 2019-2022 ARM Limited. All rights reserved.
* (C) COPYRIGHT 2014-2023 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
@ -116,6 +116,15 @@ void midgard_model_write_reg(void *h, u32 addr, u32 value);
*/
void midgard_model_read_reg(void *h, u32 addr, u32 *const value);
/**
* midgard_model_arch_timer_get_cntfrq - Get Model specific System Timer Frequency
*
* @h: Model handle.
*
* Return: Frequency in Hz
*/
u64 midgard_model_arch_timer_get_cntfrq(void *h);
/**
* gpu_device_raise_irq() - Private IRQ raise function.
*

104
drivers/gpu/arm/midgard/backend/gpu/mali_kbase_pm_backend.c
View File

@ -33,6 +33,7 @@
#include <backend/gpu/mali_kbase_js_internal.h>
#include <backend/gpu/mali_kbase_jm_internal.h>
#else
#include <linux/version_compat_defs.h>
#include <linux/pm_runtime.h>
#include <mali_kbase_reset_gpu.h>
#endif /* !MALI_USE_CSF */
@ -42,6 +43,7 @@
#include <mali_kbase_dummy_job_wa.h>
#include <backend/gpu/mali_kbase_irq_internal.h>
static void kbase_pm_gpu_poweroff_wait_wq(struct work_struct *data);
static void kbase_pm_hwcnt_disable_worker(struct work_struct *data);
static void kbase_pm_gpu_clock_control_worker(struct work_struct *data);
@ -51,6 +53,8 @@ int kbase_pm_runtime_init(struct kbase_device *kbdev)
struct kbase_pm_callback_conf *callbacks;
callbacks = (struct kbase_pm_callback_conf *)POWER_MANAGEMENT_CALLBACKS;
if (callbacks) {
kbdev->pm.backend.callback_power_on = callbacks->power_on_callback;
kbdev->pm.backend.callback_power_off = callbacks->power_off_callback;
@ -178,6 +182,10 @@ int kbase_hwaccess_pm_init(struct kbase_device *kbdev)
!kbase_hw_has_issue(kbdev, BASE_HW_ISSUE_TURSEHW_1997) &&
kbdev->pm.backend.callback_power_runtime_gpu_active &&
kbdev->pm.backend.callback_power_runtime_gpu_idle;
kbdev->pm.backend.apply_hw_issue_TITANHW_2938_wa =
kbase_hw_has_issue(kbdev, BASE_HW_ISSUE_TITANHW_2938) &&
kbdev->pm.backend.gpu_sleep_supported;
#endif
if (IS_ENABLED(CONFIG_MALI_HW_ERRATA_1485982_NOT_AFFECTED))
@ -239,6 +247,58 @@ void kbase_pm_do_poweron(struct kbase_device *kbdev, bool is_resume)
*/
}
#if MALI_USE_CSF
static bool wait_cond_mmu_fault_handling_in_gpu_poweroff_wait_wq(struct kbase_device *kbdev,
int faults_pending)
{
struct kbase_pm_backend_data *backend = &kbdev->pm.backend;
bool cond = false;
kbase_pm_lock(kbdev);
cond = backend->poweron_required || (faults_pending == 0);
kbase_pm_unlock(kbdev);
return cond;
}
#endif
static void wait_for_mmu_fault_handling_in_gpu_poweroff_wait_wq(struct kbase_device *kbdev)
{
#if MALI_USE_CSF
bool reset_triggered = false;
int ret = 0;
lockdep_assert_held(&kbdev->pm.lock);
do {
const u64 timeout_us = kbase_get_timeout_ms(kbdev, CSF_PM_TIMEOUT) * USEC_PER_MSEC;
const unsigned long delay_us = 10;
int faults_pending = 0;
kbase_pm_unlock(kbdev);
ret = read_poll_timeout_atomic(
atomic_read, faults_pending,
wait_cond_mmu_fault_handling_in_gpu_poweroff_wait_wq(kbdev, faults_pending),
delay_us, timeout_us, false, &kbdev->faults_pending);
kbase_pm_lock(kbdev);
if (ret && !reset_triggered) {
dev_err(kbdev->dev,
"Wait for fault handling timed-out in gpu_poweroff_wait_wq");
if (kbase_prepare_to_reset_gpu(kbdev,
RESET_FLAGS_HWC_UNRECOVERABLE_ERROR)) {
kbase_reset_gpu(kbdev);
reset_triggered = true;
}
}
} while (ret);
#else
kbase_pm_unlock(kbdev);
kbase_flush_mmu_wqs(kbdev);
kbase_pm_lock(kbdev);
#endif
}
static void pm_handle_power_off(struct kbase_device *kbdev)
{
struct kbase_pm_backend_data *backend = &kbdev->pm.backend;
@ -283,9 +343,7 @@ static void pm_handle_power_off(struct kbase_device *kbdev)
* process. Interrupts are disabled so no more faults
* should be generated at this point.
*/
kbase_pm_unlock(kbdev);
kbase_flush_mmu_wqs(kbdev);
kbase_pm_lock(kbdev);
wait_for_mmu_fault_handling_in_gpu_poweroff_wait_wq(kbdev);
#ifdef CONFIG_MALI_ARBITER_SUPPORT
/* poweron_required may have changed while pm lock
@ -698,12 +756,6 @@ int kbase_hwaccess_pm_powerup(struct kbase_device *kbdev, unsigned int flags)
kbdev->pm.backend.gpu_cycle_counter_requests = 0;
spin_unlock_irqrestore(&kbdev->pm.backend.gpu_cycle_counter_requests_lock, irq_flags);
/* We are ready to receive IRQ's now as power policy is set up, so
* enable them now.
*/
#ifdef CONFIG_MALI_DEBUG
kbdev->pm.backend.driver_ready_for_irqs = true;
#endif
kbase_pm_enable_interrupts(kbdev);
WARN_ON(!kbdev->pm.backend.gpu_powered);
@ -910,7 +962,9 @@ void kbase_hwaccess_pm_resume(struct kbase_device *kbdev)
void kbase_pm_handle_gpu_lost(struct kbase_device *kbdev)
{
unsigned long flags;
#if !MALI_USE_CSF
ktime_t end_timestamp = ktime_get_raw();
#endif
struct kbase_arbiter_vm_state *arb_vm_state = kbdev->pm.arb_vm_state;
if (!kbdev->arb.arb_if)
@ -937,11 +991,14 @@ void kbase_pm_handle_gpu_lost(struct kbase_device *kbdev)
/* Clear all jobs running on the GPU */
spin_lock_irqsave(&kbdev->hwaccess_lock, flags);
kbdev->protected_mode = false;
#if !MALI_USE_CSF
kbase_backend_reset(kbdev, &end_timestamp);
kbase_pm_metrics_update(kbdev, NULL);
#endif
kbase_pm_update_state(kbdev);
spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags);
#if !MALI_USE_CSF
/* Cancel any pending HWC dumps */
spin_lock_irqsave(&kbdev->hwcnt.lock, flags);
if (kbdev->hwcnt.backend.state == KBASE_INSTR_STATE_DUMPING ||
@ -951,6 +1008,7 @@ void kbase_pm_handle_gpu_lost(struct kbase_device *kbdev)
wake_up(&kbdev->hwcnt.backend.wait);
}
spin_unlock_irqrestore(&kbdev->hwcnt.lock, flags);
#endif
}
mutex_unlock(&arb_vm_state->vm_state_lock);
mutex_unlock(&kbdev->pm.lock);
@ -968,6 +1026,7 @@ int kbase_pm_force_mcu_wakeup_after_sleep(struct kbase_device *kbdev)
spin_lock_irqsave(&kbdev->hwaccess_lock, flags);
/* Set the override flag to force the power up of L2 cache */
kbdev->pm.backend.gpu_wakeup_override = true;
kbdev->pm.backend.runtime_suspend_abort_reason = ABORT_REASON_NONE;
kbase_pm_update_state(kbdev);
spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags);
@ -1003,14 +1062,27 @@ static int pm_handle_mcu_sleep_on_runtime_suspend(struct kbase_device *kbdev)
return ret;
}
/* Check if a Doorbell mirror interrupt occurred meanwhile */
/* Check if a Doorbell mirror interrupt occurred meanwhile.
* Also check if GPU idle work item is pending. If FW had sent the GPU idle notification
* after the wake up of MCU then it can be assumed that Userspace submission didn't make
* GPU non-idle, so runtime suspend doesn't need to be aborted.
*/
spin_lock_irqsave(&kbdev->hwaccess_lock, flags);
if (kbdev->pm.backend.gpu_sleep_mode_active && kbdev->pm.backend.exit_gpu_sleep_mode) {
dev_dbg(kbdev->dev,
"DB mirror interrupt occurred during runtime suspend after L2 power up");
kbdev->pm.backend.gpu_wakeup_override = false;
spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags);
return -EBUSY;
if (kbdev->pm.backend.gpu_sleep_mode_active && kbdev->pm.backend.exit_gpu_sleep_mode &&
!work_pending(&kbdev->csf.scheduler.gpu_idle_work)) {
u32 glb_req =
kbase_csf_firmware_global_input_read(&kbdev->csf.global_iface, GLB_REQ);
u32 glb_ack = kbase_csf_firmware_global_output(&kbdev->csf.global_iface, GLB_ACK);
/* Only abort the runtime suspend if GPU idle event is not pending */
if (!((glb_req ^ glb_ack) & GLB_REQ_IDLE_EVENT_MASK)) {
dev_dbg(kbdev->dev,
"DB mirror interrupt occurred during runtime suspend after L2 power up");
kbdev->pm.backend.gpu_wakeup_override = false;
kbdev->pm.backend.runtime_suspend_abort_reason = ABORT_REASON_DB_MIRROR_IRQ;
spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags);
return -EBUSY;
}
}
spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags);
/* Need to release the kbdev->pm.lock to avoid lock ordering issue

12
drivers/gpu/arm/midgard/backend/gpu/mali_kbase_pm_ca.c
View File

@ -109,13 +109,19 @@ unlock:
KBASE_EXPORT_TEST_API(kbase_devfreq_set_core_mask);
#endif
u64 kbase_pm_ca_get_core_mask(struct kbase_device *kbdev)
u64 kbase_pm_ca_get_debug_core_mask(struct kbase_device *kbdev)
{
#if MALI_USE_CSF
u64 debug_core_mask = kbdev->pm.debug_core_mask;
return kbdev->pm.debug_core_mask;
#else
u64 debug_core_mask = kbdev->pm.debug_core_mask_all;
return kbdev->pm.debug_core_mask_all;
#endif
}
KBASE_EXPORT_TEST_API(kbase_pm_ca_get_debug_core_mask);
u64 kbase_pm_ca_get_core_mask(struct kbase_device *kbdev)
{
u64 debug_core_mask = kbase_pm_ca_get_debug_core_mask(kbdev);
lockdep_assert_held(&kbdev->hwaccess_lock);

11
drivers/gpu/arm/midgard/backend/gpu/mali_kbase_pm_ca.h
View File

@ -57,6 +57,17 @@ void kbase_pm_ca_term(struct kbase_device *kbdev);
*/
u64 kbase_pm_ca_get_core_mask(struct kbase_device *kbdev);
/**
* kbase_pm_ca_get_debug_core_mask - Get debug core mask.
*
* @kbdev: The kbase device structure for the device (must be a valid pointer)
*
* Returns a mask of the currently selected shader cores.
*
* Return: The bit mask of user-selected cores
*/
u64 kbase_pm_ca_get_debug_core_mask(struct kbase_device *kbdev);
/**
* kbase_pm_ca_update_core_status - Update core status
*

34
drivers/gpu/arm/midgard/backend/gpu/mali_kbase_pm_defs.h
View File

@ -29,6 +29,8 @@
#include "mali_kbase_pm_always_on.h"
#include "mali_kbase_pm_coarse_demand.h"
#include <hw_access/mali_kbase_hw_access_regmap.h>
#if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM)
#define KBASE_PM_RUNTIME 1
#endif
@ -97,6 +99,21 @@ enum kbase_shader_core_state {
#undef KBASEP_SHADER_STATE
};
/**
* enum kbase_pm_runtime_suspend_abort_reason - Reason why runtime suspend was aborted
* after the wake up of MCU.
*
* @ABORT_REASON_NONE: Not aborted
* @ABORT_REASON_DB_MIRROR_IRQ: Runtime suspend was aborted due to DB_MIRROR irq.
* @ABORT_REASON_NON_IDLE_CGS: Runtime suspend was aborted as CSGs were detected as non-idle after
* their suspension.
*/
enum kbase_pm_runtime_suspend_abort_reason {
ABORT_REASON_NONE,
ABORT_REASON_DB_MIRROR_IRQ,
ABORT_REASON_NON_IDLE_CGS
};
/**
* struct kbasep_pm_metrics - Metrics data collected for use by the power
* management framework.
@ -248,9 +265,6 @@ union kbase_pm_policy_data {
* states and transitions.
* @cg1_disabled: Set if the policy wants to keep the second core group
* powered off
* @driver_ready_for_irqs: Debug state indicating whether sufficient
* initialization of the driver has occurred to handle
* IRQs
* @metrics: Structure to hold metrics for the GPU
* @shader_tick_timer: Structure to hold the shader poweroff tick timer state
* @poweroff_wait_in_progress: true if a wait for GPU power off is in progress.
@ -290,6 +304,8 @@ union kbase_pm_policy_data {
* called previously.
* See &struct kbase_pm_callback_conf.
* @ca_cores_enabled: Cores that are currently available
* @apply_hw_issue_TITANHW_2938_wa: Indicates if the workaround for BASE_HW_ISSUE_TITANHW_2938
* needs to be applied when unmapping memory from GPU.
* @mcu_state: The current state of the micro-control unit, only applicable
* to GPUs that have such a component
* @l2_state: The current state of the L2 cache state machine. See
@ -358,6 +374,12 @@ union kbase_pm_policy_data {
* mode for the saving the HW state before power down.
* @db_mirror_interrupt_enabled: Flag tracking if the Doorbell mirror interrupt
* is enabled or not.
* @runtime_suspend_abort_reason: Tracks if the runtime suspend was aborted,
* after the wake up of MCU, due to the DB_MIRROR irq
* or non-idle CSGs. Tracking is done to avoid
* redundant transition of MCU to sleep state after the
* abort of runtime suspend and before the resumption
* of scheduling.
* @l2_force_off_after_mcu_halt: Flag to indicate that L2 cache power down is
* must after performing the MCU halt. Flag is set
* immediately after the MCU halt and cleared
@ -427,10 +449,6 @@ struct kbase_pm_backend_data {
bool cg1_disabled;
#ifdef CONFIG_MALI_DEBUG
bool driver_ready_for_irqs;
#endif /* CONFIG_MALI_DEBUG */
struct kbasep_pm_metrics_state metrics;
struct kbasep_pm_tick_timer_state shader_tick_timer;
@ -458,6 +476,7 @@ struct kbase_pm_backend_data {
u64 ca_cores_enabled;
#if MALI_USE_CSF
bool apply_hw_issue_TITANHW_2938_wa;
enum kbase_mcu_state mcu_state;
#endif
enum kbase_l2_core_state l2_state;
@ -479,6 +498,7 @@ struct kbase_pm_backend_data {
bool gpu_idled;
bool gpu_wakeup_override;
bool db_mirror_interrupt_enabled;
enum kbase_pm_runtime_suspend_abort_reason runtime_suspend_abort_reason;
#endif
bool l2_force_off_after_mcu_halt;

65
drivers/gpu/arm/midgard/backend/gpu/mali_kbase_pm_driver.c
View File

@ -114,7 +114,8 @@ bool kbase_pm_is_mcu_desired(struct kbase_device *kbdev)
return true;
#ifdef KBASE_PM_RUNTIME
if (kbdev->pm.backend.gpu_wakeup_override)
if (kbdev->pm.backend.gpu_wakeup_override ||
kbdev->pm.backend.runtime_suspend_abort_reason != ABORT_REASON_NONE)
return true;
#endif
@ -351,12 +352,14 @@ __pure static u32 map_core_type_to_tl_pm_state(struct kbase_device *kbdev,
}
#endif
#if IS_ENABLED(CONFIG_ARM64)
#if IS_ENABLED(CONFIG_ARM64) && !MALI_USE_CSF
static void mali_cci_flush_l2(struct kbase_device *kbdev)
{
u32 val;
const u32 mask = CLEAN_CACHES_COMPLETED | RESET_COMPLETED;
u32 loops = KBASE_CLEAN_CACHE_MAX_LOOPS;
u32 raw;
const u32 timeout_us =
kbase_get_timeout_ms(kbdev, KBASE_CLEAN_CACHE_TIMEOUT) * USEC_PER_MSEC;
/*
* Note that we don't take the cache flush mutex here since
@ -368,14 +371,11 @@ static void mali_cci_flush_l2(struct kbase_device *kbdev)
kbase_reg_write32(kbdev, GPU_CONTROL_ENUM(GPU_COMMAND), GPU_COMMAND_CACHE_CLN_INV_L2);
raw = kbase_reg_read32(kbdev, GPU_CONTROL_ENUM(GPU_IRQ_RAWSTAT));
/* Wait for cache flush to complete before continuing, exit on
* gpu resets or loop expiry.
*/
while (((raw & mask) == 0) && --loops) {
raw = kbase_reg_read32(kbdev, GPU_CONTROL_ENUM(GPU_IRQ_RAWSTAT));
}
kbase_reg_poll32_timeout(kbdev, GPU_CONTROL_ENUM(GPU_IRQ_RAWSTAT), val, val & mask, 0,
timeout_us, false);
}
#endif
@ -632,7 +632,7 @@ static void kbase_pm_l2_config_override(struct kbase_device *kbdev)
val |= (kbdev->l2_hash_override << L2_CONFIG_HASH_SHIFT);
} else if (kbdev->l2_hash_values_override) {
#if MALI_USE_CSF
int i;
uint i;
WARN_ON(!kbase_hw_has_l2_slice_hash_feature(kbdev));
@ -640,7 +640,7 @@ static void kbase_pm_l2_config_override(struct kbase_device *kbdev)
val |= (0x1 << L2_CONFIG_L2_SLICE_HASH_ENABLE_SHIFT);
for (i = 0; i < GPU_L2_SLICE_HASH_COUNT; i++) {
/* L2_SLICE_HASH and ASN_HASH alias each other */
dev_dbg(kbdev->dev, "Program 0x%x to ASN_HASH[%d]\n",
dev_dbg(kbdev->dev, "Program 0x%x to ASN_HASH[%u]\n",
kbdev->l2_hash_values[i], i);
kbase_reg_write32(kbdev, GPU_L2_SLICE_HASH_OFFSET(i),
kbdev->l2_hash_values[i]);
@ -757,19 +757,20 @@ static void kbase_pm_enable_mcu_db_notification(struct kbase_device *kbdev)
*/
static void wait_mcu_as_inactive(struct kbase_device *kbdev)
{
unsigned int max_loops = KBASE_AS_INACTIVE_MAX_LOOPS;
u32 val;
int err;
const u32 timeout_us =
kbase_get_timeout_ms(kbdev, KBASE_AS_INACTIVE_TIMEOUT) * USEC_PER_MSEC;
lockdep_assert_held(&kbdev->hwaccess_lock);
if (!kbase_hw_has_issue(kbdev, BASE_HW_ISSUE_TURSEHW_2716))
return;
/* Wait for the AS_ACTIVE_INT bit to become 0 for the AS used by MCU FW */
while (--max_loops && kbase_reg_read32(kbdev, MMU_AS_OFFSET(MCU_AS_NR, STATUS)) &
AS_STATUS_AS_ACTIVE_INT_MASK)
;
if (!WARN_ON_ONCE(max_loops == 0))
err = kbase_reg_poll32_timeout(kbdev, MMU_AS_OFFSET(MCU_AS_NR, STATUS), val,
!(val & AS_STATUS_AS_ACTIVE_INT_MASK), 10, timeout_us,
false);
if (!WARN_ON_ONCE(err == -ETIMEDOUT))
return;
dev_err(kbdev->dev, "AS_ACTIVE_INT bit stuck for AS %d used by MCU FW", MCU_AS_NR);
@ -1341,15 +1342,8 @@ static void kbase_pm_l2_clear_backend_slot_submit_kctx(struct kbase_device *kbde
static bool can_power_down_l2(struct kbase_device *kbdev)
{
#if MALI_USE_CSF
/* Due to the HW issue GPU2019-3878, need to prevent L2 power off
* whilst MMU command is in progress.
* Also defer the power-down if MMU is in process of page migration.
*/
return !kbdev->mmu_hw_operation_in_progress && !kbdev->mmu_page_migrate_in_progress;
#else
/* Defer the power-down if MMU is in process of page migration. */
return !kbdev->mmu_page_migrate_in_progress;
#endif
}
static bool can_power_up_l2(struct kbase_device *kbdev)
@ -1508,7 +1502,7 @@ static int kbase_pm_l2_update_state(struct kbase_device *kbdev)
* must power them on explicitly.
*/
if (l2_present != 1)
kbase_pm_invoke(kbdev, KBASE_PM_CORE_L2, l2_present & ~1,
kbase_pm_invoke(kbdev, KBASE_PM_CORE_L2, l2_present & ~1ULL,
ACTION_PWRON);
/* Clear backend slot submission kctx */
kbase_pm_l2_clear_backend_slot_submit_kctx(kbdev);
@ -2501,7 +2495,8 @@ int kbase_pm_wait_for_l2_powered(struct kbase_device *kbdev)
spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags);
#if MALI_USE_CSF
timeout = kbase_csf_timeout_in_jiffies(kbase_get_timeout_ms(kbdev, CSF_PM_TIMEOUT));
timeout = (unsigned long)kbase_csf_timeout_in_jiffies(
kbase_get_timeout_ms(kbdev, CSF_PM_TIMEOUT));
#else
timeout = msecs_to_jiffies(PM_TIMEOUT_MS);
#endif
@ -2510,11 +2505,11 @@ int kbase_pm_wait_for_l2_powered(struct kbase_device *kbdev)
#if KERNEL_VERSION(4, 13, 1) <= LINUX_VERSION_CODE
remaining = wait_event_killable_timeout(kbdev->pm.backend.gpu_in_desired_state_wait,
kbase_pm_is_in_desired_state_with_l2_powered(kbdev),
timeout);
(long)timeout);
#else
remaining = wait_event_timeout(kbdev->pm.backend.gpu_in_desired_state_wait,
kbase_pm_is_in_desired_state_with_l2_powered(kbdev),
timeout);
(long)timeout);
#endif
if (!remaining) {
@ -2535,7 +2530,7 @@ static int pm_wait_for_desired_state(struct kbase_device *kbdev, bool killable_w
#if MALI_USE_CSF
long timeout = kbase_csf_timeout_in_jiffies(kbase_get_timeout_ms(kbdev, CSF_PM_TIMEOUT));
#else
long timeout = msecs_to_jiffies(PM_TIMEOUT_MS);
long timeout = (long)msecs_to_jiffies(PM_TIMEOUT_MS);
#endif
int err = 0;
@ -2662,7 +2657,7 @@ static int pm_wait_for_poweroff_work_complete(struct kbase_device *kbdev, bool k
/* Handling of timeout error isn't supported for arbiter builds */
const long timeout = MAX_SCHEDULE_TIMEOUT;
#else
const long timeout = msecs_to_jiffies(PM_TIMEOUT_MS);
const long timeout = (long)msecs_to_jiffies(PM_TIMEOUT_MS);
#endif
#endif
int err = 0;
@ -3081,7 +3076,7 @@ static int kbase_set_gpu_quirks(struct kbase_device *kbdev)
#endif /* !MALI_USE_CSF */
if (kbase_hw_has_feature(kbdev, BASE_HW_FEATURE_IDVS_GROUP_SIZE)) {
int default_idvs_group_size = 0xF;
u32 default_idvs_group_size = 0xF;
u32 group_size = 0;
if (of_property_read_u32(kbdev->dev->of_node, "idvs-group-size", &group_size))
@ -3219,6 +3214,7 @@ static void kbase_pm_hw_issues_apply(struct kbase_device *kbdev)
void kbase_pm_cache_snoop_enable(struct kbase_device *kbdev)
{
#if !MALI_USE_CSF
if ((kbdev->current_gpu_coherency_mode == COHERENCY_ACE) && !kbdev->cci_snoop_enabled) {
#if IS_ENABLED(CONFIG_ARM64)
if (kbdev->snoop_enable_smc != 0)
@ -3227,10 +3223,12 @@ void kbase_pm_cache_snoop_enable(struct kbase_device *kbdev)
dev_dbg(kbdev->dev, "MALI - CCI Snoops - Enabled\n");
kbdev->cci_snoop_enabled = true;
}
#endif /* !MALI_USE_CSF */
}
void kbase_pm_cache_snoop_disable(struct kbase_device *kbdev)
{
#if !MALI_USE_CSF
if (kbdev->cci_snoop_enabled) {
#if IS_ENABLED(CONFIG_ARM64)
if (kbdev->snoop_disable_smc != 0) {
@ -3241,6 +3239,7 @@ void kbase_pm_cache_snoop_disable(struct kbase_device *kbdev)
dev_dbg(kbdev->dev, "MALI - CCI Snoops Disabled\n");
kbdev->cci_snoop_enabled = false;
}
#endif /* !MALI_USE_CSF */
}
#if !MALI_USE_CSF

1
drivers/gpu/arm/midgard/backend/gpu/mali_kbase_pm_internal.h
View File

@ -1041,4 +1041,5 @@ static inline bool kbase_pm_l2_allow_mmu_page_migration(struct kbase_device *kbd
return (backend->l2_state != KBASE_L2_PEND_ON && backend->l2_state != KBASE_L2_PEND_OFF);
}
#endif /* _KBASE_BACKEND_PM_INTERNAL_H_ */

2
drivers/gpu/arm/midgard/backend/gpu/mali_kbase_pm_metrics.c
View File

@ -454,7 +454,7 @@ static void kbase_pm_metrics_active_calc(struct kbase_device *kbdev)
if (katom && katom->gpu_rb_state == KBASE_ATOM_GPU_RB_SUBMITTED) {
if (katom->core_req & BASE_JD_REQ_ONLY_COMPUTE) {
int device_nr =
u32 device_nr =
(katom->core_req & BASE_JD_REQ_SPECIFIC_COHERENT_GROUP) ?
katom->device_nr :
0;

9
drivers/gpu/arm/midgard/backend/gpu/mali_kbase_pm_policy.c
View File

@ -228,7 +228,8 @@ void kbase_pm_update_cores_state(struct kbase_device *kbdev)
spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags);
}
int kbase_pm_list_policies(struct kbase_device *kbdev, const struct kbase_pm_policy *const **list)
size_t kbase_pm_list_policies(struct kbase_device *kbdev,
const struct kbase_pm_policy *const **list)
{
CSTD_UNUSED(kbdev);
if (list)
@ -294,7 +295,7 @@ void kbase_pm_set_policy(struct kbase_device *kbdev, const struct kbase_pm_polic
bool reset_gpu = false;
bool reset_op_prevented = true;
struct kbase_csf_scheduler *scheduler = NULL;
u32 pwroff;
u64 pwroff_ns;
bool switching_to_always_on;
#endif
@ -304,9 +305,9 @@ void kbase_pm_set_policy(struct kbase_device *kbdev, const struct kbase_pm_polic
KBASE_KTRACE_ADD(kbdev, PM_SET_POLICY, NULL, new_policy->id);
#if MALI_USE_CSF
pwroff = kbase_csf_firmware_get_mcu_core_pwroff_time(kbdev);
pwroff_ns = kbase_csf_firmware_get_mcu_core_pwroff_time(kbdev);
switching_to_always_on = new_policy == &kbase_pm_always_on_policy_ops;
if (pwroff == 0 && !switching_to_always_on) {
if (pwroff_ns == 0 && !switching_to_always_on) {
dev_warn(
kbdev->dev,
"power_policy: cannot switch away from always_on with mcu_shader_pwroff_timeout set to 0\n");

43
drivers/gpu/arm/midgard/backend/gpu/mali_kbase_time.c
View File

@ -22,7 +22,6 @@
#include <mali_kbase.h>
#include <mali_kbase_hwaccess_time.h>
#if MALI_USE_CSF
#include <asm/arch_timer.h>
#include <linux/gcd.h>
#include <csf/mali_kbase_csf_timeout.h>
#endif
@ -30,6 +29,11 @@
#include <backend/gpu/mali_kbase_pm_internal.h>
#include <mali_kbase_config_defaults.h>
#include <linux/version_compat_defs.h>
#include <asm/arch_timer.h>
#if !IS_ENABLED(CONFIG_MALI_REAL_HW)
#include <backend/gpu/mali_kbase_model_linux.h>
#endif
struct kbase_timeout_info {
char *selector_str;
@ -53,6 +57,15 @@ static struct kbase_timeout_info timeout_info[KBASE_TIMEOUT_SELECTOR_COUNT] = {
MMU_AS_INACTIVE_WAIT_TIMEOUT_CYCLES },
[KCPU_FENCE_SIGNAL_TIMEOUT] = { "KCPU_FENCE_SIGNAL_TIMEOUT",
KCPU_FENCE_SIGNAL_TIMEOUT_CYCLES },
[KBASE_PRFCNT_ACTIVE_TIMEOUT] = { "KBASE_PRFCNT_ACTIVE_TIMEOUT",
KBASE_PRFCNT_ACTIVE_TIMEOUT_CYCLES },
[KBASE_CLEAN_CACHE_TIMEOUT] = { "KBASE_CLEAN_CACHE_TIMEOUT",
KBASE_CLEAN_CACHE_TIMEOUT_CYCLES },
[KBASE_AS_INACTIVE_TIMEOUT] = { "KBASE_AS_INACTIVE_TIMEOUT",
KBASE_AS_INACTIVE_TIMEOUT_CYCLES },
[IPA_INACTIVE_TIMEOUT] = { "IPA_INACTIVE_TIMEOUT", IPA_INACTIVE_TIMEOUT_CYCLES },
[CSF_FIRMWARE_STOP_TIMEOUT] = { "CSF_FIRMWARE_STOP_TIMEOUT",
CSF_FIRMWARE_STOP_TIMEOUT_CYCLES },
};
#else
static struct kbase_timeout_info timeout_info[KBASE_TIMEOUT_SELECTOR_COUNT] = {
@ -60,6 +73,12 @@ static struct kbase_timeout_info timeout_info[KBASE_TIMEOUT_SELECTOR_COUNT] = {
MMU_AS_INACTIVE_WAIT_TIMEOUT_CYCLES },
[JM_DEFAULT_JS_FREE_TIMEOUT] = { "JM_DEFAULT_JS_FREE_TIMEOUT",
JM_DEFAULT_JS_FREE_TIMEOUT_CYCLES },
[KBASE_PRFCNT_ACTIVE_TIMEOUT] = { "KBASE_PRFCNT_ACTIVE_TIMEOUT",
KBASE_PRFCNT_ACTIVE_TIMEOUT_CYCLES },
[KBASE_CLEAN_CACHE_TIMEOUT] = { "KBASE_CLEAN_CACHE_TIMEOUT",
KBASE_CLEAN_CACHE_TIMEOUT_CYCLES },
[KBASE_AS_INACTIVE_TIMEOUT] = { "KBASE_AS_INACTIVE_TIMEOUT",
KBASE_AS_INACTIVE_TIMEOUT_CYCLES },
};
#endif
@ -282,10 +301,23 @@ static void get_cpu_gpu_time(struct kbase_device *kbdev, u64 *cpu_ts, u64 *gpu_t
kbase_backend_get_gpu_time(kbdev, gpu_cycle, gpu_ts, &ts);
if (cpu_ts)
*cpu_ts = ts.tv_sec * NSEC_PER_SEC + ts.tv_nsec;
*cpu_ts = (u64)(ts.tv_sec * NSEC_PER_SEC + ts.tv_nsec);
}
#endif
u64 kbase_arch_timer_get_cntfrq(struct kbase_device *kbdev)
{
u64 freq = arch_timer_get_cntfrq();
#if !IS_ENABLED(CONFIG_MALI_REAL_HW)
freq = midgard_model_arch_timer_get_cntfrq(kbdev->model);
#endif
dev_dbg(kbdev->dev, "System Timer Freq = %lluHz", freq);
return freq;
}
int kbase_backend_time_init(struct kbase_device *kbdev)
{
int err = 0;
@ -297,7 +329,7 @@ int kbase_backend_time_init(struct kbase_device *kbdev)
kbase_pm_register_access_enable(kbdev);
get_cpu_gpu_time(kbdev, &cpu_ts, &gpu_ts, NULL);
freq = arch_timer_get_cntfrq();
freq = kbase_arch_timer_get_cntfrq(kbdev);
if (!freq) {
dev_warn(kbdev->dev, "arch_timer_get_rate() is zero!");
@ -316,8 +348,9 @@ int kbase_backend_time_init(struct kbase_device *kbdev)
goto disable_registers;
}
kbdev->backend_time.offset = cpu_ts - div64_u64(gpu_ts * kbdev->backend_time.multiplier,
kbdev->backend_time.divisor);
kbdev->backend_time.offset =
(s64)(cpu_ts - div64_u64(gpu_ts * kbdev->backend_time.multiplier,
kbdev->backend_time.divisor));
#endif
if (kbase_timeout_scaling_init(kbdev)) {

2
drivers/gpu/arm/midgard/context/mali_kbase_context.c
View File

@ -188,7 +188,7 @@ int kbase_context_common_init(struct kbase_context *kctx)
bitmap_copy(kctx->cookies, &cookies_mask, BITS_PER_LONG);
kbase_gpu_vm_unlock(kctx);
kctx->id = atomic_add_return(1, &(kctx->kbdev->ctx_num)) - 1;
kctx->id = (u32)atomic_add_return(1, &(kctx->kbdev->ctx_num)) - 1;
mutex_lock(&kctx->kbdev->kctx_list_lock);
err = kbase_insert_kctx_to_process(kctx);

2
drivers/gpu/arm/midgard/context/mali_kbase_context.h
View File

@ -88,7 +88,7 @@ void kbase_destroy_context(struct kbase_context *kctx);
*/
static inline bool kbase_ctx_flag(struct kbase_context *kctx, enum kbase_context_flags flag)
{
return atomic_read(&kctx->flags) & flag;
return atomic_read(&kctx->flags) & (int)flag;
}
/**

19
drivers/gpu/arm/midgard/csf/ipa_control/mali_kbase_csf_ipa_control.c
View File

@ -45,11 +45,6 @@
*/
#define TIMER_EVENTS_PER_SECOND ((u32)1000 / IPA_CONTROL_TIMER_DEFAULT_VALUE_MS)
/*
* Maximum number of loops polling the GPU before we assume the GPU has hung.
*/
#define IPA_INACTIVE_MAX_LOOPS (8000000U)
/*
* Number of bits used to configure a performance counter in SELECT registers.
*/
@ -86,16 +81,16 @@ static u32 timer_value(u32 gpu_rate)
static int wait_status(struct kbase_device *kbdev, u32 flags)
{
unsigned int max_loops = IPA_INACTIVE_MAX_LOOPS;
u32 status = kbase_reg_read32(kbdev, IPA_CONTROL_ENUM(STATUS));
u32 val;
const u32 timeout_us = kbase_get_timeout_ms(kbdev, IPA_INACTIVE_TIMEOUT) * USEC_PER_MSEC;
/*
* Wait for the STATUS register to indicate that flags have been
* cleared, in case a transition is pending.
*/
while (--max_loops && (status & flags))
status = kbase_reg_read32(kbdev, IPA_CONTROL_ENUM(STATUS));
if (max_loops == 0) {
const int err = kbase_reg_poll32_timeout(kbdev, IPA_CONTROL_ENUM(STATUS), val,
!(val & flags), 0, timeout_us, false);
if (err) {
dev_err(kbdev->dev, "IPA_CONTROL STATUS register stuck");
return -EBUSY;
}
@ -126,7 +121,7 @@ static int apply_select_config(struct kbase_device *kbdev, u64 *select)
return ret;
}
static u64 read_value_cnt(struct kbase_device *kbdev, u8 type, int select_idx)
static u64 read_value_cnt(struct kbase_device *kbdev, u8 type, u8 select_idx)
{
switch (type) {
case KBASE_IPA_CORE_TYPE_CSHW:

55
drivers/gpu/arm/midgard/csf/mali_kbase_csf.c
View File

@ -191,14 +191,14 @@ static int kernel_map_user_io_pages(struct kbase_context *kctx, struct kbase_que
struct page *page_list[2];
pgprot_t cpu_map_prot;
unsigned long flags;
uint64_t *user_io_addr;
u64 *user_io_addr;
int ret = 0;
size_t i;
kbase_gpu_vm_lock(kctx);
if (ARRAY_SIZE(page_list) > (KBASE_PERMANENTLY_MAPPED_MEM_LIMIT_PAGES -
atomic_read(&kctx->permanent_mapped_pages))) {
(unsigned int)atomic_read(&kctx->permanent_mapped_pages))) {
ret = -ENOMEM;
goto unlock;
}
@ -548,7 +548,7 @@ static int csf_queue_register_internal(struct kbase_context *kctx,
* enabled, otherwise leave them as default zeros.
*/
if (reg_ex && reg_ex->ex_buffer_size) {
u32 cfg = CS_INSTR_CONFIG_EVENT_SIZE_SET(0, reg_ex->ex_event_size);
u32 cfg = CS_INSTR_CONFIG_EVENT_SIZE_SET(0U, reg_ex->ex_event_size);
cfg = CS_INSTR_CONFIG_EVENT_STATE_SET(cfg, reg_ex->ex_event_state);
queue->trace_cfg = cfg;
@ -719,7 +719,7 @@ int kbase_csf_queue_bind(struct kbase_context *kctx, union kbase_ioctl_cs_queue_
group->bound_queues[bind->in.csi_index] = queue;
queue->group = group;
queue->group_priority = group->priority;
queue->csi_index = bind->in.csi_index;
queue->csi_index = (s8)bind->in.csi_index;
queue->bind_state = KBASE_CSF_QUEUE_BIND_IN_PROGRESS;
out:
@ -835,8 +835,8 @@ void kbase_csf_ring_cs_kernel_doorbell(struct kbase_device *kbdev, int csi_index
dmb(osh);
value = kbase_csf_firmware_csg_output(ginfo, CSG_DB_ACK);
value ^= (1 << csi_index);
kbase_csf_firmware_csg_input_mask(ginfo, CSG_DB_REQ, value, 1 << csi_index);
value ^= (1U << csi_index);
kbase_csf_firmware_csg_input_mask(ginfo, CSG_DB_REQ, value, 1U << csi_index);
if (likely(ring_csg_doorbell))
kbase_csf_ring_csg_doorbell(kbdev, csg_nr);
@ -897,7 +897,7 @@ static void unbind_stopped_queue(struct kbase_context *kctx, struct kbase_queue
unsigned long flags;
kbase_csf_scheduler_spin_lock(kctx->kbdev, &flags);
bitmap_clear(queue->group->protm_pending_bitmap, queue->csi_index, 1);
bitmap_clear(queue->group->protm_pending_bitmap, (unsigned int)queue->csi_index, 1);
KBASE_KTRACE_ADD_CSF_GRP_Q(kctx->kbdev, CSI_PROTM_PEND_CLEAR, queue->group, queue,
queue->group->protm_pending_bitmap[0]);
queue->group->bound_queues[queue->csi_index] = NULL;
@ -1923,8 +1923,8 @@ static void flush_gpu_cache_on_fatal_error(struct kbase_device *kbdev)
*/
if (kbdev->pm.backend.gpu_powered) {
kbase_gpu_start_cache_clean(kbdev, GPU_COMMAND_CACHE_CLN_INV_L2_LSC);
if (kbase_gpu_wait_cache_clean_timeout(kbdev,
kbdev->mmu_or_gpu_cache_op_wait_time_ms))
if (kbase_gpu_wait_cache_clean_timeout(
kbdev, kbase_get_timeout_ms(kbdev, MMU_AS_INACTIVE_WAIT_TIMEOUT)))
dev_warn(
kbdev->dev,
"[%llu] Timeout waiting for CACHE_CLN_INV_L2_LSC to complete after fatal error",
@ -2258,12 +2258,13 @@ static void handle_fault_event(struct kbase_queue *const queue, const u32 cs_ack
const u32 cs_fault_exception_data = CS_FAULT_EXCEPTION_DATA_GET(cs_fault);
const u64 cs_fault_info_exception_data = CS_FAULT_INFO_EXCEPTION_DATA_GET(cs_fault_info);
bool use_old_log_format = true;
bool skip_fault_report = kbase_ctx_flag(queue->kctx, KCTX_PAGE_FAULT_REPORT_SKIP);
kbase_csf_scheduler_spin_lock_assert_held(kbdev);
if (use_old_log_format)
if (use_old_log_format && !skip_fault_report)
dev_warn(kbdev->dev,
"Ctx %d_%d Group %d CSG %d CSI: %d\n"
"CS_FAULT.EXCEPTION_TYPE: 0x%x (%s)\n"
@ -2324,7 +2325,7 @@ static void report_queue_fatal_error(struct kbase_queue *const queue, u32 cs_fat
return;
error.payload.csg_error.handle = group->handle;
error.payload.csg_error.error.payload.fatal_queue.csi_index = queue->csi_index;
error.payload.csg_error.error.payload.fatal_queue.csi_index = (__u8)queue->csi_index;
kbase_csf_event_add_error(queue->kctx, &group->error_fatal, &error);
kbase_event_wakeup(queue->kctx);
}
@ -2433,11 +2434,12 @@ static void handle_fatal_event(struct kbase_queue *const queue,
const u32 cs_fatal_exception_data = CS_FATAL_EXCEPTION_DATA_GET(cs_fatal);
const u64 cs_fatal_info_exception_data = CS_FATAL_INFO_EXCEPTION_DATA_GET(cs_fatal_info);
bool use_old_log_format = true;
bool skip_fault_report = kbase_ctx_flag(queue->kctx, KCTX_PAGE_FAULT_REPORT_SKIP);
kbase_csf_scheduler_spin_lock_assert_held(kbdev);
if (use_old_log_format)
if (use_old_log_format && !skip_fault_report)
dev_warn(kbdev->dev,
"Ctx %d_%d Group %d CSG %d CSI: %d\n"
"CS_FATAL.EXCEPTION_TYPE: 0x%x (%s)\n"
@ -2498,17 +2500,17 @@ static void process_cs_interrupts(struct kbase_queue_group *const group,
kbase_csf_scheduler_spin_lock_assert_held(kbdev);
while (remaining != 0) {
int const i = ffs(remaining) - 1;
unsigned int const i = (unsigned int)ffs((int)remaining) - 1;
struct kbase_queue *const queue = group->bound_queues[i];
remaining &= ~(1 << i);
remaining &= ~(1U << i);
/* The queue pointer can be NULL, but if it isn't NULL then it
* cannot disappear since scheduler spinlock is held and before
* freeing a bound queue it has to be first unbound which
* requires scheduler spinlock.
*/
if (queue && !WARN_ON(queue->csi_index != i)) {
if (queue && !WARN_ON(queue->csi_index != (s8)i)) {
struct kbase_csf_cmd_stream_info const *const stream = &ginfo->streams[i];
u32 const cs_req = kbase_csf_firmware_cs_input_read(stream, CS_REQ);
u32 const cs_ack = kbase_csf_firmware_cs_output(stream, CS_ACK);
@ -2612,7 +2614,7 @@ static void process_cs_interrupts(struct kbase_queue_group *const group,
*
* See process_cs_interrupts() for details of per-stream interrupt handling.
*/
static void process_csg_interrupts(struct kbase_device *const kbdev, int const csg_nr,
static void process_csg_interrupts(struct kbase_device *const kbdev, u32 const csg_nr,
struct irq_idle_and_protm_track *track)
{
struct kbase_csf_cmd_stream_group_info *ginfo;
@ -2621,7 +2623,7 @@ static void process_csg_interrupts(struct kbase_device *const kbdev, int const c
kbase_csf_scheduler_spin_lock_assert_held(kbdev);
if (WARN_ON((u32)csg_nr >= kbdev->csf.global_iface.group_num))
if (WARN_ON(csg_nr >= kbdev->csf.global_iface.group_num))
return;
ginfo = &kbdev->csf.global_iface.groups[csg_nr];
@ -2655,10 +2657,10 @@ static void process_csg_interrupts(struct kbase_device *const kbdev, int const c
if (!group)
return;
if (WARN_ON(kbase_csf_scheduler_group_get_slot_locked(group) != csg_nr))
if (WARN_ON((u32)kbase_csf_scheduler_group_get_slot_locked(group) != csg_nr))
return;
KBASE_KTRACE_ADD_CSF_GRP(kbdev, CSG_INTERRUPT_PROCESS_START, group, csg_nr);
KBASE_KTRACE_ADD_CSF_GRP(kbdev, CSG_INTERRUPT_PROCESS_START, group, (u64)csg_nr);
kbase_csf_handle_csg_sync_update(kbdev, ginfo, group, req, ack);
@ -2673,7 +2675,7 @@ static void process_csg_interrupts(struct kbase_device *const kbdev, int const c
KBASE_KTRACE_ADD_CSF_GRP(kbdev, CSG_SLOT_IDLE_SET, group,
scheduler->csg_slots_idle_mask[0]);
KBASE_KTRACE_ADD_CSF_GRP(kbdev, CSG_INTERRUPT_IDLE, group, req ^ ack);
dev_dbg(kbdev->dev, "Idle notification received for Group %u on slot %d\n",
dev_dbg(kbdev->dev, "Idle notification received for Group %u on slot %u\n",
group->handle, csg_nr);
if (atomic_read(&scheduler->non_idle_offslot_grps)) {
@ -2690,7 +2692,7 @@ static void process_csg_interrupts(struct kbase_device *const kbdev, int const c
if (group->scan_seq_num < track->idle_seq) {
track->idle_seq = group->scan_seq_num;
track->idle_slot = csg_nr;
track->idle_slot = (s8)csg_nr;
}
}
@ -2702,7 +2704,7 @@ static void process_csg_interrupts(struct kbase_device *const kbdev, int const c
req ^ ack);
dev_info(
kbdev->dev,
"[%llu] Iterator PROGRESS_TIMER timeout notification received for group %u of ctx %d_%d on slot %d\n",
"[%llu] Iterator PROGRESS_TIMER timeout notification received for group %u of ctx %d_%d on slot %u\n",
kbase_backend_get_cycle_cnt(kbdev), group->handle, group->kctx->tgid,
group->kctx->id, csg_nr);
@ -2964,10 +2966,10 @@ void kbase_csf_interrupt(struct kbase_device *kbdev, u32 val)
kbase_csf_scheduler_spin_lock(kbdev, &flags);
/* Looping through and track the highest idle and protm groups */
while (csg_interrupts != 0) {
int const csg_nr = ffs(csg_interrupts) - 1;
u32 const csg_nr = (u32)ffs((int)csg_interrupts) - 1;
process_csg_interrupts(kbdev, csg_nr, &track);
csg_interrupts &= ~(1 << csg_nr);
csg_interrupts &= ~(1U << csg_nr);
}
/* Handle protm from the tracked information */
@ -3038,10 +3040,13 @@ void kbase_csf_interrupt(struct kbase_device *kbdev, u32 val)
if (deferred_handling_glb_idle_irq) {
unsigned long flags;
bool invoke_pm_state_machine;
kbase_csf_scheduler_spin_lock(kbdev, &flags);
kbase_csf_scheduler_process_gpu_idle_event(kbdev);
invoke_pm_state_machine = kbase_csf_scheduler_process_gpu_idle_event(kbdev);
kbase_csf_scheduler_spin_unlock(kbdev, flags);
if (unlikely(invoke_pm_state_machine))
kbase_pm_update_state(kbdev);
}
wake_up_all(&kbdev->csf.event_wait);

5
drivers/gpu/arm/midgard/csf/mali_kbase_csf_csg_debugfs.c
View File

@ -236,7 +236,6 @@ static ssize_t kbase_csf_debugfs_scheduler_state_set(struct file *file, const ch
{
struct kbase_device *kbdev = file->private_data;
char buf[MAX_SCHED_STATE_STRING_LEN];
ssize_t ret = count;
CSTD_UNUSED(ppos);
@ -256,10 +255,10 @@ static ssize_t kbase_csf_debugfs_scheduler_state_set(struct file *file, const ch
kbase_csf_scheduler_force_wakeup(kbdev);
else {
dev_dbg(kbdev->dev, "Bad scheduler state %s", buf);
ret = -EINVAL;
return -EINVAL;
}
return ret;
return (ssize_t)count;
}
static const struct file_operations kbasep_csf_debugfs_scheduler_state_fops = {

102
drivers/gpu/arm/midgard/csf/mali_kbase_csf_defs.h
View File

@ -26,15 +26,16 @@
#ifndef _KBASE_CSF_DEFS_H_
#define _KBASE_CSF_DEFS_H_
#include <linux/types.h>
#include <linux/wait.h>
#include <hw_access/mali_kbase_hw_access.h>
#include "mali_kbase_csf_firmware.h"
#include "mali_kbase_refcount_defs.h"
#include "mali_kbase_csf_event.h"
#include <uapi/gpu/arm/midgard/csf/mali_kbase_csf_errors_dumpfault.h>
#include <linux/version_compat_defs.h>
#include <linux/types.h>
#include <linux/wait.h>
#if IS_ENABLED(CONFIG_MALI_CORESIGHT)
#include <debug/backend/mali_kbase_debug_coresight_internal_csf.h>
#endif /* IS_ENABLED(CONFIG_MALI_CORESIGHT) */
@ -245,11 +246,11 @@ enum kbase_csf_scheduler_state {
/**
* enum kbase_queue_group_priority - Kbase internal relative priority list.
*
* @KBASE_QUEUE_GROUP_PRIORITY_REALTIME: The realtime queue group priority.
* @KBASE_QUEUE_GROUP_PRIORITY_HIGH: The high queue group priority.
* @KBASE_QUEUE_GROUP_PRIORITY_MEDIUM: The medium queue group priority.
* @KBASE_QUEUE_GROUP_PRIORITY_LOW: The low queue group priority.
* @KBASE_QUEUE_GROUP_PRIORITY_COUNT: The number of priority levels.
* @KBASE_QUEUE_GROUP_PRIORITY_REALTIME: The realtime queue group priority.
* @KBASE_QUEUE_GROUP_PRIORITY_HIGH: The high queue group priority.
* @KBASE_QUEUE_GROUP_PRIORITY_MEDIUM: The medium queue group priority.
* @KBASE_QUEUE_GROUP_PRIORITY_LOW: The low queue group priority.
* @KBASE_QUEUE_GROUP_PRIORITY_COUNT: The number of priority levels.
*/
enum kbase_queue_group_priority {
KBASE_QUEUE_GROUP_PRIORITY_REALTIME = 0,
@ -273,7 +274,12 @@ enum kbase_queue_group_priority {
* @CSF_SCHED_PROTM_PROGRESS_TIMEOUT: Timeout used to prevent protected mode execution hang.
* @MMU_AS_INACTIVE_WAIT_TIMEOUT: Maximum waiting time in ms for the completion
* of a MMU operation.
* @KCPU_FENCE_SIGNAL_TIMEOUT: Waiting time in ms for triggering a KCPU queue sync state dump
* @KCPU_FENCE_SIGNAL_TIMEOUT: Waiting time in ms for triggering a KCPU queue sync state dump.
* @KBASE_PRFCNT_ACTIVE_TIMEOUT: Waiting time for prfcnt to be ready.
* @KBASE_CLEAN_CACHE_TIMEOUT: Waiting time for cache flush to complete.
* @KBASE_AS_INACTIVE_TIMEOUT: Waiting time for MCU address space to become inactive.
* @IPA_INACTIVE_TIMEOUT: Waiting time for IPA_CONTROL_STATUS flags to be cleared.
* @CSF_FIRMWARE_STOP_TIMEOUT: Waiting time for the firmware to stop.
* @KBASE_TIMEOUT_SELECTOR_COUNT: Number of timeout selectors. Must be last in
* the enum.
* @KBASE_DEFAULT_TIMEOUT: Default timeout used when an invalid selector is passed
@ -289,6 +295,11 @@ enum kbase_timeout_selector {
CSF_SCHED_PROTM_PROGRESS_TIMEOUT,
MMU_AS_INACTIVE_WAIT_TIMEOUT,
KCPU_FENCE_SIGNAL_TIMEOUT,
KBASE_PRFCNT_ACTIVE_TIMEOUT,
KBASE_CLEAN_CACHE_TIMEOUT,
KBASE_AS_INACTIVE_TIMEOUT,
IPA_INACTIVE_TIMEOUT,
CSF_FIRMWARE_STOP_TIMEOUT,
/* Must be the last in the enum */
KBASE_TIMEOUT_SELECTOR_COUNT,
@ -505,9 +516,9 @@ struct kbase_protected_suspend_buffer {
* @prepared_seq_num: Indicates the position of queue group in the list of
* prepared groups to be scheduled.
* @scan_seq_num: Scan out sequence number before adjusting for dynamic
* idle conditions. It is used for setting a group's
* onslot priority. It could differ from prepared_seq_number
* when there are idle groups.
* idle conditions. It represents a group's global priority
* for a running tick/tock. It could differ from
* prepared_seq_number when there are idle groups.
* @faulted: Indicates that a GPU fault occurred for the queue group.
* This flag persists until the fault has been queued to be
* reported to userspace.
@ -538,6 +549,12 @@ struct kbase_protected_suspend_buffer {
* It is accumulated on consecutive mapping attempt failures. On
* reaching a preset limit, the group is regarded as suffered
* a fatal error and triggers a fatal error notification.
* @sched_act_seq_num: Scheduling action sequence number to determine the CSG slot
* priority in tick/tock scheduling action. It could differ from
* scan_seq_num. The field is only meaningful if the CSG is on the
* Scheduler's schedulable list for a tick/tock, and used for
* determining the CSG slot priority when the group is to be placed
* on the CSG slot.
*/
struct kbase_queue_group {
struct kbase_context *kctx;
@ -589,6 +606,7 @@ struct kbase_queue_group {
#endif
void *csg_reg;
u8 csg_reg_bind_retries;
u32 sched_act_seq_num;
#if IS_ENABLED(CONFIG_MALI_TRACE_POWER_GPU_WORK_PERIOD)
/**
* @prev_act: Previous CSG activity transition in a GPU metrics.
@ -729,13 +747,15 @@ struct kbase_csf_ctx_heap_reclaim_info {
* GPU command queues are idle and at least one of them
* is blocked on a sync wait operation.
* @num_idle_wait_grps: Length of the @idle_wait_groups list.
* @sync_update_wq: Dedicated workqueue to process work items corresponding
* to the sync_update events by sync_set/sync_add
* instruction execution on CSs bound to groups
* of @idle_wait_groups list.
* @sync_update_work: work item to process the sync_update events by
* sync_set / sync_add instruction execution on command
* streams bound to groups of @idle_wait_groups list.
* @sync_update_wq_high_prio: high-priority work queue to process the
* SYNC_UPDATE events by sync_set / sync_add
* instruction execution on command streams bound to
* groups of @idle_wait_groups list. This WQ would
* be used if the context is prioritised.
* @sync_update_wq_normal_prio: similar to sync_update_wq_high_prio, but this
* WQ would be used if the context is not
* prioritised.
* @sync_update_work: Work item to process the SYNC_UPDATE events.
* @ngrp_to_schedule: Number of groups added for the context to the
* 'groups_to_schedule' list of scheduler instance.
* @heap_info: Heap reclaim information data of the kctx. As the
@ -748,7 +768,8 @@ struct kbase_csf_scheduler_context {
u32 num_runnable_grps;
struct list_head idle_wait_groups;
u32 num_idle_wait_grps;
struct workqueue_struct *sync_update_wq;
struct workqueue_struct *sync_update_wq_high_prio;
struct workqueue_struct *sync_update_wq_normal_prio;
struct work_struct sync_update_work;
u32 ngrp_to_schedule;
struct kbase_csf_ctx_heap_reclaim_info heap_info;
@ -844,6 +865,11 @@ struct kbase_csf_user_reg_context {
* @wq: Dedicated workqueue to process work items corresponding
* to the OoM events raised for chunked tiler heaps being
* used by GPU command queues, and progress timeout events.
* @kcpu_wq_high_prio: High-priority work queue to process KCPU commands for
* all queues in this context. This WQ would be used if
* the context is prioritised.
* @kcpu_wq_normal_prio: Similar to kcpu_wq_high_prio, but this WQ would be
* used if the context is not prioritised.
* @link: Link to this csf context in the 'runnable_kctxs' list of
* the scheduler instance
* @sched: Object representing the scheduler's context
@ -862,6 +888,8 @@ struct kbase_csf_context {
struct kbase_csf_event event;
struct kbase_csf_tiler_heap_context tiler_heaps;
struct workqueue_struct *wq;
struct workqueue_struct *kcpu_wq_high_prio;
struct workqueue_struct *kcpu_wq_normal_prio;
struct list_head link;
struct kbase_csf_scheduler_context sched;
struct kbase_csf_cpu_queue_context cpu_queue;
@ -1069,6 +1097,9 @@ struct kbase_csf_mcu_shared_regions {
* protected mode execution compared to other such
* groups. It is updated on every tick/tock.
* @interrupt_lock is used to serialize the access.
* @csg_scan_sched_count: Scheduling action counter used to assign the sched_act_seq_num
* for each group added to Scheduler's schedulable list in a
* tick/tock.
* @protm_enter_time: GPU protected mode enter time.
* @reclaim_mgr: CSGs tiler heap manager object.
* @mcu_regs_data: Scheduler MCU shared regions data for managing the
@ -1118,6 +1149,7 @@ struct kbase_csf_scheduler {
u32 pm_active_count;
unsigned int csg_scheduling_period_ms;
u32 tick_protm_pending_seq;
u32 csg_scan_sched_count;
ktime_t protm_enter_time;
struct kbase_csf_sched_heap_reclaim_mgr reclaim_mgr;
struct kbase_csf_mcu_shared_regions mcu_regs_data;
@ -1201,6 +1233,8 @@ enum kbase_ipa_core_type {
KBASE_IPA_CORE_TYPE_MEMSYS,
KBASE_IPA_CORE_TYPE_TILER,
KBASE_IPA_CORE_TYPE_SHADER,
/* Must be the last in the enum */
KBASE_IPA_CORE_TYPE_NUM
};
@ -1328,7 +1362,7 @@ struct kbase_ipa_control {
* @num_pages: Number of entries in @phys and @pma (and length of the interface)
* @num_pages_aligned: Same as @num_pages except for the case when @is_small_page
* is false and @reuse_pages is false and therefore will be
* aligned to NUM_4K_PAGES_IN_2MB_PAGE.
* aligned to NUM_PAGES_IN_2MB_LARGE_PAGE.
* @virtual: Starting GPU virtual address this interface is mapped at
* @flags: bitmask of CSF_FIRMWARE_ENTRY_* conveying the interface attributes
* @data_start: Offset into firmware image at which the interface data starts
@ -1593,9 +1627,9 @@ struct kbase_csf_user_reg {
* @mcu_core_pwroff_dur_count: The counterpart of the glb_pwroff timeout input
* in interface required format, ready to be used
* directly in the firmware.
* @mcu_core_pwroff_dur_count_modifier: Update csffw_glb_req_cfg_pwroff_timer
* to make the shr(10) modifier conditional
* on new flag in GLB_PWROFF_TIMER_CONFIG
* @mcu_core_pwroff_dur_count_no_modifier: Update csffw_glb_req_cfg_pwroff_timer
* to make the shr(10) modifier conditional
* on new flag in GLB_PWROFF_TIMER_CONFIG
* @mcu_core_pwroff_reg_shadow: The actual value that has been programed into
* the glb_pwoff register. This is separated from
* the @p mcu_core_pwroff_dur_count as an update
@ -1606,10 +1640,9 @@ struct kbase_csf_user_reg {
* @gpu_idle_dur_count: The counterpart of the hysteresis time window in
* interface required format, ready to be used
* directly in the firmware.
* @gpu_idle_dur_count_modifier: Update csffw_glb_req_idle_enable to make the shr(10)
* modifier conditional on the new flag
* in GLB_IDLE_TIMER_CONFIG.
* @fw_timeout_ms: Timeout value (in milliseconds) used when waiting
* @gpu_idle_dur_count_no_modifier: Update csffw_glb_req_idle_enable to make the shr(10)
* modifier conditional on the new flag
* in GLB_IDLE_TIMER_CONFIG.
* for any request sent to the firmware.
* @hwcnt: Contain members required for handling the dump of
* HW counters.
@ -1656,14 +1689,13 @@ struct kbase_csf_device {
bool glb_init_request_pending;
struct work_struct fw_error_work;
struct kbase_ipa_control ipa_control;
u32 mcu_core_pwroff_dur_ns;
u64 mcu_core_pwroff_dur_ns;
u32 mcu_core_pwroff_dur_count;
u32 mcu_core_pwroff_dur_count_modifier;
u32 mcu_core_pwroff_dur_count_no_modifier;
u32 mcu_core_pwroff_reg_shadow;
u32 gpu_idle_hysteresis_ns;
u64 gpu_idle_hysteresis_ns;
u32 gpu_idle_dur_count;
u32 gpu_idle_dur_count_modifier;
unsigned int fw_timeout_ms;
u32 gpu_idle_dur_count_no_modifier;
struct kbase_csf_hwcnt hwcnt;
struct kbase_csf_mcu_fw fw;
struct kbase_csf_firmware_log fw_log;
@ -1699,7 +1731,7 @@ struct kbase_csf_device {
* @current_setup: Stores the MMU configuration for this address space.
*/
struct kbase_as {
int number;
unsigned int number;
struct workqueue_struct *pf_wq;
struct work_struct work_pagefault;
struct work_struct work_busfault;

230
drivers/gpu/arm/midgard/csf/mali_kbase_csf_firmware.c
View File

@ -66,6 +66,7 @@ static unsigned int csf_firmware_boot_timeout_ms;
module_param(csf_firmware_boot_timeout_ms, uint, 0444);
MODULE_PARM_DESC(csf_firmware_boot_timeout_ms, "Maximum time to wait for firmware to boot.");
#ifdef CONFIG_MALI_DEBUG
/* Makes Driver wait indefinitely for an acknowledgment for the different
* requests it sends to firmware. Otherwise the timeouts interfere with the
@ -110,8 +111,6 @@ MODULE_PARM_DESC(fw_debug, "Enables effective use of a debugger for debugging fi
#define BUILD_INFO_GIT_DIRTY_LEN (1U)
#define BUILD_INFO_GIT_SHA_PATTERN "git_sha: "
#define CSF_MAX_FW_STOP_LOOPS (100000)
#define CSF_GLB_REQ_CFG_MASK \
(GLB_REQ_CFG_ALLOC_EN_MASK | GLB_REQ_CFG_PROGRESS_TIMER_MASK | \
GLB_REQ_CFG_PWROFF_TIMER_MASK | GLB_REQ_IDLE_ENABLE_MASK)
@ -208,17 +207,6 @@ static int setup_shared_iface_static_region(struct kbase_device *kbdev)
return ret;
}
static int wait_mcu_status_value(struct kbase_device *kbdev, u32 val)
{
u32 max_loops = CSF_MAX_FW_STOP_LOOPS;
/* wait for the MCU_STATUS register to reach the given status value */
while (--max_loops && (kbase_reg_read32(kbdev, GPU_CONTROL_ENUM(MCU_STATUS)) != val))
;
return (max_loops == 0) ? -1 : 0;
}
void kbase_csf_firmware_disable_mcu(struct kbase_device *kbdev)
{
@ -229,10 +217,15 @@ void kbase_csf_firmware_disable_mcu(struct kbase_device *kbdev)
static void wait_for_firmware_stop(struct kbase_device *kbdev)
{
if (wait_mcu_status_value(kbdev, MCU_CONTROL_REQ_DISABLE) < 0) {
/* This error shall go away once MIDJM-2371 is closed */
dev_err(kbdev->dev, "Firmware failed to stop");
}
u32 val;
const u32 timeout_us =
kbase_get_timeout_ms(kbdev, CSF_FIRMWARE_STOP_TIMEOUT) * USEC_PER_MSEC;
const int err = kbase_reg_poll32_timeout(kbdev, GPU_CONTROL_ENUM(MCU_STATUS), val,
val == MCU_CONTROL_REQ_DISABLE, 0, timeout_us,
false);
if (err)
dev_err(kbdev->dev, "Firmware failed to stop, error no: %d", err);
KBASE_TLSTREAM_TL_KBASE_CSFFW_FW_OFF(kbdev, kbase_backend_get_cycle_cnt(kbdev));
}
@ -302,22 +295,15 @@ static void boot_csf_firmware(struct kbase_device *kbdev)
*/
static int wait_ready(struct kbase_device *kbdev)
{
const ktime_t wait_loop_start = ktime_get_raw();
const u32 mmu_as_inactive_wait_time_ms = kbdev->mmu_or_gpu_cache_op_wait_time_ms;
s64 diff;
u32 val;
const u32 timeout_us =
kbase_get_timeout_ms(kbdev, MMU_AS_INACTIVE_WAIT_TIMEOUT) * USEC_PER_MSEC;
const int err = kbase_reg_poll32_timeout(kbdev, MMU_AS_OFFSET(MCU_AS_NR, STATUS), val,
!(val & AS_STATUS_AS_ACTIVE_EXT_MASK), 0,
timeout_us, false);
do {
unsigned int i;
for (i = 0; i < 1000; i++) {
/* Wait for the MMU status to indicate there is no active command */
if (!(kbase_reg_read32(kbdev, MMU_AS_OFFSET(MCU_AS_NR, STATUS)) &
AS_STATUS_AS_ACTIVE_EXT_MASK))
return 0;
}
diff = ktime_to_ms(ktime_sub(ktime_get_raw(), wait_loop_start));
} while (diff < mmu_as_inactive_wait_time_ms);
if (!err)
return 0;
dev_err(kbdev->dev,
"AS_ACTIVE bit stuck for MCU AS. Might be caused by unstable GPU clk/pwr or faulty system");
@ -520,11 +506,11 @@ out:
* parsed FW interface entry using large page(s) from protected memory.
* If no appropriate entry is found it is set to NULL.
* @num_pages: Number of pages requested.
* @num_pages_aligned: This is an output parameter used to carry the number of 4KB pages
* @num_pages_aligned: This is an output parameter used to carry the number of small pages
* within the 2MB pages aligned allocation.
* @is_small_page: This is an output flag used to select between the small and large page
* to be used for the FW entry allocation.
* @force_small_page: Use 4kB pages to allocate memory needed for FW loading
* @force_small_page: Use small pages to allocate memory needed for FW loading
*
* Go through all the already initialized interfaces and find if a previously
* allocated large page can be used to store contents of new FW interface entry.
@ -559,16 +545,16 @@ static inline bool entry_find_large_page_to_reuse(struct kbase_device *kbdev,
* then use 2MB page(s) for it.
*/
if (!(virtual_start & (SZ_2M - 1))) {
*num_pages_aligned = round_up(*num_pages_aligned, NUM_4K_PAGES_IN_2MB_PAGE);
*num_pages_aligned = round_up(*num_pages_aligned, NUM_PAGES_IN_2MB_LARGE_PAGE);
*is_small_page = false;
goto out;
}
/* If the section doesn't lie within the same 2MB aligned boundary,
* then use 4KB pages as it would be complicated to use a 2MB page
* then use small pages as it would be complicated to use a 2MB page
* for such section.
*/
if ((virtual_start & ~(SZ_2M - 1)) != (virtual_end & ~(SZ_2M - 1)))
if ((virtual_start & ~(SZ_2M - 1UL)) != (virtual_end & ~(SZ_2M - 1UL)))
goto out;
/* Find the nearest 2MB aligned section which comes before the current
@ -599,7 +585,7 @@ static inline bool entry_find_large_page_to_reuse(struct kbase_device *kbdev,
*phys = &target_interface->phys[page_index];
if (target_interface->pma)
*pma = &target_interface->pma[page_index / NUM_4K_PAGES_IN_2MB_PAGE];
*pma = &target_interface->pma[page_index / NUM_PAGES_IN_2MB_LARGE_PAGE];
*is_small_page = false;
reuse_large_page = true;
@ -1520,7 +1506,7 @@ static void handle_internal_firmware_fatal(struct kbase_device *const kbdev)
* active address space and retain its refcount.
*/
spin_lock_irqsave(&kbdev->hwaccess_lock, flags);
kctx = kbase_ctx_sched_as_to_ctx_nolock(kbdev, as);
kctx = kbase_ctx_sched_as_to_ctx_nolock(kbdev, (size_t)as);
if (kctx) {
kbase_ctx_sched_retain_ctx_refcount(kctx);
@ -1597,7 +1583,8 @@ static int wait_for_global_request_with_timeout(struct kbase_device *const kbdev
static int wait_for_global_request(struct kbase_device *const kbdev, u32 const req_mask)
{
return wait_for_global_request_with_timeout(kbdev, req_mask, kbdev->csf.fw_timeout_ms);
return wait_for_global_request_with_timeout(
kbdev, req_mask, kbase_get_timeout_ms(kbdev, CSF_FIRMWARE_TIMEOUT));
}
static void set_global_request(const struct kbase_csf_global_iface *const global_iface,
@ -1635,7 +1622,7 @@ static void set_shader_poweroff_timer(struct kbase_device *const kbdev,
kbase_csf_firmware_global_input(global_iface, GLB_PWROFF_TIMER, pwroff_reg);
kbase_csf_firmware_global_input_mask(global_iface, GLB_PWROFF_TIMER_CONFIG,
kbdev->csf.mcu_core_pwroff_dur_count_modifier,
kbdev->csf.mcu_core_pwroff_dur_count_no_modifier,
GLB_PWROFF_TIMER_CONFIG_NO_MODIFIER_MASK);
set_global_request(global_iface, GLB_REQ_CFG_PWROFF_TIMER_MASK);
@ -1665,7 +1652,7 @@ static void enable_gpu_idle_timer(struct kbase_device *const kbdev)
kbdev->csf.gpu_idle_dur_count);
kbase_csf_firmware_global_input_mask(global_iface, GLB_IDLE_TIMER_CONFIG,
kbdev->csf.gpu_idle_dur_count_modifier,
kbdev->csf.gpu_idle_dur_count_no_modifier,
GLB_IDLE_TIMER_CONFIG_NO_MODIFIER_MASK);
kbase_csf_firmware_global_input_mask(global_iface, GLB_REQ, GLB_REQ_REQ_IDLE_ENABLE,
@ -1961,11 +1948,11 @@ void kbase_csf_firmware_reload_completed(struct kbase_device *kbdev)
kbase_pm_update_state(kbdev);
}
static u32 convert_dur_to_idle_count(struct kbase_device *kbdev, const u32 dur_ns, u32 *modifier)
static u32 convert_dur_to_idle_count(struct kbase_device *kbdev, const u64 dur_ns, u32 *no_modifier)
{
#define HYSTERESIS_VAL_UNIT_SHIFT (10)
/* Get the cntfreq_el0 value, which drives the SYSTEM_TIMESTAMP */
u64 freq = arch_timer_get_cntfrq();
u64 freq = kbase_arch_timer_get_cntfrq(kbdev);
u64 dur_val = dur_ns;
u32 cnt_val_u32, reg_val_u32;
bool src_system_timestamp = freq > 0;
@ -1988,10 +1975,10 @@ static u32 convert_dur_to_idle_count(struct kbase_device *kbdev, const u32 dur_n
dur_val = dur_val * freq;
dur_val = div_u64(dur_val, NSEC_PER_SEC);
if (dur_val < S32_MAX) {
*modifier = 1;
*no_modifier = 1;
} else {
dur_val = dur_val >> HYSTERESIS_VAL_UNIT_SHIFT;
*modifier = 0;
*no_modifier = 0;
}
/* Interface limits the value field to S32_MAX */
@ -2006,24 +1993,24 @@ static u32 convert_dur_to_idle_count(struct kbase_device *kbdev, const u32 dur_n
return reg_val_u32;
}
u32 kbase_csf_firmware_get_gpu_idle_hysteresis_time(struct kbase_device *kbdev)
u64 kbase_csf_firmware_get_gpu_idle_hysteresis_time(struct kbase_device *kbdev)
{
unsigned long flags;
u32 dur;
u64 dur_ns;
kbase_csf_scheduler_spin_lock(kbdev, &flags);
dur = kbdev->csf.gpu_idle_hysteresis_ns;
dur_ns = kbdev->csf.gpu_idle_hysteresis_ns;
kbase_csf_scheduler_spin_unlock(kbdev, flags);
return dur;
return dur_ns;
}
u32 kbase_csf_firmware_set_gpu_idle_hysteresis_time(struct kbase_device *kbdev, u32 dur_ns)
u32 kbase_csf_firmware_set_gpu_idle_hysteresis_time(struct kbase_device *kbdev, u64 dur_ns)
{
unsigned long flags;
u32 modifier = 0;
u32 no_modifier = 0;
const u32 hysteresis_val = convert_dur_to_idle_count(kbdev, dur_ns, &modifier);
const u32 hysteresis_val = convert_dur_to_idle_count(kbdev, dur_ns, &no_modifier);
/* The 'fw_load_lock' is taken to synchronize against the deferred
* loading of FW, where the idle timer will be enabled.
@ -2033,7 +2020,7 @@ u32 kbase_csf_firmware_set_gpu_idle_hysteresis_time(struct kbase_device *kbdev,
kbase_csf_scheduler_spin_lock(kbdev, &flags);
kbdev->csf.gpu_idle_hysteresis_ns = dur_ns;
kbdev->csf.gpu_idle_dur_count = hysteresis_val;
kbdev->csf.gpu_idle_dur_count_modifier = modifier;
kbdev->csf.gpu_idle_dur_count_no_modifier = no_modifier;
kbase_csf_scheduler_spin_unlock(kbdev, flags);
mutex_unlock(&kbdev->fw_load_lock);
goto end;
@ -2073,7 +2060,7 @@ u32 kbase_csf_firmware_set_gpu_idle_hysteresis_time(struct kbase_device *kbdev,
kbase_csf_scheduler_spin_lock(kbdev, &flags);
kbdev->csf.gpu_idle_hysteresis_ns = dur_ns;
kbdev->csf.gpu_idle_dur_count = hysteresis_val;
kbdev->csf.gpu_idle_dur_count_modifier = modifier;
kbdev->csf.gpu_idle_dur_count_no_modifier = no_modifier;
kbase_csf_firmware_enable_gpu_idle_timer(kbdev);
kbase_csf_scheduler_spin_unlock(kbdev, flags);
wait_for_global_request(kbdev, GLB_REQ_IDLE_ENABLE_MASK);
@ -2086,12 +2073,13 @@ end:
return hysteresis_val;
}
KBASE_EXPORT_TEST_API(kbase_csf_firmware_set_gpu_idle_hysteresis_time);
static u32 convert_dur_to_core_pwroff_count(struct kbase_device *kbdev, const u32 dur_ns,
u32 *modifier)
static u32 convert_dur_to_core_pwroff_count(struct kbase_device *kbdev, const u64 dur_ns,
u32 *no_modifier)
{
/* Get the cntfreq_el0 value, which drives the SYSTEM_TIMESTAMP */
u64 freq = arch_timer_get_cntfrq();
u64 freq = kbase_arch_timer_get_cntfrq(kbdev);
u64 dur_val = dur_ns;
u32 cnt_val_u32, reg_val_u32;
bool src_system_timestamp = freq > 0;
@ -2117,10 +2105,10 @@ static u32 convert_dur_to_core_pwroff_count(struct kbase_device *kbdev, const u3
dur_val = dur_val * freq;
dur_val = div_u64(dur_val, NSEC_PER_SEC);
if (dur_val < S32_MAX) {
*modifier = 1;
*no_modifier = 1;
} else {
dur_val = dur_val >> HYSTERESIS_VAL_UNIT_SHIFT;
*modifier = 0;
*no_modifier = 0;
}
if (dur_val == 0 && !always_on) {
@ -2143,29 +2131,29 @@ static u32 convert_dur_to_core_pwroff_count(struct kbase_device *kbdev, const u3
return reg_val_u32;
}
u32 kbase_csf_firmware_get_mcu_core_pwroff_time(struct kbase_device *kbdev)
u64 kbase_csf_firmware_get_mcu_core_pwroff_time(struct kbase_device *kbdev)
{
u32 pwroff;
u64 pwroff_ns;
unsigned long flags;
spin_lock_irqsave(&kbdev->hwaccess_lock, flags);
pwroff = kbdev->csf.mcu_core_pwroff_dur_ns;
pwroff_ns = kbdev->csf.mcu_core_pwroff_dur_ns;
spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags);
return pwroff;
return pwroff_ns;
}
u32 kbase_csf_firmware_set_mcu_core_pwroff_time(struct kbase_device *kbdev, u32 dur_ns)
u32 kbase_csf_firmware_set_mcu_core_pwroff_time(struct kbase_device *kbdev, u64 dur_ns)
{
unsigned long flags;
u32 modifier = 0;
u32 no_modifier = 0;
const u32 pwroff = convert_dur_to_core_pwroff_count(kbdev, dur_ns, &modifier);
const u32 pwroff = convert_dur_to_core_pwroff_count(kbdev, dur_ns, &no_modifier);
spin_lock_irqsave(&kbdev->hwaccess_lock, flags);
kbdev->csf.mcu_core_pwroff_dur_ns = dur_ns;
kbdev->csf.mcu_core_pwroff_dur_count = pwroff;
kbdev->csf.mcu_core_pwroff_dur_count_modifier = modifier;
kbdev->csf.mcu_core_pwroff_dur_count_no_modifier = no_modifier;
spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags);
dev_dbg(kbdev->dev, "MCU shader Core Poweroff input update: 0x%.8x", pwroff);
@ -2178,6 +2166,34 @@ u32 kbase_csf_firmware_reset_mcu_core_pwroff_time(struct kbase_device *kbdev)
return kbase_csf_firmware_set_mcu_core_pwroff_time(kbdev, DEFAULT_GLB_PWROFF_TIMEOUT_NS);
}
/**
* kbase_csf_get_iterator_trace_enable - Parsing the iterator_trace enable firstly from
* the module parameter, and then from device-tree.
* @kbdev: Kernel base device pointer
*
* Return: true on enabled, otherwise false.
*/
static bool kbase_csf_get_iterator_trace_enable(struct kbase_device *kbdev)
{
const void *dt_iter_trace_param;
unsigned int val;
/* check device tree for iterator trace enable property and
* fallback to "iter_trace_enable" if not found and try again
*/
dt_iter_trace_param = of_get_property(kbdev->dev->of_node, "iter-trace-enable", NULL);
if (!dt_iter_trace_param)
dt_iter_trace_param =
of_get_property(kbdev->dev->of_node, "iter_trace_enable", NULL);
val = (dt_iter_trace_param) ? be32_to_cpup(dt_iter_trace_param) : 0;
dev_dbg(kbdev->dev, "Iterator trace enable device-tree config value: %u", val);
return (val != 0);
}
/**
* kbase_device_csf_iterator_trace_init - Send request to enable iterator
* trace port.
@ -2188,50 +2204,35 @@ u32 kbase_csf_firmware_reset_mcu_core_pwroff_time(struct kbase_device *kbdev)
*/
static int kbase_device_csf_iterator_trace_init(struct kbase_device *kbdev)
{
/* Enable the iterator trace port if supported by the GPU.
* It requires the GPU to have a nonzero "iter-trace-enable"
* property in the device tree, and the FW must advertise
* this feature in GLB_FEATURES.
/* Enable the iterator trace port if supported by the GPU and is
* configured to do so. The FW must advertise this feature in GLB_FEATURES.
*/
if (kbdev->pm.backend.gpu_powered) {
/* check device tree for iterator trace enable property
* and fallback to "iter_trace_enable" if it is not found
*/
const void *iter_trace_param =
of_get_property(kbdev->dev->of_node, "iter-trace-enable", NULL);
const struct kbase_csf_global_iface *iface = &kbdev->csf.global_iface;
bool dev_support_iter_trace = iface->features &
GLB_FEATURES_ITER_TRACE_SUPPORTED_MASK;
if (!iter_trace_param)
iter_trace_param =
of_get_property(kbdev->dev->of_node, "iter_trace_enable", NULL);
dev_dbg(kbdev->dev, "Device supporting iterator trace: %s\n",
dev_support_iter_trace ? "true" : "false");
if (dev_support_iter_trace && kbase_csf_get_iterator_trace_enable(kbdev)) {
long ack_timeout = kbase_csf_timeout_in_jiffies(
kbase_get_timeout_ms(kbdev, CSF_FIRMWARE_TIMEOUT));
if (iter_trace_param) {
u32 iter_trace_value = be32_to_cpup(iter_trace_param);
/* write enable request to global input */
kbase_csf_firmware_global_input_mask(iface, GLB_REQ,
GLB_REQ_ITER_TRACE_ENABLE_MASK,
GLB_REQ_ITER_TRACE_ENABLE_MASK);
/* Ring global doorbell */
kbase_csf_ring_doorbell(kbdev, CSF_KERNEL_DOORBELL_NR);
if ((iface->features & GLB_FEATURES_ITER_TRACE_SUPPORTED_MASK) &&
iter_trace_value) {
long ack_timeout;
ack_timeout = wait_event_timeout(
kbdev->csf.event_wait,
!((kbase_csf_firmware_global_input_read(iface, GLB_REQ) ^
kbase_csf_firmware_global_output(iface, GLB_ACK)) &
GLB_REQ_ITER_TRACE_ENABLE_MASK),
ack_timeout);
ack_timeout = kbase_csf_timeout_in_jiffies(
kbase_get_timeout_ms(kbdev, CSF_FIRMWARE_TIMEOUT));
/* write enable request to global input */
kbase_csf_firmware_global_input_mask(
iface, GLB_REQ, GLB_REQ_ITER_TRACE_ENABLE_MASK,
GLB_REQ_ITER_TRACE_ENABLE_MASK);
/* Ring global doorbell */
kbase_csf_ring_doorbell(kbdev, CSF_KERNEL_DOORBELL_NR);
ack_timeout = wait_event_timeout(
kbdev->csf.event_wait,
!((kbase_csf_firmware_global_input_read(iface, GLB_REQ) ^
kbase_csf_firmware_global_output(iface, GLB_ACK)) &
GLB_REQ_ITER_TRACE_ENABLE_MASK),
ack_timeout);
return ack_timeout ? 0 : -EINVAL;
}
return ack_timeout ? 0 : -EINVAL;
}
}
return 0;
@ -2241,8 +2242,6 @@ int kbase_csf_firmware_early_init(struct kbase_device *kbdev)
{
init_waitqueue_head(&kbdev->csf.event_wait);
kbdev->csf.fw_timeout_ms = kbase_get_timeout_ms(kbdev, CSF_FIRMWARE_TIMEOUT);
kbase_csf_firmware_reset_mcu_core_pwroff_time(kbdev);
INIT_LIST_HEAD(&kbdev->csf.firmware_interfaces);
INIT_LIST_HEAD(&kbdev->csf.firmware_config);
@ -2270,7 +2269,7 @@ void kbase_csf_firmware_early_term(struct kbase_device *kbdev)
int kbase_csf_firmware_late_init(struct kbase_device *kbdev)
{
u32 modifier = 0;
u32 no_modifier = 0;
kbdev->csf.gpu_idle_hysteresis_ns = FIRMWARE_IDLE_HYSTERESIS_TIME_NS;
@ -2280,8 +2279,8 @@ int kbase_csf_firmware_late_init(struct kbase_device *kbdev)
#endif
WARN_ON(!kbdev->csf.gpu_idle_hysteresis_ns);
kbdev->csf.gpu_idle_dur_count =
convert_dur_to_idle_count(kbdev, kbdev->csf.gpu_idle_hysteresis_ns, &modifier);
kbdev->csf.gpu_idle_dur_count_modifier = modifier;
convert_dur_to_idle_count(kbdev, kbdev->csf.gpu_idle_hysteresis_ns, &no_modifier);
kbdev->csf.gpu_idle_dur_count_no_modifier = no_modifier;
return 0;
}
@ -2694,7 +2693,9 @@ int kbase_csf_firmware_mcu_register_read(struct kbase_device *const kbdev, u32 c
int kbase_csf_firmware_mcu_register_poll(struct kbase_device *const kbdev, u32 const reg_addr,
u32 const val_mask, u32 const reg_val)
{
unsigned long remaining = kbase_csf_timeout_in_jiffies(kbdev->csf.fw_timeout_ms) + jiffies;
unsigned long remaining =
kbase_csf_timeout_in_jiffies(kbase_get_timeout_ms(kbdev, CSF_FIRMWARE_TIMEOUT)) +
jiffies;
u32 read_val;
dev_dbg(kbdev->dev, "p: reg %08x val %08x mask %08x", reg_addr, reg_val, val_mask);
@ -2922,6 +2923,12 @@ int kbase_csf_trigger_firmware_config_update(struct kbase_device *kbdev)
unsigned long flags;
int err = 0;
err = kbase_reset_gpu_prevent_and_wait(kbdev);
if (err) {
dev_warn(kbdev->dev, "Unsuccessful GPU reset detected when updating FW config");
return err;
}
/* Ensure GPU is powered-up until we complete config update.*/
kbase_csf_scheduler_pm_active(kbdev);
err = kbase_csf_scheduler_killable_wait_mcu_active(kbdev);
@ -2944,6 +2951,7 @@ int kbase_csf_trigger_firmware_config_update(struct kbase_device *kbdev)
exit:
kbase_csf_scheduler_pm_idle(kbdev);
kbase_reset_gpu_allow(kbdev);
return err;
}

21
drivers/gpu/arm/midgard/csf/mali_kbase_csf_firmware.h
View File

@ -24,6 +24,7 @@
#include "device/mali_kbase_device.h"
#include <csf/mali_kbase_csf_registers.h>
#include <hw_access/mali_kbase_hw_access_regmap.h>
#include <uapi/gpu/arm/midgard/gpu/mali_kbase_gpu_regmap.h>
/*
@ -770,9 +771,9 @@ extern bool fw_debug;
static inline long kbase_csf_timeout_in_jiffies(const unsigned int msecs)
{
#ifdef CONFIG_MALI_DEBUG
return (fw_debug ? MAX_SCHEDULE_TIMEOUT : msecs_to_jiffies(msecs));
return (fw_debug ? MAX_SCHEDULE_TIMEOUT : (long)msecs_to_jiffies(msecs));
#else
return msecs_to_jiffies(msecs);
return (long)msecs_to_jiffies(msecs);
#endif
}
@ -807,15 +808,15 @@ void kbase_csf_firmware_disable_gpu_idle_timer(struct kbase_device *kbdev);
*
* Return: the internally recorded hysteresis (nominal) value.
*/
u32 kbase_csf_firmware_get_gpu_idle_hysteresis_time(struct kbase_device *kbdev);
u64 kbase_csf_firmware_get_gpu_idle_hysteresis_time(struct kbase_device *kbdev);
/**
* kbase_csf_firmware_set_gpu_idle_hysteresis_time - Set the firmware GPU idle
* detection hysteresis duration
*
* @kbdev: Instance of a GPU platform device that implements a CSF interface.
* @dur: The duration value (unit: milliseconds) for the configuring
* hysteresis field for GPU idle detection
* @kbdev: Instance of a GPU platform device that implements a CSF interface.
* @dur_ns: The duration value (unit: nanoseconds) for the configuring
* hysteresis field for GPU idle detection
*
* The supplied value will be recorded internally without any change. But the
* actual field value will be subject to hysteresis source frequency scaling
@ -827,7 +828,7 @@ u32 kbase_csf_firmware_get_gpu_idle_hysteresis_time(struct kbase_device *kbdev);
*
* Return: the actual internally configured hysteresis field value.
*/
u32 kbase_csf_firmware_set_gpu_idle_hysteresis_time(struct kbase_device *kbdev, u32 dur);
u32 kbase_csf_firmware_set_gpu_idle_hysteresis_time(struct kbase_device *kbdev, u64 dur_ns);
/**
* kbase_csf_firmware_get_mcu_core_pwroff_time - Get the MCU shader Core power-off
@ -838,14 +839,14 @@ u32 kbase_csf_firmware_set_gpu_idle_hysteresis_time(struct kbase_device *kbdev,
* Return: the internally recorded MCU shader Core power-off (nominal) timeout value. The unit
* of the value is in micro-seconds.
*/
u32 kbase_csf_firmware_get_mcu_core_pwroff_time(struct kbase_device *kbdev);
u64 kbase_csf_firmware_get_mcu_core_pwroff_time(struct kbase_device *kbdev);
/**
* kbase_csf_firmware_set_mcu_core_pwroff_time - Set the MCU shader Core power-off
* time value
*
* @kbdev: Instance of a GPU platform device that implements a CSF interface.
* @dur: The duration value (unit: micro-seconds) for configuring MCU
* @dur_ns: The duration value (unit: nanoseconds) for configuring MCU
* core power-off timer, when the shader cores' power
* transitions are delegated to the MCU (normal operational
* mode)
@ -864,7 +865,7 @@ u32 kbase_csf_firmware_get_mcu_core_pwroff_time(struct kbase_device *kbdev);
* Return: the actual internal core power-off timer value in register defined
* format.
*/
u32 kbase_csf_firmware_set_mcu_core_pwroff_time(struct kbase_device *kbdev, u32 dur);
u32 kbase_csf_firmware_set_mcu_core_pwroff_time(struct kbase_device *kbdev, u64 dur_ns);
/**
* kbase_csf_firmware_reset_mcu_core_pwroff_time - Reset the MCU shader Core power-off

10
drivers/gpu/arm/midgard/csf/mali_kbase_csf_firmware_cfg.c
View File

@ -145,7 +145,7 @@ static ssize_t store_fw_cfg(struct kobject *kobj, struct attribute *attr, const
cur_val = config->cur_val;
if (cur_val == val) {
spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags);
return count;
return (ssize_t)count;
}
/* If configuration update cannot be performed with
@ -209,7 +209,7 @@ static ssize_t store_fw_cfg(struct kobject *kobj, struct attribute *attr, const
return -EINVAL;
}
return count;
return (ssize_t)count;
}
static const struct sysfs_ops fw_cfg_ops = {
@ -373,17 +373,17 @@ int kbase_csf_firmware_cfg_fw_wa_init(struct kbase_device *kbdev)
if (entry_count == -EINVAL || entry_count == -ENODATA)
return 0;
entry_bytes = entry_count * sizeof(u32);
entry_bytes = (size_t)entry_count * sizeof(u32);
kbdev->csf.quirks_ext = kzalloc(entry_bytes, GFP_KERNEL);
if (!kbdev->csf.quirks_ext)
return -ENOMEM;
ret = of_property_read_u32_array(kbdev->dev->of_node, "quirks-ext", kbdev->csf.quirks_ext,
entry_count);
(size_t)entry_count);
if (ret == -EINVAL)
ret = of_property_read_u32_array(kbdev->dev->of_node, "quirks_ext",
kbdev->csf.quirks_ext, entry_count);
kbdev->csf.quirks_ext, (size_t)entry_count);
if (ret == -EINVAL || ret == -ENODATA) {
/* This is unexpected since the property is already accessed for counting the number

13
drivers/gpu/arm/midgard/csf/mali_kbase_csf_firmware_log.c
View File

@ -144,7 +144,7 @@ static ssize_t kbasep_csf_firmware_log_debugfs_read(struct file *file, char __us
}
*ppos += n_read;
ret = n_read;
ret = (int)n_read;
out:
atomic_set(&fw_log->busy, 0);
@ -178,8 +178,9 @@ static int kbase_csf_firmware_log_mode_write(void *data, u64 val)
break;
case KBASE_CSF_FIRMWARE_LOG_MODE_AUTO_PRINT:
case KBASE_CSF_FIRMWARE_LOG_MODE_AUTO_DISCARD:
schedule_delayed_work(&fw_log->poll_work,
msecs_to_jiffies(atomic_read(&fw_log->poll_period_ms)));
schedule_delayed_work(
&fw_log->poll_work,
msecs_to_jiffies((unsigned int)atomic_read(&fw_log->poll_period_ms)));
break;
default:
ret = -EINVAL;
@ -198,7 +199,7 @@ static int kbase_csf_firmware_log_poll_period_read(void *data, u64 *val)
struct kbase_device *kbdev = (struct kbase_device *)data;
struct kbase_csf_firmware_log *fw_log = &kbdev->csf.fw_log;
*val = atomic_read(&fw_log->poll_period_ms);
*val = (u64)atomic_read(&fw_log->poll_period_ms);
return 0;
}
@ -263,7 +264,7 @@ static void kbase_csf_firmware_log_poll(struct work_struct *work)
return;
schedule_delayed_work(&fw_log->poll_work,
msecs_to_jiffies(atomic_read(&fw_log->poll_period_ms)));
msecs_to_jiffies((unsigned int)atomic_read(&fw_log->poll_period_ms)));
}
int kbase_csf_firmware_log_init(struct kbase_device *kbdev)
@ -382,7 +383,7 @@ void kbase_csf_firmware_log_dump_buffer(struct kbase_device *kbdev)
pend = p + read_size;
p = buf;
while (p < pend && (pnewline = memchr(p, '\n', pend - p))) {
while (p < pend && (pnewline = memchr(p, '\n', (size_t)(pend - p)))) {
/* Null-terminate the string */
*pnewline = 0;

123
drivers/gpu/arm/midgard/csf/mali_kbase_csf_firmware_no_mali.c
View File

@ -533,9 +533,9 @@ EXPORT_SYMBOL(kbase_csf_ring_doorbell);
*/
static void handle_internal_firmware_fatal(struct kbase_device *const kbdev)
{
int as;
size_t as;
for (as = 0; as < kbdev->nr_hw_address_spaces; as++) {
for (as = 0; as < (size_t)kbdev->nr_hw_address_spaces; as++) {
unsigned long flags;
struct kbase_context *kctx;
struct kbase_fault fault;
@ -604,7 +604,8 @@ static bool global_request_complete(struct kbase_device *const kbdev, u32 const
static int wait_for_global_request(struct kbase_device *const kbdev, u32 const req_mask)
{
const long wait_timeout = kbase_csf_timeout_in_jiffies(kbdev->csf.fw_timeout_ms);
const long wait_timeout =
kbase_csf_timeout_in_jiffies(kbase_get_timeout_ms(kbdev, CSF_FIRMWARE_TIMEOUT));
long remaining;
int err = 0;
@ -893,12 +894,12 @@ void kbase_csf_firmware_reload_completed(struct kbase_device *kbdev)
kbase_pm_update_state(kbdev);
}
static u32 convert_dur_to_idle_count(struct kbase_device *kbdev, const u32 dur_ms, u32 *modifier)
static u32 convert_dur_to_idle_count(struct kbase_device *kbdev, const u32 dur_ns, u32 *no_modifier)
{
#define HYSTERESIS_VAL_UNIT_SHIFT (10)
/* Get the cntfreq_el0 value, which drives the SYSTEM_TIMESTAMP */
u64 freq = arch_timer_get_cntfrq();
u64 dur_val = dur_ms;
u64 freq = kbase_arch_timer_get_cntfrq(kbdev);
u64 dur_val = dur_ns;
u32 cnt_val_u32, reg_val_u32;
bool src_system_timestamp = freq > 0;
@ -916,45 +917,46 @@ static u32 convert_dur_to_idle_count(struct kbase_device *kbdev, const u32 dur_m
"Can't get the timestamp frequency, use cycle counter format with firmware idle hysteresis!");
}
/* Formula for dur_val = ((dur_ms/1000) * freq_HZ) >> 10) */
dur_val = (dur_val * freq) >> HYSTERESIS_VAL_UNIT_SHIFT;
dur_val = div_u64(dur_val, 1000);
*modifier = 0;
/* Formula for dur_val = (dur/1e9) * freq_HZ) */
dur_val = dur_val * freq;
dur_val = div_u64(dur_val, NSEC_PER_SEC);
if (dur_val < S32_MAX) {
*no_modifier = 1;
} else {
dur_val = dur_val >> HYSTERESIS_VAL_UNIT_SHIFT;
*no_modifier = 0;
}
/* Interface limits the value field to S32_MAX */
cnt_val_u32 = (dur_val > S32_MAX) ? S32_MAX : (u32)dur_val;
reg_val_u32 = GLB_IDLE_TIMER_TIMEOUT_SET(0, cnt_val_u32);
/* add the source flag */
if (src_system_timestamp)
reg_val_u32 = GLB_IDLE_TIMER_TIMER_SOURCE_SET(
reg_val_u32, GLB_IDLE_TIMER_TIMER_SOURCE_SYSTEM_TIMESTAMP);
else
reg_val_u32 = GLB_IDLE_TIMER_TIMER_SOURCE_SET(
reg_val_u32, GLB_IDLE_TIMER_TIMER_SOURCE_GPU_COUNTER);
reg_val_u32 = GLB_IDLE_TIMER_TIMER_SOURCE_SET(
reg_val_u32, (src_system_timestamp ? GLB_IDLE_TIMER_TIMER_SOURCE_SYSTEM_TIMESTAMP :
GLB_IDLE_TIMER_TIMER_SOURCE_GPU_COUNTER));
return reg_val_u32;
}
u32 kbase_csf_firmware_get_gpu_idle_hysteresis_time(struct kbase_device *kbdev)
u64 kbase_csf_firmware_get_gpu_idle_hysteresis_time(struct kbase_device *kbdev)
{
unsigned long flags;
u32 dur;
u64 dur_ns;
kbase_csf_scheduler_spin_lock(kbdev, &flags);
dur = kbdev->csf.gpu_idle_hysteresis_ns;
dur_ns = kbdev->csf.gpu_idle_hysteresis_ns;
kbase_csf_scheduler_spin_unlock(kbdev, flags);
return dur;
return dur_ns;
}
u32 kbase_csf_firmware_set_gpu_idle_hysteresis_time(struct kbase_device *kbdev, u32 dur)
u32 kbase_csf_firmware_set_gpu_idle_hysteresis_time(struct kbase_device *kbdev, u64 dur_ns)
{
unsigned long flags;
u32 modifier = 0;
u32 no_modifier = 0;
const u32 hysteresis_val = convert_dur_to_idle_count(kbdev, dur, &modifier);
const u32 hysteresis_val = convert_dur_to_idle_count(kbdev, dur_ns, &no_modifier);
/* The 'fw_load_lock' is taken to synchronize against the deferred
* loading of FW, where the idle timer will be enabled.
@ -962,9 +964,9 @@ u32 kbase_csf_firmware_set_gpu_idle_hysteresis_time(struct kbase_device *kbdev,
mutex_lock(&kbdev->fw_load_lock);
if (unlikely(!kbdev->csf.firmware_inited)) {
kbase_csf_scheduler_spin_lock(kbdev, &flags);
kbdev->csf.gpu_idle_hysteresis_ns = dur;
kbdev->csf.gpu_idle_hysteresis_ns = dur_ns;
kbdev->csf.gpu_idle_dur_count = hysteresis_val;
kbdev->csf.gpu_idle_dur_count_modifier = modifier;
kbdev->csf.gpu_idle_dur_count_no_modifier = no_modifier;
kbase_csf_scheduler_spin_unlock(kbdev, flags);
mutex_unlock(&kbdev->fw_load_lock);
goto end;
@ -1002,9 +1004,9 @@ u32 kbase_csf_firmware_set_gpu_idle_hysteresis_time(struct kbase_device *kbdev,
wait_for_global_request(kbdev, GLB_REQ_IDLE_DISABLE_MASK);
kbase_csf_scheduler_spin_lock(kbdev, &flags);
kbdev->csf.gpu_idle_hysteresis_ns = dur;
kbdev->csf.gpu_idle_hysteresis_ns = dur_ns;
kbdev->csf.gpu_idle_dur_count = hysteresis_val;
kbdev->csf.gpu_idle_dur_count_modifier = modifier;
kbdev->csf.gpu_idle_dur_count_no_modifier = no_modifier;
kbase_csf_firmware_enable_gpu_idle_timer(kbdev);
kbase_csf_scheduler_spin_unlock(kbdev, flags);
wait_for_global_request(kbdev, GLB_REQ_IDLE_ENABLE_MASK);
@ -1018,12 +1020,12 @@ end:
return hysteresis_val;
}
static u32 convert_dur_to_core_pwroff_count(struct kbase_device *kbdev, const u32 dur_us,
u32 *modifier)
static u32 convert_dur_to_core_pwroff_count(struct kbase_device *kbdev, const u64 dur_ns,
u32 *no_modifier)
{
/* Get the cntfreq_el0 value, which drives the SYSTEM_TIMESTAMP */
u64 freq = arch_timer_get_cntfrq();
u64 dur_val = dur_us;
u64 freq = kbase_arch_timer_get_cntfrq(kbdev);
u64 dur_val = dur_ns;
u32 cnt_val_u32, reg_val_u32;
bool src_system_timestamp = freq > 0;
@ -1041,50 +1043,57 @@ static u32 convert_dur_to_core_pwroff_count(struct kbase_device *kbdev, const u3
"Can't get the timestamp frequency, use cycle counter with MCU shader Core Poweroff timer!");
}
/* Formula for dur_val = ((dur_us/1e6) * freq_HZ) >> 10) */
dur_val = (dur_val * freq) >> HYSTERESIS_VAL_UNIT_SHIFT;
dur_val = div_u64(dur_val, 1000000);
*modifier = 0;
/* Formula for dur_val = (dur/1e9) * freq_HZ) */
dur_val = dur_val * freq;
dur_val = div_u64(dur_val, NSEC_PER_SEC);
if (dur_val < S32_MAX) {
*no_modifier = 1;
} else {
dur_val = dur_val >> HYSTERESIS_VAL_UNIT_SHIFT;
*no_modifier = 0;
}
/* Interface limits the value field to S32_MAX */
cnt_val_u32 = (dur_val > S32_MAX) ? S32_MAX : (u32)dur_val;
if (dur_val > S32_MAX) {
/* Upper Bound - as interface limits the field to S32_MAX */
cnt_val_u32 = S32_MAX;
} else {
cnt_val_u32 = (u32)dur_val;
}
reg_val_u32 = GLB_PWROFF_TIMER_TIMEOUT_SET(0, cnt_val_u32);
/* add the source flag */
if (src_system_timestamp)
reg_val_u32 = GLB_PWROFF_TIMER_TIMER_SOURCE_SET(
reg_val_u32, GLB_PWROFF_TIMER_TIMER_SOURCE_SYSTEM_TIMESTAMP);
else
reg_val_u32 = GLB_PWROFF_TIMER_TIMER_SOURCE_SET(
reg_val_u32, GLB_PWROFF_TIMER_TIMER_SOURCE_GPU_COUNTER);
reg_val_u32 = GLB_PWROFF_TIMER_TIMER_SOURCE_SET(
reg_val_u32,
(src_system_timestamp ? GLB_PWROFF_TIMER_TIMER_SOURCE_SYSTEM_TIMESTAMP :
GLB_PWROFF_TIMER_TIMER_SOURCE_GPU_COUNTER));
return reg_val_u32;
}
u32 kbase_csf_firmware_get_mcu_core_pwroff_time(struct kbase_device *kbdev)
u64 kbase_csf_firmware_get_mcu_core_pwroff_time(struct kbase_device *kbdev)
{
u32 pwroff;
u64 pwroff_ns;
unsigned long flags;
spin_lock_irqsave(&kbdev->hwaccess_lock, flags);
pwroff = kbdev->csf.mcu_core_pwroff_dur_ns;
pwroff_ns = kbdev->csf.mcu_core_pwroff_dur_ns;
spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags);
return pwroff;
return pwroff_ns;
}
u32 kbase_csf_firmware_set_mcu_core_pwroff_time(struct kbase_device *kbdev, u32 dur)
u32 kbase_csf_firmware_set_mcu_core_pwroff_time(struct kbase_device *kbdev, u64 dur_ns)
{
unsigned long flags;
u32 modifier = 0;
u32 no_modifier = 0;
const u32 pwroff = convert_dur_to_core_pwroff_count(kbdev, dur, &modifier);
const u32 pwroff = convert_dur_to_core_pwroff_count(kbdev, dur_ns, &no_modifier);
spin_lock_irqsave(&kbdev->hwaccess_lock, flags);
kbdev->csf.mcu_core_pwroff_dur_ns = dur;
kbdev->csf.mcu_core_pwroff_dur_ns = dur_ns;
kbdev->csf.mcu_core_pwroff_dur_count = pwroff;
kbdev->csf.mcu_core_pwroff_dur_count_modifier = modifier;
kbdev->csf.mcu_core_pwroff_dur_count_no_modifier = no_modifier;
spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags);
dev_dbg(kbdev->dev, "MCU shader Core Poweroff input update: 0x%.8x", pwroff);
@ -1101,8 +1110,6 @@ int kbase_csf_firmware_early_init(struct kbase_device *kbdev)
{
init_waitqueue_head(&kbdev->csf.event_wait);
kbdev->csf.fw_timeout_ms = kbase_get_timeout_ms(kbdev, CSF_FIRMWARE_TIMEOUT);
kbase_csf_firmware_reset_mcu_core_pwroff_time(kbdev);
INIT_LIST_HEAD(&kbdev->csf.firmware_interfaces);
INIT_LIST_HEAD(&kbdev->csf.firmware_config);
@ -1125,7 +1132,7 @@ void kbase_csf_firmware_early_term(struct kbase_device *kbdev)
int kbase_csf_firmware_late_init(struct kbase_device *kbdev)
{
u32 modifier = 0;
u32 no_modifier = 0;
kbdev->csf.gpu_idle_hysteresis_ns = FIRMWARE_IDLE_HYSTERESIS_TIME_NS;
#ifdef KBASE_PM_RUNTIME
@ -1134,8 +1141,8 @@ int kbase_csf_firmware_late_init(struct kbase_device *kbdev)
#endif
WARN_ON(!kbdev->csf.gpu_idle_hysteresis_ns);
kbdev->csf.gpu_idle_dur_count =
convert_dur_to_idle_count(kbdev, kbdev->csf.gpu_idle_hysteresis_ns, &modifier);
kbdev->csf.gpu_idle_dur_count_modifier = modifier;
convert_dur_to_idle_count(kbdev, kbdev->csf.gpu_idle_hysteresis_ns, &no_modifier);
kbdev->csf.gpu_idle_dur_count_no_modifier = no_modifier;
return 0;
}

103
drivers/gpu/arm/midgard/csf/mali_kbase_csf_kcpu.c
View File

@ -464,7 +464,9 @@ static void kbase_kcpu_jit_retry_pending_allocs(struct kbase_context *kctx)
* kbase_csf_kcpu_queue_context.jit_lock .
*/
list_for_each_entry(blocked_queue, &kctx->csf.kcpu_queues.jit_blocked_queues, jit_blocked)
queue_work(blocked_queue->wq, &blocked_queue->work);
queue_work(atomic_read(&kctx->prioritized) ? kctx->csf.kcpu_wq_high_prio :
kctx->csf.kcpu_wq_normal_prio,
&blocked_queue->work);
}
static int kbase_kcpu_jit_free_process(struct kbase_kcpu_command_queue *queue,
@ -510,7 +512,7 @@ static int kbase_kcpu_jit_free_process(struct kbase_kcpu_command_queue *queue,
}
KBASE_TLSTREAM_TL_KBASE_ARRAY_ITEM_KCPUQUEUE_EXECUTE_JIT_FREE_END(
queue->kctx->kbdev, queue, item_err, pages_used);
queue->kctx->kbdev, queue, (u32)item_err, pages_used);
}
/*
@ -611,7 +613,7 @@ kbase_csf_queue_group_suspend_prepare(struct kbase_kcpu_command_queue *kcpu_queu
u64 page_addr = addr & PAGE_MASK;
u64 end_addr = addr + csg_suspend_buf_size - 1;
u64 last_page_addr = end_addr & PAGE_MASK;
int nr_pages = (last_page_addr - page_addr) / PAGE_SIZE + 1;
unsigned int nr_pages = (last_page_addr - page_addr) / PAGE_SIZE + 1;
int pinned_pages = 0, ret = 0;
struct kbase_va_region *reg;
@ -647,7 +649,7 @@ kbase_csf_queue_group_suspend_prepare(struct kbase_kcpu_command_queue *kcpu_queu
if (kbase_is_region_invalid_or_free(reg)) {
kbase_gpu_vm_unlock(kctx);
pinned_pages = get_user_pages_fast(page_addr, nr_pages, 1, sus_buf->pages);
pinned_pages = get_user_pages_fast(page_addr, (int)nr_pages, 1, sus_buf->pages);
kbase_gpu_vm_lock(kctx);
if (pinned_pages < 0) {
@ -715,8 +717,11 @@ static int kbase_csf_queue_group_suspend_process(struct kbase_context *kctx,
static enum kbase_csf_event_callback_action event_cqs_callback(void *param)
{
struct kbase_kcpu_command_queue *kcpu_queue = (struct kbase_kcpu_command_queue *)param;
struct kbase_context *kctx = kcpu_queue->kctx;
queue_work(kcpu_queue->wq, &kcpu_queue->work);
queue_work(atomic_read(&kctx->prioritized) ? kctx->csf.kcpu_wq_high_prio :
kctx->csf.kcpu_wq_normal_prio,
&kcpu_queue->work);
return KBASE_CSF_EVENT_CALLBACK_KEEP;
}
@ -1301,11 +1306,7 @@ static int kbase_kcpu_cqs_set_operation_prepare(
}
#if IS_ENABLED(CONFIG_SYNC_FILE)
#if (KERNEL_VERSION(4, 10, 0) > LINUX_VERSION_CODE)
static void kbase_csf_fence_wait_callback(struct fence *fence, struct fence_cb *cb)
#else
static void kbase_csf_fence_wait_callback(struct dma_fence *fence, struct dma_fence_cb *cb)
#endif
{
struct kbase_kcpu_command_fence_info *fence_info =
container_of(cb, struct kbase_kcpu_command_fence_info, fence_cb);
@ -1321,7 +1322,9 @@ static void kbase_csf_fence_wait_callback(struct dma_fence *fence, struct dma_fe
fence->seqno);
/* Resume kcpu command queue processing. */
queue_work(kcpu_queue->wq, &kcpu_queue->work);
queue_work(atomic_read(&kctx->prioritized) ? kctx->csf.kcpu_wq_high_prio :
kctx->csf.kcpu_wq_normal_prio,
&kcpu_queue->work);
}
static void kbasep_kcpu_fence_wait_cancel(struct kbase_kcpu_command_queue *kcpu_queue,
@ -1374,11 +1377,7 @@ static void fence_timeout_callback(struct timer_list *timer)
struct kbase_context *const kctx = kcpu_queue->kctx;
struct kbase_kcpu_command *cmd = &kcpu_queue->commands[kcpu_queue->start_offset];
struct kbase_kcpu_command_fence_info *fence_info;
#if (KERNEL_VERSION(4, 10, 0) > LINUX_VERSION_CODE)
struct fence *fence;
#else
struct dma_fence *fence;
#endif
struct kbase_sync_fence_info info;
if (cmd->type != BASE_KCPU_COMMAND_TYPE_FENCE_WAIT) {
@ -1400,7 +1399,9 @@ static void fence_timeout_callback(struct timer_list *timer)
kbase_sync_fence_info_get(fence, &info);
if (info.status == 1) {
queue_work(kcpu_queue->wq, &kcpu_queue->work);
queue_work(atomic_read(&kctx->prioritized) ? kctx->csf.kcpu_wq_high_prio :
kctx->csf.kcpu_wq_normal_prio,
&kcpu_queue->work);
} else if (info.status == 0) {
dev_warn(kctx->kbdev->dev, "fence has not yet signalled in %ums",
FENCE_WAIT_TIMEOUT_MS);
@ -1444,11 +1445,7 @@ static int kbase_kcpu_fence_wait_process(struct kbase_kcpu_command_queue *kcpu_q
struct kbase_kcpu_command_fence_info *fence_info)
{
int fence_status = 0;
#if (KERNEL_VERSION(4, 10, 0) > LINUX_VERSION_CODE)
struct fence *fence;
#else
struct dma_fence *fence;
#endif
struct kbase_context *const kctx = kcpu_queue->kctx;
lockdep_assert_held(&kcpu_queue->lock);
@ -1514,11 +1511,7 @@ static int kbase_kcpu_fence_wait_prepare(struct kbase_kcpu_command_queue *kcpu_q
struct base_kcpu_command_fence_info *fence_info,
struct kbase_kcpu_command *current_command)
{
#if (KERNEL_VERSION(4, 10, 0) > LINUX_VERSION_CODE)
struct fence *fence_in;
#else
struct dma_fence *fence_in;
#endif
struct base_fence fence;
lockdep_assert_held(&kcpu_queue->lock);
@ -1613,11 +1606,7 @@ static void kcpu_force_signal_fence(struct kbase_kcpu_command_queue *kcpu_queue)
{
int status;
int i;
#if (KERNEL_VERSION(4, 10, 0) > LINUX_VERSION_CODE)
struct fence *fence;
#else
struct dma_fence *fence;
#endif
struct kbase_context *const kctx = kcpu_queue->kctx;
#ifdef CONFIG_MALI_FENCE_DEBUG
int del;
@ -1703,7 +1692,9 @@ static void fence_signal_timeout_cb(struct timer_list *timer)
if (atomic_read(&kcpu_queue->fence_signal_pending_cnt) > 1)
fence_signal_timeout_start(kcpu_queue);
queue_work(kcpu_queue->wq, &kcpu_queue->timeout_work);
queue_work(atomic_read(&kctx->prioritized) ? kctx->csf.kcpu_wq_high_prio :
kctx->csf.kcpu_wq_normal_prio,
&kcpu_queue->timeout_work);
}
}
@ -1762,11 +1753,7 @@ static int kbasep_kcpu_fence_signal_init(struct kbase_kcpu_command_queue *kcpu_q
struct base_fence *fence, struct sync_file **sync_file,
int *fd)
{
#if (KERNEL_VERSION(4, 10, 0) > LINUX_VERSION_CODE)
struct fence *fence_out;
#else
struct dma_fence *fence_out;
#endif
struct kbase_kcpu_dma_fence *kcpu_fence;
int ret = 0;
@ -1780,11 +1767,7 @@ static int kbasep_kcpu_fence_signal_init(struct kbase_kcpu_command_queue *kcpu_q
kcpu_fence->metadata = kcpu_queue->metadata;
WARN_ON(!kbase_refcount_inc_not_zero(&kcpu_fence->metadata->refcount));
#if (KERNEL_VERSION(4, 10, 0) > LINUX_VERSION_CODE)
fence_out = (struct fence *)kcpu_fence;
#else
fence_out = (struct dma_fence *)kcpu_fence;
#endif
dma_fence_init(fence_out, &kbase_fence_ops, &kbase_csf_fence_lock,
kcpu_queue->fence_context, ++kcpu_queue->fence_seqno);
@ -1859,7 +1842,7 @@ static int kbase_kcpu_fence_signal_prepare(struct kbase_kcpu_command_queue *kcpu
* installed, so the install step needs to be done at the last
* before returning success.
*/
fd_install(fd, sync_file->file);
fd_install((unsigned int)fd, sync_file->file);
if (atomic_inc_return(&kcpu_queue->fence_signal_pending_cnt) == 1)
fence_signal_timeout_start(kcpu_queue);
@ -1903,11 +1886,7 @@ static void kcpu_fence_timeout_dump(struct kbase_kcpu_command_queue *queue,
struct kbase_kcpu_command *cmd;
struct kbase_kcpu_command_fence_info *fence_info;
struct kbase_kcpu_dma_fence *kcpu_fence;
#if (KERNEL_VERSION(4, 10, 0) > LINUX_VERSION_CODE)
struct fence *fence;
#else
struct dma_fence *fence;
#endif
struct kbase_sync_fence_info info;
u16 i;
@ -2045,8 +2024,6 @@ static int delete_queue(struct kbase_context *kctx, u32 id)
cancel_work_sync(&queue->timeout_work);
cancel_work_sync(&queue->work);
destroy_workqueue(queue->wq);
mutex_destroy(&queue->lock);
kfree(queue);
@ -2085,7 +2062,7 @@ static void KBASE_TLSTREAM_TL_KBASE_KCPUQUEUE_EXECUTE_JIT_ALLOC_INFO(
#endif /* CONFIG_MALI_VECTOR_DUMP */
}
KBASE_TLSTREAM_TL_KBASE_ARRAY_ITEM_KCPUQUEUE_EXECUTE_JIT_ALLOC_END(
kbdev, queue, alloc_status, gpu_alloc_addr, mmu_flags);
kbdev, queue, (u32)alloc_status, gpu_alloc_addr, mmu_flags);
}
}
@ -2584,7 +2561,7 @@ int kbase_csf_kcpu_queue_enqueue(struct kbase_context *kctx,
}
}
kcpu_cmd->enqueue_ts = atomic64_inc_return(&kctx->csf.kcpu_queues.cmd_seq_num);
kcpu_cmd->enqueue_ts = (u64)atomic64_inc_return(&kctx->csf.kcpu_queues.cmd_seq_num);
switch (command.type) {
case BASE_KCPU_COMMAND_TYPE_FENCE_WAIT:
#if IS_ENABLED(CONFIG_SYNC_FILE)
@ -2676,6 +2653,23 @@ out:
int kbase_csf_kcpu_queue_context_init(struct kbase_context *kctx)
{
kctx->csf.kcpu_wq_high_prio = alloc_workqueue("mali_kcpu_wq_%i_high_prio",
WQ_UNBOUND | WQ_HIGHPRI, 0, kctx->tgid);
if (kctx->csf.kcpu_wq_high_prio == NULL) {
dev_err(kctx->kbdev->dev,
"Failed to initialize KCPU queue high-priority workqueue");
return -ENOMEM;
}
kctx->csf.kcpu_wq_normal_prio =
alloc_workqueue("mali_kcpu_wq_%i_normal_prio", 0, 0, kctx->tgid);
if (kctx->csf.kcpu_wq_normal_prio == NULL) {
dev_err(kctx->kbdev->dev,
"Failed to initialize KCPU queue normal-priority workqueue");
destroy_workqueue(kctx->csf.kcpu_wq_high_prio);
return -ENOMEM;
}
mutex_init(&kctx->csf.kcpu_queues.lock);
return 0;
@ -2689,10 +2683,13 @@ void kbase_csf_kcpu_queue_context_term(struct kbase_context *kctx)
if (WARN_ON(!kctx->csf.kcpu_queues.array[id]))
clear_bit(id, kctx->csf.kcpu_queues.in_use);
else
(void)delete_queue(kctx, id);
(void)delete_queue(kctx, (u32)id);
}
mutex_destroy(&kctx->csf.kcpu_queues.lock);
destroy_workqueue(kctx->csf.kcpu_wq_normal_prio);
destroy_workqueue(kctx->csf.kcpu_wq_high_prio);
}
KBASE_EXPORT_TEST_API(kbase_csf_kcpu_queue_context_term);
@ -2737,15 +2734,7 @@ int kbase_csf_kcpu_queue_new(struct kbase_context *kctx, struct kbase_ioctl_kcpu
goto out;
}
queue->wq = alloc_workqueue("mali_kbase_csf_kcpu_wq_%i", WQ_UNBOUND | WQ_HIGHPRI, 0, idx);
if (queue->wq == NULL) {
kfree(queue);
ret = -ENOMEM;
goto out;
}
bitmap_set(kctx->csf.kcpu_queues.in_use, idx, 1);
bitmap_set(kctx->csf.kcpu_queues.in_use, (unsigned int)idx, 1);
kctx->csf.kcpu_queues.array[idx] = queue;
mutex_init(&queue->lock);
queue->kctx = kctx;
@ -2758,7 +2747,6 @@ int kbase_csf_kcpu_queue_new(struct kbase_context *kctx, struct kbase_ioctl_kcpu
metadata = kzalloc(sizeof(*metadata), GFP_KERNEL);
if (!metadata) {
destroy_workqueue(queue->wq);
kfree(queue);
ret = -ENOMEM;
goto out;
@ -2766,10 +2754,9 @@ int kbase_csf_kcpu_queue_new(struct kbase_context *kctx, struct kbase_ioctl_kcpu
metadata->kbdev = kctx->kbdev;
metadata->kctx_id = kctx->id;
n = snprintf(metadata->timeline_name, MAX_TIMELINE_NAME, "%d-%d_%d-%lld-kcpu",
n = snprintf(metadata->timeline_name, MAX_TIMELINE_NAME, "%u-%d_%u-%llu-kcpu",
kctx->kbdev->id, kctx->tgid, kctx->id, queue->fence_context);
if (WARN_ON(n >= MAX_TIMELINE_NAME)) {
destroy_workqueue(queue->wq);
kfree(queue);
kfree(metadata);
ret = -EINVAL;

13
drivers/gpu/arm/midgard/csf/mali_kbase_csf_kcpu.h
View File

@ -25,11 +25,7 @@
#include <mali_kbase_fence.h>
#include <mali_kbase_sync.h>
#if (KERNEL_VERSION(4, 10, 0) > LINUX_VERSION_CODE)
#include <linux/fence.h>
#else
#include <linux/dma-fence.h>
#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(4, 10, 0) */
#include <linux/version_compat_defs.h>
/* The maximum number of KCPU commands in flight, enqueueing more commands
* than this value shall block.
@ -56,13 +52,8 @@ struct kbase_kcpu_command_import_info {
* @fence_has_force_signaled: fence has forced signaled after fence timeouted
*/
struct kbase_kcpu_command_fence_info {
#if (KERNEL_VERSION(4, 10, 0) > LINUX_VERSION_CODE)
struct fence_cb fence_cb;
struct fence *fence;
#else
struct dma_fence_cb fence_cb;
struct dma_fence *fence;
#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(4, 10, 0) */
struct kbase_kcpu_command_queue *kcpu_queue;
bool fence_has_force_signaled;
};
@ -249,7 +240,6 @@ struct kbase_kcpu_command {
* @kctx: The context to which this command queue belongs.
* @commands: Array of commands which have been successfully
* enqueued to this command queue.
* @wq: Dedicated workqueue for processing commands.
* @work: struct work_struct which contains a pointer to
* the function which handles processing of kcpu
* commands enqueued into a kcpu command queue;
@ -296,7 +286,6 @@ struct kbase_kcpu_command_queue {
struct mutex lock;
struct kbase_context *kctx;
struct kbase_kcpu_command commands[KBASEP_KCPU_QUEUE_SIZE];
struct workqueue_struct *wq;
struct work_struct work;
struct work_struct timeout_work;
u8 start_offset;

8
drivers/gpu/arm/midgard/csf/mali_kbase_csf_kcpu_fence_debugfs.c
View File

@ -60,9 +60,9 @@ static ssize_t kbase_csf_kcpu_queue_fence_signal_enabled_set(struct file *file,
if (ret < 0)
return ret;
atomic_set(&kbdev->fence_signal_timeout_enabled, enabled);
atomic_set(&kbdev->fence_signal_timeout_enabled, (int)enabled);
return count;
return (ssize_t)count;
}
static const struct file_operations kbase_csf_kcpu_queue_fence_signal_fops = {
@ -82,7 +82,7 @@ static ssize_t kbase_csf_kcpu_queue_fence_signal_timeout_get(struct file *file,
unsigned int timeout_ms = kbase_get_timeout_ms(kbdev, KCPU_FENCE_SIGNAL_TIMEOUT);
size = scnprintf(buffer, sizeof(buffer), "%u\n", timeout_ms);
return simple_read_from_buffer(buf, count, ppos, buffer, size);
return simple_read_from_buffer(buf, count, ppos, buffer, (size_t)size);
}
static ssize_t kbase_csf_kcpu_queue_fence_signal_timeout_set(struct file *file,
@ -105,7 +105,7 @@ static ssize_t kbase_csf_kcpu_queue_fence_signal_timeout_set(struct file *file,
*/
kbase_device_set_timeout_ms(kbdev, KCPU_FENCE_SIGNAL_TIMEOUT, timeout_ms);
return count;
return (ssize_t)count;
}
static const struct file_operations kbase_csf_kcpu_queue_fence_signal_timeout_fops = {

4
drivers/gpu/arm/midgard/csf/mali_kbase_csf_mcu_shared_reg.c
View File

@ -412,7 +412,7 @@ int kbase_csf_mcu_shared_add_queue(struct kbase_device *kbdev, struct kbase_queu
"No bound csg_reg, or in wrong state"))
return -EIO;
vpfn = CSG_REG_USERIO_VPFN(csg_reg->reg, queue->csi_index, nr_susp_pages);
vpfn = CSG_REG_USERIO_VPFN(csg_reg->reg, (u32)queue->csi_index, nr_susp_pages);
err = userio_pages_replace_phys(kbdev, vpfn, queue->phys);
if (likely(!err)) {
/* Mark the queue has been successfully mapped */
@ -452,7 +452,7 @@ void kbase_csf_mcu_shared_drop_stopped_queue(struct kbase_device *kbdev, struct
csg_reg = get_group_bound_csg_reg(group);
vpfn = CSG_REG_USERIO_VPFN(csg_reg->reg, queue->csi_index, nr_susp_pages);
vpfn = CSG_REG_USERIO_VPFN(csg_reg->reg, (u32)queue->csi_index, nr_susp_pages);
WARN_ONCE(userio_pages_replace_phys(kbdev, vpfn, NULL),
"Unexpected restoring to dummy map update error");

4
drivers/gpu/arm/midgard/csf/mali_kbase_csf_protected_memory.c
View File

@ -79,7 +79,7 @@ kbase_csf_protected_memory_alloc(struct kbase_device *const kbdev, struct tagged
unsigned int num_pages_order;
if (is_small_page)
order = KBASE_MEM_POOL_4KB_PAGE_TABLE_ORDER;
order = KBASE_MEM_POOL_SMALL_PAGE_TABLE_ORDER;
num_pages_order = (1u << order);
@ -135,7 +135,7 @@ void kbase_csf_protected_memory_free(struct kbase_device *const kbdev,
unsigned int num_pages_order = (1u << KBASE_MEM_POOL_2MB_PAGE_TABLE_ORDER);
if (is_small_page)
num_pages_order = (1u << KBASE_MEM_POOL_4KB_PAGE_TABLE_ORDER);
num_pages_order = (1u << KBASE_MEM_POOL_SMALL_PAGE_TABLE_ORDER);
if (WARN_ON(!pma_dev) || WARN_ON(!pma))
return;

84
drivers/gpu/arm/midgard/csf/mali_kbase_csf_registers.h
View File

@ -271,21 +271,21 @@
/* CS_KERNEL_INPUT_BLOCK register set definitions */
/* GLB_VERSION register */
#define GLB_VERSION_PATCH_SHIFT (0)
#define GLB_VERSION_PATCH_MASK ((0xFFFF) << GLB_VERSION_PATCH_SHIFT)
#define GLB_VERSION_PATCH_MASK ((0xFFFFU) << GLB_VERSION_PATCH_SHIFT)
#define GLB_VERSION_PATCH_GET(reg_val) \
(((reg_val)&GLB_VERSION_PATCH_MASK) >> GLB_VERSION_PATCH_SHIFT)
#define GLB_VERSION_PATCH_SET(reg_val, value) \
(((reg_val) & ~GLB_VERSION_PATCH_MASK) | \
(((value) << GLB_VERSION_PATCH_SHIFT) & GLB_VERSION_PATCH_MASK))
#define GLB_VERSION_MINOR_SHIFT (16)
#define GLB_VERSION_MINOR_MASK ((0xFF) << GLB_VERSION_MINOR_SHIFT)
#define GLB_VERSION_MINOR_MASK ((0xFFU) << GLB_VERSION_MINOR_SHIFT)
#define GLB_VERSION_MINOR_GET(reg_val) \
(((reg_val)&GLB_VERSION_MINOR_MASK) >> GLB_VERSION_MINOR_SHIFT)
#define GLB_VERSION_MINOR_SET(reg_val, value) \
(((reg_val) & ~GLB_VERSION_MINOR_MASK) | \
(((value) << GLB_VERSION_MINOR_SHIFT) & GLB_VERSION_MINOR_MASK))
#define GLB_VERSION_MAJOR_SHIFT (24)
#define GLB_VERSION_MAJOR_MASK ((0xFF) << GLB_VERSION_MAJOR_SHIFT)
#define GLB_VERSION_MAJOR_MASK ((0xFFU) << GLB_VERSION_MAJOR_SHIFT)
#define GLB_VERSION_MAJOR_GET(reg_val) \
(((reg_val)&GLB_VERSION_MAJOR_MASK) >> GLB_VERSION_MAJOR_SHIFT)
#define GLB_VERSION_MAJOR_SET(reg_val, value) \
@ -311,60 +311,60 @@
(((value) << CS_REQ_EXTRACT_EVENT_SHIFT) & CS_REQ_EXTRACT_EVENT_MASK))
#define CS_REQ_IDLE_SYNC_WAIT_SHIFT 8
#define CS_REQ_IDLE_SYNC_WAIT_MASK (0x1 << CS_REQ_IDLE_SYNC_WAIT_SHIFT)
#define CS_REQ_IDLE_SYNC_WAIT_MASK (0x1U << CS_REQ_IDLE_SYNC_WAIT_SHIFT)
#define CS_REQ_IDLE_SYNC_WAIT_GET(reg_val) \
(((reg_val)&CS_REQ_IDLE_SYNC_WAIT_MASK) >> CS_REQ_IDLE_SYNC_WAIT_SHIFT)
#define CS_REQ_IDLE_SYNC_WAIT_SET(reg_val, value) \
(((reg_val) & ~CS_REQ_IDLE_SYNC_WAIT_MASK) | \
(((value) << CS_REQ_IDLE_SYNC_WAIT_SHIFT) & CS_REQ_IDLE_SYNC_WAIT_MASK))
#define CS_REQ_IDLE_PROTM_PEND_SHIFT 9
#define CS_REQ_IDLE_PROTM_PEND_MASK (0x1 << CS_REQ_IDLE_PROTM_PEND_SHIFT)
#define CS_REQ_IDLE_PROTM_PEND_MASK (0x1U << CS_REQ_IDLE_PROTM_PEND_SHIFT)
#define CS_REQ_IDLE_PROTM_PEND_GET(reg_val) \
(((reg_val)&CS_REQ_IDLE_PROTM_PEND_MASK) >> CS_REQ_IDLE_PROTM_PEND_SHIFT)
#define CS_REQ_IDLE_PROTM_PEND_SET(reg_val, value) \
(((reg_val) & ~CS_REQ_IDLE_PROTM_PEND_MASK) | \
(((value) << CS_REQ_IDLE_PROTM_PEND_SHIFT) & CS_REQ_IDLE_PROTM_PEND_MASK))
#define CS_REQ_IDLE_EMPTY_SHIFT 10
#define CS_REQ_IDLE_EMPTY_MASK (0x1 << CS_REQ_IDLE_EMPTY_SHIFT)
#define CS_REQ_IDLE_EMPTY_MASK (0x1U << CS_REQ_IDLE_EMPTY_SHIFT)
#define CS_REQ_IDLE_EMPTY_GET(reg_val) \
(((reg_val)&CS_REQ_IDLE_EMPTY_MASK) >> CS_REQ_IDLE_EMPTY_SHIFT)
#define CS_REQ_IDLE_EMPTY_SET(reg_val, value) \
(((reg_val) & ~CS_REQ_IDLE_EMPTY_MASK) | \
(((value) << CS_REQ_IDLE_EMPTY_SHIFT) & CS_REQ_IDLE_EMPTY_MASK))
#define CS_REQ_IDLE_RESOURCE_REQ_SHIFT 11
#define CS_REQ_IDLE_RESOURCE_REQ_MASK (0x1 << CS_REQ_IDLE_RESOURCE_REQ_SHIFT)
#define CS_REQ_IDLE_RESOURCE_REQ_MASK (0x1U << CS_REQ_IDLE_RESOURCE_REQ_SHIFT)
#define CS_REQ_IDLE_RESOURCE_REQ_GET(reg_val) \
(((reg_val)&CS_REQ_IDLE_RESOURCE_REQ_MASK) >> CS_REQ_IDLE_RESOURCE_REQ_SHIFT)
#define CS_REQ_IDLE_RESOURCE_REQ_SET(reg_val, value) \
(((reg_val) & ~CS_REQ_IDLE_RESOURCE_REQ_MASK) | \
(((value) << CS_REQ_IDLE_RESOURCE_REQ_SHIFT) & CS_REQ_IDLE_RESOURCE_REQ_MASK))
#define CS_REQ_IDLE_SHARED_SB_DEC_SHIFT 12
#define CS_REQ_IDLE_SHARED_SB_DEC_MASK (0x1 << CS_REQ_IDLE_SHARED_SB_DEC_SHIFT)
#define CS_REQ_IDLE_SHARED_SB_DEC_MASK (0x1U << CS_REQ_IDLE_SHARED_SB_DEC_SHIFT)
#define CS_REQ_IDLE_SHARED_SB_DEC_GET(reg_val) \
(((reg_val)&CS_REQ_IDLE_SHARED_SB_DEC_MASK) >> CS_REQ_IDLE_SHARED_SB_DEC_SHIFT)
#define CS_REQ_IDLE_SHARED_SB_DEC_REQ_SET(reg_val, value) \
(((reg_val) & ~CS_REQ_IDLE_SHARED_SB_DEC_MASK) | \
(((value) << CS_REQ_IDLE_SHARED_SB_DEC_SHIFT) & CS_REQ_IDLE_SHARED_SB_DEC_MASK))
#define CS_REQ_TILER_OOM_SHIFT 26
#define CS_REQ_TILER_OOM_MASK (0x1 << CS_REQ_TILER_OOM_SHIFT)
#define CS_REQ_TILER_OOM_MASK (0x1U << CS_REQ_TILER_OOM_SHIFT)
#define CS_REQ_TILER_OOM_GET(reg_val) (((reg_val)&CS_REQ_TILER_OOM_MASK) >> CS_REQ_TILER_OOM_SHIFT)
#define CS_REQ_TILER_OOM_SET(reg_val, value) \
(((reg_val) & ~CS_REQ_TILER_OOM_MASK) | \
(((value) << CS_REQ_TILER_OOM_SHIFT) & CS_REQ_TILER_OOM_MASK))
#define CS_REQ_PROTM_PEND_SHIFT 27
#define CS_REQ_PROTM_PEND_MASK (0x1 << CS_REQ_PROTM_PEND_SHIFT)
#define CS_REQ_PROTM_PEND_MASK (0x1U << CS_REQ_PROTM_PEND_SHIFT)
#define CS_REQ_PROTM_PEND_GET(reg_val) \
(((reg_val)&CS_REQ_PROTM_PEND_MASK) >> CS_REQ_PROTM_PEND_SHIFT)
#define CS_REQ_PROTM_PEND_SET(reg_val, value) \
(((reg_val) & ~CS_REQ_PROTM_PEND_MASK) | \
(((value) << CS_REQ_PROTM_PEND_SHIFT) & CS_REQ_PROTM_PEND_MASK))
#define CS_REQ_FATAL_SHIFT 30
#define CS_REQ_FATAL_MASK (0x1 << CS_REQ_FATAL_SHIFT)
#define CS_REQ_FATAL_MASK (0x1U << CS_REQ_FATAL_SHIFT)
#define CS_REQ_FATAL_GET(reg_val) (((reg_val)&CS_REQ_FATAL_MASK) >> CS_REQ_FATAL_SHIFT)
#define CS_REQ_FATAL_SET(reg_val, value) \
(((reg_val) & ~CS_REQ_FATAL_MASK) | (((value) << CS_REQ_FATAL_SHIFT) & CS_REQ_FATAL_MASK))
#define CS_REQ_FAULT_SHIFT 31
#define CS_REQ_FAULT_MASK (0x1 << CS_REQ_FAULT_SHIFT)
#define CS_REQ_FAULT_MASK (0x1U << CS_REQ_FAULT_SHIFT)
#define CS_REQ_FAULT_GET(reg_val) (((reg_val)&CS_REQ_FAULT_MASK) >> CS_REQ_FAULT_SHIFT)
#define CS_REQ_FAULT_SET(reg_val, value) \
(((reg_val) & ~CS_REQ_FAULT_MASK) | (((value) << CS_REQ_FAULT_SHIFT) & CS_REQ_FAULT_MASK))
@ -559,32 +559,32 @@
#define CS_ACK_STATE_START 0x1
/* End of CS_ACK_STATE values */
#define CS_ACK_EXTRACT_EVENT_SHIFT 4
#define CS_ACK_EXTRACT_EVENT_MASK (0x1 << CS_ACK_EXTRACT_EVENT_SHIFT)
#define CS_ACK_EXTRACT_EVENT_MASK (0x1U << CS_ACK_EXTRACT_EVENT_SHIFT)
#define CS_ACK_EXTRACT_EVENT_GET(reg_val) \
(((reg_val)&CS_ACK_EXTRACT_EVENT_MASK) >> CS_ACK_EXTRACT_EVENT_SHIFT)
#define CS_ACK_EXTRACT_EVENT_SET(reg_val, value) \
(((reg_val) & ~CS_ACK_EXTRACT_EVENT_MASK) | \
(((value) << CS_ACK_EXTRACT_EVENT_SHIFT) & CS_ACK_EXTRACT_EVENT_MASK))
#define CS_ACK_TILER_OOM_SHIFT 26
#define CS_ACK_TILER_OOM_MASK (0x1 << CS_ACK_TILER_OOM_SHIFT)
#define CS_ACK_TILER_OOM_MASK (0x1U << CS_ACK_TILER_OOM_SHIFT)
#define CS_ACK_TILER_OOM_GET(reg_val) (((reg_val)&CS_ACK_TILER_OOM_MASK) >> CS_ACK_TILER_OOM_SHIFT)
#define CS_ACK_TILER_OOM_SET(reg_val, value) \
(((reg_val) & ~CS_ACK_TILER_OOM_MASK) | \
(((value) << CS_ACK_TILER_OOM_SHIFT) & CS_ACK_TILER_OOM_MASK))
#define CS_ACK_PROTM_PEND_SHIFT 27
#define CS_ACK_PROTM_PEND_MASK (0x1 << CS_ACK_PROTM_PEND_SHIFT)
#define CS_ACK_PROTM_PEND_MASK (0x1U << CS_ACK_PROTM_PEND_SHIFT)
#define CS_ACK_PROTM_PEND_GET(reg_val) \
(((reg_val)&CS_ACK_PROTM_PEND_MASK) >> CS_ACK_PROTM_PEND_SHIFT)
#define CS_ACK_PROTM_PEND_SET(reg_val, value) \
(((reg_val) & ~CS_ACK_PROTM_PEND_MASK) | \
(((value) << CS_ACK_PROTM_PEND_SHIFT) & CS_ACK_PROTM_PEND_MASK))
#define CS_ACK_FATAL_SHIFT 30
#define CS_ACK_FATAL_MASK (0x1 << CS_ACK_FATAL_SHIFT)
#define CS_ACK_FATAL_MASK (0x1U << CS_ACK_FATAL_SHIFT)
#define CS_ACK_FATAL_GET(reg_val) (((reg_val)&CS_ACK_FATAL_MASK) >> CS_ACK_FATAL_SHIFT)
#define CS_ACK_FATAL_SET(reg_val, value) \
(((reg_val) & ~CS_ACK_FATAL_MASK) | (((value) << CS_ACK_FATAL_SHIFT) & CS_ACK_FATAL_MASK))
#define CS_ACK_FAULT_SHIFT 31
#define CS_ACK_FAULT_MASK (0x1 << CS_ACK_FAULT_SHIFT)
#define CS_ACK_FAULT_MASK (0x1U << CS_ACK_FAULT_SHIFT)
#define CS_ACK_FAULT_GET(reg_val) (((reg_val)&CS_ACK_FAULT_MASK) >> CS_ACK_FAULT_SHIFT)
#define CS_ACK_FAULT_SET(reg_val, value) \
(((reg_val) & ~CS_ACK_FAULT_MASK) | (((value) << CS_ACK_FAULT_SHIFT) & CS_ACK_FAULT_MASK))
@ -601,21 +601,21 @@
/* CS_STATUS_WAIT register */
#define CS_STATUS_WAIT_SB_MASK_SHIFT 0
#define CS_STATUS_WAIT_SB_MASK_MASK (0xFFFF << CS_STATUS_WAIT_SB_MASK_SHIFT)
#define CS_STATUS_WAIT_SB_MASK_MASK (0xFFFFU << CS_STATUS_WAIT_SB_MASK_SHIFT)
#define CS_STATUS_WAIT_SB_MASK_GET(reg_val) \
(((reg_val)&CS_STATUS_WAIT_SB_MASK_MASK) >> CS_STATUS_WAIT_SB_MASK_SHIFT)
#define CS_STATUS_WAIT_SB_MASK_SET(reg_val, value) \
(((reg_val) & ~CS_STATUS_WAIT_SB_MASK_MASK) | \
(((value) << CS_STATUS_WAIT_SB_MASK_SHIFT) & CS_STATUS_WAIT_SB_MASK_MASK))
#define CS_STATUS_WAIT_SB_SOURCE_SHIFT 16
#define CS_STATUS_WAIT_SB_SOURCE_MASK (0xF << CS_STATUS_WAIT_SB_SOURCE_SHIFT)
#define CS_STATUS_WAIT_SB_SOURCE_MASK (0xFU << CS_STATUS_WAIT_SB_SOURCE_SHIFT)
#define CS_STATUS_WAIT_SB_SOURCE_GET(reg_val) \
(((reg_val)&CS_STATUS_WAIT_SB_SOURCE_MASK) >> CS_STATUS_WAIT_SB_SOURCE_SHIFT)
#define CS_STATUS_WAIT_SB_SOURCE_SET(reg_val, value) \
(((reg_val) & ~CS_STATUS_WAIT_SB_SOURCE_MASK) | \
(((value) << CS_STATUS_WAIT_SB_SOURCE_SHIFT) & CS_STATUS_WAIT_SB_SOURCE_MASK))
#define CS_STATUS_WAIT_SYNC_WAIT_CONDITION_SHIFT 24
#define CS_STATUS_WAIT_SYNC_WAIT_CONDITION_MASK (0xF << CS_STATUS_WAIT_SYNC_WAIT_CONDITION_SHIFT)
#define CS_STATUS_WAIT_SYNC_WAIT_CONDITION_MASK (0xFU << CS_STATUS_WAIT_SYNC_WAIT_CONDITION_SHIFT)
#define CS_STATUS_WAIT_SYNC_WAIT_CONDITION_GET(reg_val) \
(((reg_val)&CS_STATUS_WAIT_SYNC_WAIT_CONDITION_MASK) >> \
CS_STATUS_WAIT_SYNC_WAIT_CONDITION_SHIFT)
@ -630,28 +630,28 @@
/* End of CS_STATUS_WAIT_SYNC_WAIT_CONDITION values */
/* PROGRESS_WAIT is only for before v14.x.4 */
#define CS_STATUS_WAIT_PROGRESS_WAIT_SHIFT 28
#define CS_STATUS_WAIT_PROGRESS_WAIT_MASK (0x1 << CS_STATUS_WAIT_PROGRESS_WAIT_SHIFT)
#define CS_STATUS_WAIT_PROGRESS_WAIT_MASK (0x1U << CS_STATUS_WAIT_PROGRESS_WAIT_SHIFT)
#define CS_STATUS_WAIT_PROGRESS_WAIT_GET(reg_val) \
(((reg_val)&CS_STATUS_WAIT_PROGRESS_WAIT_MASK) >> CS_STATUS_WAIT_PROGRESS_WAIT_SHIFT)
#define CS_STATUS_WAIT_PROGRESS_WAIT_SET(reg_val, value) \
(((reg_val) & ~CS_STATUS_WAIT_PROGRESS_WAIT_MASK) | \
(((value) << CS_STATUS_WAIT_PROGRESS_WAIT_SHIFT) & CS_STATUS_WAIT_PROGRESS_WAIT_MASK))
#define CS_STATUS_WAIT_PROTM_PEND_SHIFT 29
#define CS_STATUS_WAIT_PROTM_PEND_MASK (0x1 << CS_STATUS_WAIT_PROTM_PEND_SHIFT)
#define CS_STATUS_WAIT_PROTM_PEND_MASK (0x1U << CS_STATUS_WAIT_PROTM_PEND_SHIFT)
#define CS_STATUS_WAIT_PROTM_PEND_GET(reg_val) \
(((reg_val)&CS_STATUS_WAIT_PROTM_PEND_MASK) >> CS_STATUS_WAIT_PROTM_PEND_SHIFT)
#define CS_STATUS_WAIT_PROTM_PEND_SET(reg_val, value) \
(((reg_val) & ~CS_STATUS_WAIT_PROTM_PEND_MASK) | \
(((value) << CS_STATUS_WAIT_PROTM_PEND_SHIFT) & CS_STATUS_WAIT_PROTM_PEND_MASK))
#define CS_STATUS_WAIT_SYNC_WAIT_SIZE_SHIFT 30
#define CS_STATUS_WAIT_SYNC_WAIT_SIZE_MASK (0x1 << CS_STATUS_WAIT_SYNC_WAIT_SIZE_SHIFT)
#define CS_STATUS_WAIT_SYNC_WAIT_SIZE_MASK (0x1U << CS_STATUS_WAIT_SYNC_WAIT_SIZE_SHIFT)
#define CS_STATUS_WAIT_SYNC_WAIT_SIZE_GET(reg_val) \
(((reg_val)&CS_STATUS_WAIT_SYNC_WAIT_SIZE_MASK) >> CS_STATUS_WAIT_SYNC_WAIT_SIZE_SHIFT)
#define CS_STATUS_WAIT_SYNC_WAIT_SIZE_SET(reg_val, value) \
(((reg_val) & ~CS_STATUS_WAIT_SYNC_WAIT_SIZE_MASK) | \
(((value) << CS_STATUS_WAIT_SYNC_WAIT_SIZE_SHIFT) & CS_STATUS_WAIT_SYNC_WAIT_SIZE_MASK))
#define CS_STATUS_WAIT_SYNC_WAIT_SHIFT 31
#define CS_STATUS_WAIT_SYNC_WAIT_MASK (0x1 << CS_STATUS_WAIT_SYNC_WAIT_SHIFT)
#define CS_STATUS_WAIT_SYNC_WAIT_MASK (0x1U << CS_STATUS_WAIT_SYNC_WAIT_SHIFT)
#define CS_STATUS_WAIT_SYNC_WAIT_GET(reg_val) \
(((reg_val)&CS_STATUS_WAIT_SYNC_WAIT_MASK) >> CS_STATUS_WAIT_SYNC_WAIT_SHIFT)
#define CS_STATUS_WAIT_SYNC_WAIT_SET(reg_val, value) \
@ -754,7 +754,7 @@
/* CS_FAULT register */
#define CS_FAULT_EXCEPTION_TYPE_SHIFT 0
#define CS_FAULT_EXCEPTION_TYPE_MASK (0xFF << CS_FAULT_EXCEPTION_TYPE_SHIFT)
#define CS_FAULT_EXCEPTION_TYPE_MASK (0xFFU << CS_FAULT_EXCEPTION_TYPE_SHIFT)
#define CS_FAULT_EXCEPTION_TYPE_GET(reg_val) \
(((reg_val)&CS_FAULT_EXCEPTION_TYPE_MASK) >> CS_FAULT_EXCEPTION_TYPE_SHIFT)
#define CS_FAULT_EXCEPTION_TYPE_SET(reg_val, value) \
@ -796,7 +796,7 @@
#define CS_FAULT_EXCEPTION_TYPE_MEMORY_ATTRIBUTE_FAULT_3 0xEB
/* End of CS_FAULT_EXCEPTION_TYPE values */
#define CS_FAULT_EXCEPTION_DATA_SHIFT 8
#define CS_FAULT_EXCEPTION_DATA_MASK (0xFFFFFF << CS_FAULT_EXCEPTION_DATA_SHIFT)
#define CS_FAULT_EXCEPTION_DATA_MASK (0xFFFFFFU << CS_FAULT_EXCEPTION_DATA_SHIFT)
#define CS_FAULT_EXCEPTION_DATA_GET(reg_val) \
(((reg_val)&CS_FAULT_EXCEPTION_DATA_MASK) >> CS_FAULT_EXCEPTION_DATA_SHIFT)
#define CS_FAULT_EXCEPTION_DATA_SET(reg_val, value) \
@ -821,7 +821,7 @@
#define CS_FATAL_EXCEPTION_TYPE_FIRMWARE_INTERNAL_ERROR 0x68
/* End of CS_FATAL_EXCEPTION_TYPE values */
#define CS_FATAL_EXCEPTION_DATA_SHIFT 8
#define CS_FATAL_EXCEPTION_DATA_MASK (0xFFFFFF << CS_FATAL_EXCEPTION_DATA_SHIFT)
#define CS_FATAL_EXCEPTION_DATA_MASK (0xFFFFFFU << CS_FATAL_EXCEPTION_DATA_SHIFT)
#define CS_FATAL_EXCEPTION_DATA_GET(reg_val) \
(((reg_val)&CS_FATAL_EXCEPTION_DATA_MASK) >> CS_FATAL_EXCEPTION_DATA_SHIFT)
#define CS_FATAL_EXCEPTION_DATA_SET(reg_val, value) \
@ -941,32 +941,32 @@
#define CSG_REQ_STATE_RESUME 0x3
/* End of CSG_REQ_STATE values */
#define CSG_REQ_EP_CFG_SHIFT 4
#define CSG_REQ_EP_CFG_MASK (0x1 << CSG_REQ_EP_CFG_SHIFT)
#define CSG_REQ_EP_CFG_MASK (0x1U << CSG_REQ_EP_CFG_SHIFT)
#define CSG_REQ_EP_CFG_GET(reg_val) (((reg_val)&CSG_REQ_EP_CFG_MASK) >> CSG_REQ_EP_CFG_SHIFT)
#define CSG_REQ_EP_CFG_SET(reg_val, value) \
(((reg_val) & ~CSG_REQ_EP_CFG_MASK) | \
(((value) << CSG_REQ_EP_CFG_SHIFT) & CSG_REQ_EP_CFG_MASK))
#define CSG_REQ_STATUS_UPDATE_SHIFT 5
#define CSG_REQ_STATUS_UPDATE_MASK (0x1 << CSG_REQ_STATUS_UPDATE_SHIFT)
#define CSG_REQ_STATUS_UPDATE_MASK (0x1U << CSG_REQ_STATUS_UPDATE_SHIFT)
#define CSG_REQ_STATUS_UPDATE_GET(reg_val) \
(((reg_val)&CSG_REQ_STATUS_UPDATE_MASK) >> CSG_REQ_STATUS_UPDATE_SHIFT)
#define CSG_REQ_STATUS_UPDATE_SET(reg_val, value) \
(((reg_val) & ~CSG_REQ_STATUS_UPDATE_MASK) | \
(((value) << CSG_REQ_STATUS_UPDATE_SHIFT) & CSG_REQ_STATUS_UPDATE_MASK))
#define CSG_REQ_SYNC_UPDATE_SHIFT 28
#define CSG_REQ_SYNC_UPDATE_MASK (0x1 << CSG_REQ_SYNC_UPDATE_SHIFT)
#define CSG_REQ_SYNC_UPDATE_MASK (0x1U << CSG_REQ_SYNC_UPDATE_SHIFT)
#define CSG_REQ_SYNC_UPDATE_GET(reg_val) \
(((reg_val)&CSG_REQ_SYNC_UPDATE_MASK) >> CSG_REQ_SYNC_UPDATE_SHIFT)
#define CSG_REQ_SYNC_UPDATE_SET(reg_val, value) \
(((reg_val) & ~CSG_REQ_SYNC_UPDATE_MASK) | \
(((value) << CSG_REQ_SYNC_UPDATE_SHIFT) & CSG_REQ_SYNC_UPDATE_MASK))
#define CSG_REQ_IDLE_SHIFT 29
#define CSG_REQ_IDLE_MASK (0x1 << CSG_REQ_IDLE_SHIFT)
#define CSG_REQ_IDLE_MASK (0x1U << CSG_REQ_IDLE_SHIFT)
#define CSG_REQ_IDLE_GET(reg_val) (((reg_val)&CSG_REQ_IDLE_MASK) >> CSG_REQ_IDLE_SHIFT)
#define CSG_REQ_IDLE_SET(reg_val, value) \
(((reg_val) & ~CSG_REQ_IDLE_MASK) | (((value) << CSG_REQ_IDLE_SHIFT) & CSG_REQ_IDLE_MASK))
#define CSG_REQ_PROGRESS_TIMER_EVENT_SHIFT 31
#define CSG_REQ_PROGRESS_TIMER_EVENT_MASK (0x1 << CSG_REQ_PROGRESS_TIMER_EVENT_SHIFT)
#define CSG_REQ_PROGRESS_TIMER_EVENT_MASK (0x1U << CSG_REQ_PROGRESS_TIMER_EVENT_SHIFT)
#define CSG_REQ_PROGRESS_TIMER_EVENT_GET(reg_val) \
(((reg_val)&CSG_REQ_PROGRESS_TIMER_EVENT_MASK) >> CSG_REQ_PROGRESS_TIMER_EVENT_SHIFT)
#define CSG_REQ_PROGRESS_TIMER_EVENT_SET(reg_val, value) \
@ -1133,38 +1133,38 @@
#define CSG_ACK_STATE_RESUME 0x3
/* End of CSG_ACK_STATE values */
#define CSG_ACK_EP_CFG_SHIFT 4
#define CSG_ACK_EP_CFG_MASK (0x1 << CSG_ACK_EP_CFG_SHIFT)
#define CSG_ACK_EP_CFG_MASK (0x1U << CSG_ACK_EP_CFG_SHIFT)
#define CSG_ACK_EP_CFG_GET(reg_val) (((reg_val)&CSG_ACK_EP_CFG_MASK) >> CSG_ACK_EP_CFG_SHIFT)
#define CSG_ACK_EP_CFG_SET(reg_val, value) \
(((reg_val) & ~CSG_ACK_EP_CFG_MASK) | \
(((value) << CSG_ACK_EP_CFG_SHIFT) & CSG_ACK_EP_CFG_MASK))
#define CSG_ACK_STATUS_UPDATE_SHIFT 5
#define CSG_ACK_STATUS_UPDATE_MASK (0x1 << CSG_ACK_STATUS_UPDATE_SHIFT)
#define CSG_ACK_STATUS_UPDATE_MASK (0x1U << CSG_ACK_STATUS_UPDATE_SHIFT)
#define CSG_ACK_STATUS_UPDATE_GET(reg_val) \
(((reg_val)&CSG_ACK_STATUS_UPDATE_MASK) >> CSG_ACK_STATUS_UPDATE_SHIFT)
#define CSG_ACK_STATUS_UPDATE_SET(reg_val, value) \
(((reg_val) & ~CSG_ACK_STATUS_UPDATE_MASK) | \
(((value) << CSG_ACK_STATUS_UPDATE_SHIFT) & CSG_ACK_STATUS_UPDATE_MASK))
#define CSG_ACK_SYNC_UPDATE_SHIFT 28
#define CSG_ACK_SYNC_UPDATE_MASK (0x1 << CSG_ACK_SYNC_UPDATE_SHIFT)
#define CSG_ACK_SYNC_UPDATE_MASK (0x1U << CSG_ACK_SYNC_UPDATE_SHIFT)
#define CSG_ACK_SYNC_UPDATE_GET(reg_val) \
(((reg_val)&CSG_ACK_SYNC_UPDATE_MASK) >> CSG_ACK_SYNC_UPDATE_SHIFT)
#define CSG_ACK_SYNC_UPDATE_SET(reg_val, value) \
(((reg_val) & ~CSG_ACK_SYNC_UPDATE_MASK) | \
(((value) << CSG_ACK_SYNC_UPDATE_SHIFT) & CSG_ACK_SYNC_UPDATE_MASK))
#define CSG_ACK_IDLE_SHIFT 29
#define CSG_ACK_IDLE_MASK (0x1 << CSG_ACK_IDLE_SHIFT)
#define CSG_ACK_IDLE_MASK (0x1U << CSG_ACK_IDLE_SHIFT)
#define CSG_ACK_IDLE_GET(reg_val) (((reg_val)&CSG_ACK_IDLE_MASK) >> CSG_ACK_IDLE_SHIFT)
#define CSG_ACK_IDLE_SET(reg_val, value) \
(((reg_val) & ~CSG_ACK_IDLE_MASK) | (((value) << CSG_ACK_IDLE_SHIFT) & CSG_ACK_IDLE_MASK))
#define CSG_ACK_DOORBELL_SHIFT 30
#define CSG_ACK_DOORBELL_MASK (0x1 << CSG_ACK_DOORBELL_SHIFT)
#define CSG_ACK_DOORBELL_MASK (0x1U << CSG_ACK_DOORBELL_SHIFT)
#define CSG_ACK_DOORBELL_GET(reg_val) (((reg_val)&CSG_ACK_DOORBELL_MASK) >> CSG_ACK_DOORBELL_SHIFT)
#define CSG_ACK_DOORBELL_SET(reg_val, value) \
(((reg_val) & ~CSG_ACK_DOORBELL_MASK) | \
(((value) << CSG_ACK_DOORBELL_SHIFT) & CSG_ACK_DOORBELL_MASK))
#define CSG_ACK_PROGRESS_TIMER_EVENT_SHIFT 31
#define CSG_ACK_PROGRESS_TIMER_EVENT_MASK (0x1 << CSG_ACK_PROGRESS_TIMER_EVENT_SHIFT)
#define CSG_ACK_PROGRESS_TIMER_EVENT_MASK (0x1U << CSG_ACK_PROGRESS_TIMER_EVENT_SHIFT)
#define CSG_ACK_PROGRESS_TIMER_EVENT_GET(reg_val) \
(((reg_val)&CSG_ACK_PROGRESS_TIMER_EVENT_MASK) >> CSG_ACK_PROGRESS_TIMER_EVENT_SHIFT)
#define CSG_ACK_PROGRESS_TIMER_EVENT_SET(reg_val, value) \
@ -1611,8 +1611,8 @@
(((reg_val) & ~GLB_PWROFF_TIMER_TIMER_SOURCE_MASK) | \
(((value) << GLB_PWROFF_TIMER_TIMER_SOURCE_SHIFT) & GLB_PWROFF_TIMER_TIMER_SOURCE_MASK))
/* GLB_PWROFF_TIMER_TIMER_SOURCE values */
#define GLB_PWROFF_TIMER_TIMER_SOURCE_SYSTEM_TIMESTAMP 0x0
#define GLB_PWROFF_TIMER_TIMER_SOURCE_GPU_COUNTER 0x1
#define GLB_PWROFF_TIMER_TIMER_SOURCE_SYSTEM_TIMESTAMP 0x0U
#define GLB_PWROFF_TIMER_TIMER_SOURCE_GPU_COUNTER 0x1U
/* End of GLB_PWROFF_TIMER_TIMER_SOURCE values */
/* GLB_PWROFF_TIMER_CONFIG register */
@ -1695,8 +1695,8 @@
(((reg_val) & ~GLB_IDLE_TIMER_TIMER_SOURCE_MASK) | \
(((value) << GLB_IDLE_TIMER_TIMER_SOURCE_SHIFT) & GLB_IDLE_TIMER_TIMER_SOURCE_MASK))
/* GLB_IDLE_TIMER_TIMER_SOURCE values */
#define GLB_IDLE_TIMER_TIMER_SOURCE_SYSTEM_TIMESTAMP 0x0
#define GLB_IDLE_TIMER_TIMER_SOURCE_GPU_COUNTER 0x1
#define GLB_IDLE_TIMER_TIMER_SOURCE_SYSTEM_TIMESTAMP 0x0U
#define GLB_IDLE_TIMER_TIMER_SOURCE_GPU_COUNTER 0x1U
/* End of GLB_IDLE_TIMER_TIMER_SOURCE values */
/* GLB_IDLE_TIMER_CONFIG values */

18
drivers/gpu/arm/midgard/csf/mali_kbase_csf_reset_gpu.c
View File

@ -240,13 +240,17 @@ static void kbase_csf_debug_dump_registers(struct kbase_device *kbdev)
kbase_reg_read32(kbdev, GPU_CONTROL_ENUM(GPU_IRQ_MASK)),
kbase_reg_read32(kbdev, JOB_CONTROL_ENUM(JOB_IRQ_MASK)),
kbase_reg_read32(kbdev, MMU_CONTROL_ENUM(IRQ_MASK)));
dev_err(kbdev->dev, " PWR_OVERRIDE0=0x%08x PWR_OVERRIDE1=0x%08x",
kbase_reg_read32(kbdev, GPU_CONTROL_ENUM(PWR_OVERRIDE0)),
kbase_reg_read32(kbdev, GPU_CONTROL_ENUM(PWR_OVERRIDE1)));
dev_err(kbdev->dev, " SHADER_CONFIG=0x%08x L2_MMU_CONFIG=0x%08x TILER_CONFIG=0x%08x",
kbase_reg_read32(kbdev, GPU_CONTROL_ENUM(SHADER_CONFIG)),
kbase_reg_read32(kbdev, GPU_CONTROL_ENUM(L2_MMU_CONFIG)),
kbase_reg_read32(kbdev, GPU_CONTROL_ENUM(TILER_CONFIG)));
if (kbdev->gpu_props.gpu_id.arch_id < GPU_ID_ARCH_MAKE(14, 10, 0)) {
dev_err(kbdev->dev, " PWR_OVERRIDE0=0x%08x PWR_OVERRIDE1=0x%08x",
kbase_reg_read32(kbdev, GPU_CONTROL_ENUM(PWR_OVERRIDE0)),
kbase_reg_read32(kbdev, GPU_CONTROL_ENUM(PWR_OVERRIDE1)));
dev_err(kbdev->dev,
" SHADER_CONFIG=0x%08x L2_MMU_CONFIG=0x%08x TILER_CONFIG=0x%08x",
kbase_reg_read32(kbdev, GPU_CONTROL_ENUM(SHADER_CONFIG)),
kbase_reg_read32(kbdev, GPU_CONTROL_ENUM(L2_MMU_CONFIG)),
kbase_reg_read32(kbdev, GPU_CONTROL_ENUM(TILER_CONFIG)));
}
}
/**

347
drivers/gpu/arm/midgard/csf/mali_kbase_csf_scheduler.c
View File

@ -528,7 +528,7 @@ static int wait_for_scheduler_to_exit_sleep(struct kbase_device *kbdev)
/* Usually Scheduler would remain in sleeping state until the
* auto-suspend timer expires and all active CSGs are suspended.
*/
sleep_exit_wait_time = autosuspend_delay + kbdev->reset_timeout_ms;
sleep_exit_wait_time = (u32)autosuspend_delay + kbdev->reset_timeout_ms;
remaining = kbase_csf_timeout_in_jiffies(sleep_exit_wait_time);
@ -680,7 +680,7 @@ static void unassign_user_doorbell_from_queue(struct kbase_device *kbdev, struct
queue->doorbell_nr = KBASEP_USER_DB_NR_INVALID;
/* After this the dummy page would be mapped in */
unmap_mapping_range(kbdev->csf.db_filp->f_inode->i_mapping,
queue->db_file_offset << PAGE_SHIFT, PAGE_SIZE, 1);
(loff_t)(queue->db_file_offset << PAGE_SHIFT), PAGE_SIZE, 1);
}
mutex_unlock(&kbdev->csf.reg_lock);
@ -714,7 +714,7 @@ static void assign_user_doorbell_to_queue(struct kbase_device *kbdev,
/* After this the real Hw doorbell page would be mapped in */
unmap_mapping_range(kbdev->csf.db_filp->f_inode->i_mapping,
queue->db_file_offset << PAGE_SHIFT, PAGE_SIZE, 1);
(loff_t)(queue->db_file_offset << PAGE_SHIFT), PAGE_SIZE, 1);
}
mutex_unlock(&kbdev->csf.reg_lock);
@ -791,44 +791,56 @@ static void enqueue_gpu_idle_work(struct kbase_csf_scheduler *const scheduler)
queue_work(scheduler->idle_wq, &scheduler->gpu_idle_work);
}
void kbase_csf_scheduler_process_gpu_idle_event(struct kbase_device *kbdev)
bool kbase_csf_scheduler_process_gpu_idle_event(struct kbase_device *kbdev)
{
struct kbase_csf_scheduler *scheduler = &kbdev->csf.scheduler;
int non_idle_offslot_grps;
bool can_suspend_on_idle;
bool invoke_pm_state_machine = false;
lockdep_assert_held(&kbdev->hwaccess_lock);
lockdep_assert_held(&scheduler->interrupt_lock);
non_idle_offslot_grps = atomic_read(&scheduler->non_idle_offslot_grps);
can_suspend_on_idle = kbase_pm_idle_groups_sched_suspendable(kbdev);
KBASE_KTRACE_ADD(kbdev, SCHEDULER_GPU_IDLE_EVENT_CAN_SUSPEND, NULL,
((u64)(u32)non_idle_offslot_grps) | (((u64)can_suspend_on_idle) << 32));
(((u64)can_suspend_on_idle) << 32));
if (!non_idle_offslot_grps) {
if (can_suspend_on_idle) {
/* fast_gpu_idle_handling is protected by the
* interrupt_lock, which would prevent this from being
* updated whilst gpu_idle_worker() is executing.
if (can_suspend_on_idle) {
/* fast_gpu_idle_handling is protected by the
* interrupt_lock, which would prevent this from being
* updated whilst gpu_idle_worker() is executing.
*/
scheduler->fast_gpu_idle_handling = (kbdev->csf.gpu_idle_hysteresis_ns == 0) ||
!kbase_csf_scheduler_all_csgs_idle(kbdev);
/* If GPU idle event occurred after the runtime suspend was aborted due to
* DB_MIRROR irq then it suggests that Userspace submission didn't make GPU
* non-idle. So the planned resumption of scheduling can be cancelled and
* MCU can be put back to sleep state to re-trigger the runtime suspend.
*/
if (unlikely(kbdev->pm.backend.exit_gpu_sleep_mode &&
kbdev->pm.backend.runtime_suspend_abort_reason ==
ABORT_REASON_DB_MIRROR_IRQ)) {
/* Cancel the planned resumption of scheduling */
kbdev->pm.backend.exit_gpu_sleep_mode = false;
kbdev->pm.backend.runtime_suspend_abort_reason = ABORT_REASON_NONE;
/* PM state machine can be invoked to put MCU back to the sleep
* state right away and thereby re-trigger the runtime suspend.
*/
scheduler->fast_gpu_idle_handling =
(kbdev->csf.gpu_idle_hysteresis_ns == 0) ||
!kbase_csf_scheduler_all_csgs_idle(kbdev);
/* The GPU idle worker relies on update_on_slot_queues_offsets() to have
* finished. It's queued before to reduce the time it takes till execution
* but it'll eventually be blocked by the scheduler->interrupt_lock.
*/
enqueue_gpu_idle_work(scheduler);
/* The extract offsets are unused in fast GPU idle handling */
if (!scheduler->fast_gpu_idle_handling)
update_on_slot_queues_offsets(kbdev);
invoke_pm_state_machine = true;
}
} else {
/* Invoke the scheduling tick to get the non-idle suspended groups loaded soon */
kbase_csf_scheduler_invoke_tick(kbdev);
/* The GPU idle worker relies on update_on_slot_queues_offsets() to have
* finished. It's queued before to reduce the time it takes till execution
* but it'll eventually be blocked by the scheduler->interrupt_lock.
*/
enqueue_gpu_idle_work(scheduler);
}
/* The extract offsets are unused in fast GPU idle handling */
if (!scheduler->fast_gpu_idle_handling)
update_on_slot_queues_offsets(kbdev);
return invoke_pm_state_machine;
}
u32 kbase_csf_scheduler_get_nr_active_csgs_locked(struct kbase_device *kbdev)
@ -837,8 +849,8 @@ u32 kbase_csf_scheduler_get_nr_active_csgs_locked(struct kbase_device *kbdev)
lockdep_assert_held(&kbdev->csf.scheduler.interrupt_lock);
nr_active_csgs = bitmap_weight(kbdev->csf.scheduler.csg_inuse_bitmap,
kbdev->csf.global_iface.group_num);
nr_active_csgs = (u32)bitmap_weight(kbdev->csf.scheduler.csg_inuse_bitmap,
kbdev->csf.global_iface.group_num);
return nr_active_csgs;
}
@ -938,13 +950,15 @@ static void update_idle_protm_group_state_to_runnable(struct kbase_queue_group *
static bool scheduler_protm_wait_quit(struct kbase_device *kbdev)
{
struct kbase_csf_scheduler *const scheduler = &kbdev->csf.scheduler;
long wt = kbase_csf_timeout_in_jiffies(kbdev->csf.fw_timeout_ms);
const unsigned int fw_timeout_ms = kbase_get_timeout_ms(kbdev, CSF_FIRMWARE_TIMEOUT);
long wt = kbase_csf_timeout_in_jiffies(fw_timeout_ms);
long remaining;
bool success = true;
lockdep_assert_held(&scheduler->lock);
KBASE_KTRACE_ADD(kbdev, SCHEDULER_PROTM_WAIT_QUIT_START, NULL, jiffies_to_msecs(wt));
KBASE_KTRACE_ADD(kbdev, SCHEDULER_PROTM_WAIT_QUIT_START, NULL,
jiffies_to_msecs((unsigned long)wt));
remaining = wait_event_timeout(kbdev->csf.event_wait,
!kbase_csf_scheduler_protected_mode_in_use(kbdev), wt);
@ -954,12 +968,13 @@ static bool scheduler_protm_wait_quit(struct kbase_device *kbdev)
struct kbase_context *kctx = group ? group->kctx : NULL;
dev_warn(kbdev->dev, "[%llu] Timeout (%d ms), protm_quit wait skipped",
kbase_backend_get_cycle_cnt(kbdev), kbdev->csf.fw_timeout_ms);
kbase_backend_get_cycle_cnt(kbdev), fw_timeout_ms);
schedule_actions_trigger_df(kbdev, kctx, DF_PROTECTED_MODE_EXIT_TIMEOUT);
success = false;
}
KBASE_KTRACE_ADD(kbdev, SCHEDULER_PROTM_WAIT_QUIT_END, NULL, jiffies_to_msecs(remaining));
KBASE_KTRACE_ADD(kbdev, SCHEDULER_PROTM_WAIT_QUIT_END, NULL,
jiffies_to_msecs((unsigned long)remaining));
return success;
}
@ -1084,6 +1099,8 @@ static int scheduler_pm_active_after_sleep(struct kbase_device *kbdev, unsigned
if (!WARN_ON(prev_count == U32_MAX))
kbdev->csf.scheduler.pm_active_count++;
kbdev->pm.backend.runtime_suspend_abort_reason = ABORT_REASON_NONE;
/* On 0 => 1, make a pm_ctx_active request */
if (!prev_count) {
spin_unlock_irqrestore(&kbdev->hwaccess_lock, *flags);
@ -1279,8 +1296,9 @@ static void update_idle_suspended_group_state(struct kbase_queue_group *group)
unsigned int n_slots = group->kctx->kbdev->csf.global_iface.group_num;
spin_lock_irqsave(&scheduler->interrupt_lock, flags);
n_idle = bitmap_weight(scheduler->csg_slots_idle_mask, n_slots);
n_used = bitmap_weight(scheduler->csg_inuse_bitmap, n_slots);
n_idle = (unsigned int)bitmap_weight(scheduler->csg_slots_idle_mask,
n_slots);
n_used = (unsigned int)bitmap_weight(scheduler->csg_inuse_bitmap, n_slots);
spin_unlock_irqrestore(&scheduler->interrupt_lock, flags);
if (n_idle || n_used < scheduler->num_csg_slots_for_tick ||
@ -1292,7 +1310,7 @@ static void update_idle_suspended_group_state(struct kbase_queue_group *group)
new_val = atomic_inc_return(&scheduler->non_idle_offslot_grps);
KBASE_KTRACE_ADD_CSF_GRP(group->kctx->kbdev, SCHEDULER_NONIDLE_OFFSLOT_GRP_INC, group,
new_val);
(u64)new_val);
}
int kbase_csf_scheduler_group_get_slot_locked(struct kbase_queue_group *group)
@ -1363,7 +1381,7 @@ bool kbase_csf_scheduler_group_events_enabled(struct kbase_device *kbdev,
}
struct kbase_queue_group *kbase_csf_scheduler_get_group_on_slot(struct kbase_device *kbdev,
int slot)
u32 slot)
{
lockdep_assert_held(&kbdev->csf.scheduler.interrupt_lock);
@ -1378,7 +1396,8 @@ static int halt_stream_sync(struct kbase_queue *queue)
struct kbase_csf_cmd_stream_group_info *ginfo;
struct kbase_csf_cmd_stream_info *stream;
int csi_index = queue->csi_index;
long remaining = kbase_csf_timeout_in_jiffies(kbdev->csf.fw_timeout_ms);
const unsigned int fw_timeout_ms = kbase_get_timeout_ms(kbdev, CSF_FIRMWARE_TIMEOUT);
long remaining = kbase_csf_timeout_in_jiffies(fw_timeout_ms);
unsigned long flags;
if (WARN_ON(!group) || WARN_ON(!kbasep_csf_scheduler_group_is_on_slot_locked(group)))
@ -1399,8 +1418,8 @@ static int halt_stream_sync(struct kbase_queue *queue)
dev_warn(
kbdev->dev,
"[%llu] Timeout (%d ms) waiting for queue to start on csi %d bound to group %d on slot %d",
kbase_backend_get_cycle_cnt(kbdev), kbdev->csf.fw_timeout_ms,
csi_index, group->handle, group->csg_nr);
kbase_backend_get_cycle_cnt(kbdev), fw_timeout_ms, csi_index,
group->handle, group->csg_nr);
if (kbase_prepare_to_reset_gpu(kbdev, RESET_FLAGS_NONE))
kbase_reset_gpu(kbdev);
@ -1408,7 +1427,7 @@ static int halt_stream_sync(struct kbase_queue *queue)
return -ETIMEDOUT;
}
remaining = kbase_csf_timeout_in_jiffies(kbdev->csf.fw_timeout_ms);
remaining = kbase_csf_timeout_in_jiffies(fw_timeout_ms);
}
spin_lock_irqsave(&kbdev->csf.scheduler.interrupt_lock, flags);
@ -1430,8 +1449,8 @@ static int halt_stream_sync(struct kbase_queue *queue)
dev_warn(
kbdev->dev,
"[%llu] Timeout (%d ms) waiting for queue to stop on csi %d bound to group %d on slot %d",
kbase_backend_get_cycle_cnt(kbdev), kbdev->csf.fw_timeout_ms,
queue->csi_index, group->handle, group->csg_nr);
kbase_backend_get_cycle_cnt(kbdev), fw_timeout_ms, queue->csi_index,
group->handle, group->csg_nr);
/* TODO GPUCORE-25328: The CSG can't be terminated, the GPU
* will be reset as a work-around.
@ -1487,6 +1506,7 @@ static int sched_halt_stream(struct kbase_queue *queue)
int slot;
int err = 0;
const u32 group_schedule_timeout = kbase_get_timeout_ms(kbdev, CSF_CSG_SUSPEND_TIMEOUT);
const u32 fw_timeout_ms = kbase_get_timeout_ms(kbdev, CSF_FIRMWARE_TIMEOUT);
if (WARN_ON(!group))
return -EINVAL;
@ -1585,15 +1605,14 @@ retry:
kbdev->csf.event_wait,
(CS_ACK_STATE_GET(kbase_csf_firmware_cs_output(
stream, CS_ACK)) == CS_ACK_STATE_STOP),
kbase_csf_timeout_in_jiffies(kbdev->csf.fw_timeout_ms));
kbase_csf_timeout_in_jiffies(fw_timeout_ms));
if (!remaining) {
dev_warn(
kbdev->dev,
"[%llu] Timeout (%d ms) waiting for queue stop ack on csi %d bound to group %d on slot %d",
kbase_backend_get_cycle_cnt(kbdev),
kbdev->csf.fw_timeout_ms, queue->csi_index,
group->handle, group->csg_nr);
kbase_backend_get_cycle_cnt(kbdev), fw_timeout_ms,
queue->csi_index, group->handle, group->csg_nr);
err = -ETIMEDOUT;
@ -1728,7 +1747,7 @@ static void program_cs_trace_cfg(struct kbase_csf_cmd_stream_info *stream,
* queue's register_ex call.
*/
if (kbase_csf_scheduler_queue_has_trace(queue)) {
u32 cs_cfg = CS_INSTR_CONFIG_JASID_SET(queue->trace_cfg, queue->kctx->as_nr);
u32 cs_cfg = CS_INSTR_CONFIG_JASID_SET(queue->trace_cfg, (u32)queue->kctx->as_nr);
kbase_csf_firmware_cs_input(stream, CS_INSTR_CONFIG, cs_cfg);
kbase_csf_firmware_cs_input(stream, CS_INSTR_BUFFER_SIZE, queue->trace_buffer_size);
@ -1801,7 +1820,7 @@ static void program_cs(struct kbase_device *kbdev, struct kbase_queue *queue,
kbase_csf_firmware_cs_input(stream, CS_USER_OUTPUT_HI, user_output >> 32);
kbase_csf_firmware_cs_input(stream, CS_CONFIG,
(queue->doorbell_nr << 8) | (queue->priority & 0xF));
((u32)queue->doorbell_nr << 8) | (queue->priority & 0xF));
/* Program the queue's cs_trace configuration */
program_cs_trace_cfg(stream, queue);
@ -2039,6 +2058,7 @@ static void halt_csg_slot(struct kbase_queue_group *group, bool suspend)
struct kbase_device *kbdev = group->kctx->kbdev;
struct kbase_csf_global_iface *global_iface = &kbdev->csf.global_iface;
struct kbase_csf_csg_slot *csg_slot = kbdev->csf.scheduler.csg_slots;
const unsigned int fw_timeout_ms = kbase_get_timeout_ms(kbdev, CSF_FIRMWARE_TIMEOUT);
s8 slot;
lockdep_assert_held(&kbdev->csf.scheduler.lock);
@ -2050,15 +2070,14 @@ static void halt_csg_slot(struct kbase_queue_group *group, bool suspend)
/* When in transition, wait for it to complete */
if (atomic_read(&csg_slot[slot].state) == CSG_SLOT_READY2RUN) {
long remaining = kbase_csf_timeout_in_jiffies(kbdev->csf.fw_timeout_ms);
long remaining = kbase_csf_timeout_in_jiffies(fw_timeout_ms);
dev_dbg(kbdev->dev, "slot %d wait for up-running\n", slot);
remaining = wait_event_timeout(kbdev->csf.event_wait, csg_slot_running(kbdev, slot),
remaining);
if (!remaining)
dev_warn(kbdev->dev, "[%llu] slot %d timeout (%d ms) on up-running\n",
kbase_backend_get_cycle_cnt(kbdev), slot,
kbdev->csf.fw_timeout_ms);
kbase_backend_get_cycle_cnt(kbdev), slot, fw_timeout_ms);
}
if (csg_slot_running(kbdev, slot)) {
@ -2079,7 +2098,7 @@ static void halt_csg_slot(struct kbase_queue_group *group, bool suspend)
csg_slot[slot].trigger_jiffies = jiffies;
KBASE_KTRACE_ADD_CSF_GRP(kbdev, CSG_SLOT_STOP_REQ, group, halt_cmd);
KBASE_TLSTREAM_TL_KBASE_DEVICE_HALTING_CSG(kbdev, kbdev->id, slot, suspend);
KBASE_TLSTREAM_TL_KBASE_DEVICE_HALTING_CSG(kbdev, kbdev->id, (u32)slot, suspend);
}
}
@ -2554,7 +2573,8 @@ static void update_offslot_non_idle_cnt(struct kbase_queue_group *group)
if (group->prepared_seq_num < scheduler->non_idle_scanout_grps) {
int new_val = atomic_dec_return(&scheduler->non_idle_offslot_grps);
KBASE_KTRACE_ADD_CSF_GRP(kbdev, SCHEDULER_NONIDLE_OFFSLOT_GRP_DEC, group, new_val);
KBASE_KTRACE_ADD_CSF_GRP(kbdev, SCHEDULER_NONIDLE_OFFSLOT_GRP_DEC, group,
(u64)new_val);
}
}
@ -2569,7 +2589,8 @@ static void update_offslot_non_idle_cnt_for_onslot_grp(struct kbase_queue_group
if (group->prepared_seq_num < scheduler->non_idle_scanout_grps) {
int new_val = atomic_dec_return(&scheduler->non_idle_offslot_grps);
KBASE_KTRACE_ADD_CSF_GRP(kbdev, SCHEDULER_NONIDLE_OFFSLOT_GRP_DEC, group, new_val);
KBASE_KTRACE_ADD_CSF_GRP(kbdev, SCHEDULER_NONIDLE_OFFSLOT_GRP_DEC, group,
(u64)new_val);
}
}
@ -2587,13 +2608,13 @@ static void update_offslot_non_idle_cnt_on_grp_suspend(struct kbase_queue_group
if (group->run_state == KBASE_CSF_GROUP_SUSPENDED) {
int new_val = atomic_inc_return(&scheduler->non_idle_offslot_grps);
KBASE_KTRACE_ADD_CSF_GRP(kbdev, SCHEDULER_NONIDLE_OFFSLOT_GRP_INC,
group, new_val);
group, (u64)new_val);
}
} else {
if (group->run_state != KBASE_CSF_GROUP_SUSPENDED) {
int new_val = atomic_dec_return(&scheduler->non_idle_offslot_grps);
KBASE_KTRACE_ADD_CSF_GRP(kbdev, SCHEDULER_NONIDLE_OFFSLOT_GRP_DEC,
group, new_val);
group, (u64)new_val);
}
}
} else {
@ -2601,7 +2622,7 @@ static void update_offslot_non_idle_cnt_on_grp_suspend(struct kbase_queue_group
if (group->run_state == KBASE_CSF_GROUP_SUSPENDED) {
int new_val = atomic_inc_return(&scheduler->non_idle_offslot_grps);
KBASE_KTRACE_ADD_CSF_GRP(kbdev, SCHEDULER_NONIDLE_OFFSLOT_GRP_INC, group,
new_val);
(u64)new_val);
}
}
}
@ -2796,10 +2817,10 @@ static bool cleanup_csg_slot(struct kbase_queue_group *group)
csg_slot->trigger_jiffies = jiffies;
atomic_set(&csg_slot->state, CSG_SLOT_READY);
KBASE_KTRACE_ADD_CSF_GRP(kbdev, CSG_SLOT_CLEANED, group, slot);
KBASE_KTRACE_ADD_CSF_GRP(kbdev, CSG_SLOT_CLEANED, group, (u64)slot);
dev_dbg(kbdev->dev, "Cleanup done for group %d on slot %d\n", group->handle, slot);
KBASE_TLSTREAM_TL_KBASE_DEVICE_DEPROGRAM_CSG(kbdev, kbdev->id, slot);
KBASE_TLSTREAM_TL_KBASE_DEVICE_DEPROGRAM_CSG(kbdev, kbdev->id, (u32)slot);
/* Notify the group is off-slot and the csg_reg might be available for
* resue with other groups in a 'lazy unbinding' style.
@ -2965,7 +2986,7 @@ static void program_csg_slot(struct kbase_queue_group *group, s8 slot, u8 prio)
kbase_csf_firmware_csg_input(ginfo, CSG_EP_REQ_LO, ep_cfg & U32_MAX);
/* Program the address space number assigned to the context */
kbase_csf_firmware_csg_input(ginfo, CSG_CONFIG, kctx->as_nr);
kbase_csf_firmware_csg_input(ginfo, CSG_CONFIG, (u32)kctx->as_nr);
kbase_csf_firmware_csg_input(ginfo, CSG_SUSPEND_BUF_LO, normal_suspend_buf & U32_MAX);
kbase_csf_firmware_csg_input(ginfo, CSG_SUSPEND_BUF_HI, normal_suspend_buf >> 32);
@ -3012,7 +3033,8 @@ static void program_csg_slot(struct kbase_queue_group *group, s8 slot, u8 prio)
/* Trace the programming of the CSG on the slot */
KBASE_TLSTREAM_TL_KBASE_DEVICE_PROGRAM_CSG(kbdev, kbdev->id, group->kctx->id, group->handle,
slot, (state == CSG_REQ_STATE_RESUME) ? 1 : 0);
(u32)slot,
(state == CSG_REQ_STATE_RESUME) ? 1 : 0);
dev_dbg(kbdev->dev, "Starting group %d of context %d_%d on slot %d with priority %u\n",
group->handle, kctx->tgid, kctx->id, slot, prio);
@ -3063,7 +3085,7 @@ static void sched_evict_group(struct kbase_queue_group *group, bool fault,
group->run_state == KBASE_CSF_GROUP_RUNNABLE)) {
int new_val = atomic_dec_return(&scheduler->non_idle_offslot_grps);
KBASE_KTRACE_ADD_CSF_GRP(kbdev, SCHEDULER_NONIDLE_OFFSLOT_GRP_DEC, group,
new_val);
(u64)new_val);
}
for (i = 0; i < MAX_SUPPORTED_STREAMS_PER_GROUP; i++) {
@ -3109,7 +3131,8 @@ static void sched_evict_group(struct kbase_queue_group *group, bool fault,
static int term_group_sync(struct kbase_queue_group *group)
{
struct kbase_device *kbdev = group->kctx->kbdev;
long remaining = kbase_csf_timeout_in_jiffies(kbdev->csf.fw_timeout_ms);
const unsigned int fw_timeout_ms = kbase_get_timeout_ms(kbdev, CSF_FIRMWARE_TIMEOUT);
long remaining = kbase_csf_timeout_in_jiffies(fw_timeout_ms);
int err = 0;
term_csg_slot(group);
@ -3125,7 +3148,7 @@ static int term_group_sync(struct kbase_queue_group *group)
dev_warn(
kbdev->dev,
"[%llu] term request timeout (%d ms) for group %d of context %d_%d on slot %d",
kbase_backend_get_cycle_cnt(kbdev), kbdev->csf.fw_timeout_ms, group->handle,
kbase_backend_get_cycle_cnt(kbdev), fw_timeout_ms, group->handle,
group->kctx->tgid, group->kctx->id, group->csg_nr);
if (kbase_csf_firmware_ping_wait(kbdev, FW_PING_AFTER_ERROR_TIMEOUT_MS))
error_type = DF_PING_REQUEST_TIMEOUT;
@ -3276,7 +3299,8 @@ static int scheduler_group_schedule(struct kbase_queue_group *group)
insert_group_to_runnable(&kbdev->csf.scheduler, group, KBASE_CSF_GROUP_RUNNABLE);
/* A new group into the scheduler */
new_val = atomic_inc_return(&kbdev->csf.scheduler.non_idle_offslot_grps);
KBASE_KTRACE_ADD_CSF_GRP(kbdev, SCHEDULER_NONIDLE_OFFSLOT_GRP_INC, group, new_val);
KBASE_KTRACE_ADD_CSF_GRP(kbdev, SCHEDULER_NONIDLE_OFFSLOT_GRP_INC, group,
(u64)new_val);
}
/* Since a group has become active now, check if GPU needs to be
@ -3302,7 +3326,8 @@ static inline void set_max_csg_slots(struct kbase_device *kbdev)
{
struct kbase_csf_scheduler *scheduler = &kbdev->csf.scheduler;
unsigned int total_csg_slots = kbdev->csf.global_iface.group_num;
unsigned int max_address_space_slots = kbdev->nr_hw_address_spaces - NUM_RESERVED_AS_SLOTS;
unsigned int max_address_space_slots =
(unsigned int)kbdev->nr_hw_address_spaces - NUM_RESERVED_AS_SLOTS;
WARN_ON(scheduler->num_active_address_spaces > total_csg_slots);
@ -3325,7 +3350,8 @@ static inline void count_active_address_space(struct kbase_device *kbdev,
{
struct kbase_csf_scheduler *scheduler = &kbdev->csf.scheduler;
unsigned int total_csg_slots = kbdev->csf.global_iface.group_num;
unsigned int max_address_space_slots = kbdev->nr_hw_address_spaces - NUM_RESERVED_AS_SLOTS;
unsigned int max_address_space_slots =
(unsigned int)kbdev->nr_hw_address_spaces - NUM_RESERVED_AS_SLOTS;
if (scheduler->ngrp_to_schedule <= total_csg_slots) {
if (kctx->csf.sched.ngrp_to_schedule == 1)
@ -3358,9 +3384,9 @@ static inline void count_active_address_space(struct kbase_device *kbdev,
* priority of a slot belonging to a higher priority idle group will always be
* greater than the priority of a slot belonging to a lower priority non-idle
* group, reflecting the original position of a group in the scan order (i.e
* static priority) 'scan_seq_num', which is set during the prepare phase of a
* tick/tock before the group is moved to 'idle_groups_to_schedule' list if it
* is idle.
* static priority) 'sched_act_seq_num', which is set during the prepare phase
* of a tick/tock before the group is moved to 'idle_groups_to_schedule' list if
* it is idle.
* The priority range [MAX_CSG_SLOT_PRIORITY, 0] is partitioned with the first
* 'slots_for_tick' groups in the original scan order are assigned a priority in
* the subrange [MAX_CSG_SLOT_PRIORITY, MAX_CSG_SLOT_PRIORITY - slots_for_tick),
@ -3385,8 +3411,8 @@ static u8 get_slot_priority(struct kbase_queue_group *group)
slot_prio = (u8)(MAX_CSG_SLOT_PRIORITY - used_slots);
} else {
/* There will be a mix of idle and non-idle groups. */
if (group->scan_seq_num < slots_for_tick)
slot_prio = (u8)(MAX_CSG_SLOT_PRIORITY - group->scan_seq_num);
if (group->sched_act_seq_num < slots_for_tick)
slot_prio = (u8)(MAX_CSG_SLOT_PRIORITY - group->sched_act_seq_num);
else if (MAX_CSG_SLOT_PRIORITY > (slots_for_tick + used_slots))
slot_prio = (u8)(MAX_CSG_SLOT_PRIORITY - (slots_for_tick + used_slots));
else
@ -3644,7 +3670,7 @@ static void program_suspending_csg_slots(struct kbase_device *kbdev)
"[%llu] Group %d of context %d_%d on slot %u failed to suspend (timeout %d ms)",
kbase_backend_get_cycle_cnt(kbdev), group->handle,
group->kctx->tgid, group->kctx->id, i,
kbdev->csf.fw_timeout_ms);
kbase_get_timeout_ms(kbdev, CSF_FIRMWARE_TIMEOUT));
if (kbase_csf_firmware_ping_wait(kbdev,
FW_PING_AFTER_ERROR_TIMEOUT_MS))
error_type = DF_PING_REQUEST_TIMEOUT;
@ -3713,7 +3739,8 @@ static void wait_csg_slots_start(struct kbase_device *kbdev)
{
u32 num_groups = kbdev->csf.global_iface.group_num;
struct kbase_csf_scheduler *scheduler = &kbdev->csf.scheduler;
long remaining = kbase_csf_timeout_in_jiffies(kbdev->csf.fw_timeout_ms);
long remaining =
kbase_csf_timeout_in_jiffies(kbase_get_timeout_ms(kbdev, CSF_FIRMWARE_TIMEOUT));
DECLARE_BITMAP(slot_mask, MAX_SUPPORTED_CSGS) = { 0 };
u32 i;
@ -3753,8 +3780,9 @@ static void wait_csg_slots_start(struct kbase_device *kbdev)
dev_err(kbdev->dev,
"[%llu] Timeout (%d ms) waiting for CSG slots to start, slots: 0x%*pb\n",
kbase_backend_get_cycle_cnt(kbdev), kbdev->csf.fw_timeout_ms,
num_groups, slot_mask);
kbase_backend_get_cycle_cnt(kbdev),
kbase_get_timeout_ms(kbdev, CSF_FIRMWARE_TIMEOUT), num_groups,
slot_mask);
if (kbase_csf_firmware_ping_wait(kbdev, FW_PING_AFTER_ERROR_TIMEOUT_MS))
error_type = DF_PING_REQUEST_TIMEOUT;
schedule_actions_trigger_df(kbdev, group->kctx, error_type);
@ -3884,7 +3912,8 @@ static int wait_csg_slots_handshake_ack(struct kbase_device *kbdev, u32 field_ma
static void wait_csg_slots_finish_prio_update(struct kbase_device *kbdev)
{
unsigned long *slot_mask = kbdev->csf.scheduler.csg_slots_prio_update;
long wait_time = kbase_csf_timeout_in_jiffies(kbdev->csf.fw_timeout_ms);
const unsigned int fw_timeout_ms = kbase_get_timeout_ms(kbdev, CSF_FIRMWARE_TIMEOUT);
long wait_time = kbase_csf_timeout_in_jiffies(fw_timeout_ms);
int ret = wait_csg_slots_handshake_ack(kbdev, CSG_REQ_EP_CFG_MASK, slot_mask, wait_time);
lockdep_assert_held(&kbdev->csf.scheduler.lock);
@ -3898,7 +3927,7 @@ static void wait_csg_slots_finish_prio_update(struct kbase_device *kbdev)
dev_warn(
kbdev->dev,
"[%llu] Timeout (%d ms) on CSG_REQ:EP_CFG, skipping the update wait: slot mask=0x%lx",
kbase_backend_get_cycle_cnt(kbdev), kbdev->csf.fw_timeout_ms, slot_mask[0]);
kbase_backend_get_cycle_cnt(kbdev), fw_timeout_ms, slot_mask[0]);
if (kbase_csf_firmware_ping_wait(kbdev, FW_PING_AFTER_ERROR_TIMEOUT_MS))
error_type = DF_PING_REQUEST_TIMEOUT;
schedule_actions_trigger_df(kbdev, group->kctx, error_type);
@ -4297,6 +4326,34 @@ static void scheduler_apply(struct kbase_device *kbdev)
program_suspending_csg_slots(kbdev);
}
/**
* scheduler_scan_add_group_to_sched_list - Add a schedulable group to one of the scheduler's
* schedulable lists following exactly the scan sequence.
*
* @kbdev: Pointer to the GPU device.
* @sched_list: the scheduling list for appending the given group
* @group: the group that is to be added forllowing the scan out procedure.
*
* This function is called when a group is required to be added to a scheduler maintained list
* for a tick/tock scheduling operation.
*/
static void scheduler_scan_add_group_to_sched_list(struct kbase_device *kbdev,
struct list_head *sched_list,
struct kbase_queue_group *group)
{
struct kbase_csf_scheduler *scheduler = &kbdev->csf.scheduler;
lockdep_assert_held(&scheduler->lock);
lockdep_assert_held(&scheduler->interrupt_lock);
list_add_tail(&group->link_to_schedule, sched_list);
/* Set the act_seq_num when a group is added to a schedulable list.
* Otherwise it's a don't care case, as the group would not be involved
* with onslot running.
*/
group->sched_act_seq_num = scheduler->csg_scan_sched_count++;
}
static void scheduler_ctx_scan_groups(struct kbase_device *kbdev, struct kbase_context *kctx,
int priority, struct list_head *privileged_groups,
struct list_head *active_groups)
@ -4338,17 +4395,17 @@ static void scheduler_ctx_scan_groups(struct kbase_device *kbdev, struct kbase_c
update_idle_protm_group_state_to_runnable(group);
else if (queue_group_idle_locked(group)) {
if (can_schedule_idle_group(group))
list_add_tail(&group->link_to_schedule,
&scheduler->idle_groups_to_schedule);
scheduler_scan_add_group_to_sched_list(
kbdev, &scheduler->idle_groups_to_schedule, group);
continue;
}
if (protm_req && (group->priority == KBASE_QUEUE_GROUP_PRIORITY_REALTIME)) {
list_add_tail(&group->link_to_schedule, privileged_groups);
scheduler_scan_add_group_to_sched_list(kbdev, privileged_groups, group);
continue;
}
list_add_tail(&group->link_to_schedule, active_groups);
scheduler_scan_add_group_to_sched_list(kbdev, active_groups, group);
}
}
@ -4559,7 +4616,9 @@ static void scheduler_update_idle_slots_status(struct kbase_device *kbdev,
/* The groups are aggregated into a single kernel doorbell request */
if (!bitmap_empty(csg_bitmap, num_groups)) {
long wt = kbase_csf_timeout_in_jiffies(kbdev->csf.fw_timeout_ms);
const unsigned int fw_timeout_ms =
kbase_get_timeout_ms(kbdev, CSF_FIRMWARE_TIMEOUT);
long wt = kbase_csf_timeout_in_jiffies(fw_timeout_ms);
u32 db_slots = (u32)csg_bitmap[0];
kbase_csf_ring_csg_slots_doorbell(kbdev, db_slots);
@ -4574,8 +4633,7 @@ static void scheduler_update_idle_slots_status(struct kbase_device *kbdev,
dev_warn(
kbdev->dev,
"[%llu] Timeout (%d ms) on CSG_REQ:STATUS_UPDATE, treat groups as not idle: slot mask=0x%lx",
kbase_backend_get_cycle_cnt(kbdev), kbdev->csf.fw_timeout_ms,
csg_bitmap[0]);
kbase_backend_get_cycle_cnt(kbdev), fw_timeout_ms, csg_bitmap[0]);
schedule_actions_trigger_df(kbdev, group->kctx,
DF_CSG_STATUS_UPDATE_TIMEOUT);
@ -4753,7 +4811,8 @@ static int suspend_active_groups_on_powerdown(struct kbase_device *kbdev, bool s
dev_warn(
kbdev->dev,
"[%llu] Timeout (%d ms) waiting for CSG slots to suspend on power down, slot_mask: 0x%*pb\n",
kbase_backend_get_cycle_cnt(kbdev), kbdev->csf.fw_timeout_ms,
kbase_backend_get_cycle_cnt(kbdev),
kbase_get_timeout_ms(kbdev, CSF_FIRMWARE_TIMEOUT),
kbdev->csf.global_iface.group_num, slot_mask);
if (kbase_csf_firmware_ping_wait(kbdev, FW_PING_AFTER_ERROR_TIMEOUT_MS))
error_type = DF_PING_REQUEST_TIMEOUT;
@ -4843,42 +4902,29 @@ static bool scheduler_idle_suspendable(struct kbase_device *kbdev)
spin_lock_irqsave(&kbdev->hwaccess_lock, flags);
spin_lock(&scheduler->interrupt_lock);
if (scheduler->fast_gpu_idle_handling) {
scheduler->fast_gpu_idle_handling = false;
if (scheduler->total_runnable_grps) {
suspend = !atomic_read(&scheduler->non_idle_offslot_grps) &&
kbase_pm_idle_groups_sched_suspendable(kbdev);
} else
suspend = kbase_pm_no_runnables_sched_suspendable(kbdev);
if (suspend && unlikely(atomic_read(&scheduler->gpu_no_longer_idle)))
suspend = false;
spin_unlock(&scheduler->interrupt_lock);
spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags);
return suspend;
}
if (scheduler->total_runnable_grps) {
/* Check both on-slots and off-slots groups idle status */
suspend = kbase_csf_scheduler_all_csgs_idle(kbdev) &&
suspend = (scheduler->fast_gpu_idle_handling ||
kbase_csf_scheduler_all_csgs_idle(kbdev)) &&
!atomic_read(&scheduler->non_idle_offslot_grps) &&
kbase_pm_idle_groups_sched_suspendable(kbdev);
} else
suspend = kbase_pm_no_runnables_sched_suspendable(kbdev);
if (suspend && unlikely(atomic_read(&scheduler->gpu_no_longer_idle)))
suspend = false;
/* Confirm that all groups are actually idle before proceeding with
* suspension as groups might potentially become active again without
* informing the scheduler in case userspace rings a doorbell directly.
*/
if (suspend && (unlikely(atomic_read(&scheduler->gpu_no_longer_idle)) ||
unlikely(!all_on_slot_groups_remained_idle(kbdev)))) {
if (suspend && !scheduler->fast_gpu_idle_handling &&
unlikely(!all_on_slot_groups_remained_idle(kbdev))) {
dev_dbg(kbdev->dev, "GPU suspension skipped due to active CSGs");
suspend = false;
}
scheduler->fast_gpu_idle_handling = false;
spin_unlock(&scheduler->interrupt_lock);
spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags);
@ -5021,6 +5067,7 @@ static int scheduler_prepare(struct kbase_device *kbdev)
WARN_ON(!list_empty(&scheduler->idle_groups_to_schedule));
scheduler->num_active_address_spaces = 0;
scheduler->num_csg_slots_for_tick = 0;
scheduler->csg_scan_sched_count = 0;
bitmap_zero(scheduler->csg_slots_prio_update, MAX_SUPPORTED_CSGS);
INIT_LIST_HEAD(&privileged_groups);
INIT_LIST_HEAD(&active_groups);
@ -5031,9 +5078,19 @@ static int scheduler_prepare(struct kbase_device *kbdev)
for (i = 0; i < KBASE_QUEUE_GROUP_PRIORITY_COUNT; ++i) {
struct kbase_context *kctx;
list_for_each_entry(kctx, &scheduler->runnable_kctxs, csf.link)
scheduler_ctx_scan_groups(kbdev, kctx, i, &privileged_groups,
&active_groups);
/* Scan the per-priority list of groups twice, firstly for the
* prioritised contexts, then the normal ones.
*/
list_for_each_entry(kctx, &scheduler->runnable_kctxs, csf.link) {
if (atomic_read(&kctx->prioritized))
scheduler_ctx_scan_groups(kbdev, kctx, i, &privileged_groups,
&active_groups);
}
list_for_each_entry(kctx, &scheduler->runnable_kctxs, csf.link) {
if (!atomic_read(&kctx->prioritized))
scheduler_ctx_scan_groups(kbdev, kctx, i, &privileged_groups,
&active_groups);
}
}
spin_unlock_irqrestore(&scheduler->interrupt_lock, flags);
@ -5051,7 +5108,7 @@ static int scheduler_prepare(struct kbase_device *kbdev)
* of the tick. It will be subject to up/downs during the scheduler
* active phase.
*/
atomic_set(&scheduler->non_idle_offslot_grps, scheduler->non_idle_scanout_grps);
atomic_set(&scheduler->non_idle_offslot_grps, (int)scheduler->non_idle_scanout_grps);
KBASE_KTRACE_ADD_CSF_GRP(kbdev, SCHEDULER_NONIDLE_OFFSLOT_GRP_INC, NULL,
scheduler->non_idle_scanout_grps);
@ -5296,7 +5353,7 @@ static void evict_lru_or_blocked_csg(struct kbase_device *kbdev)
}
if (lru_idle_group != NULL) {
unsigned long slot_mask = 1 << lru_idle_group->csg_nr;
unsigned long slot_mask = 1UL << lru_idle_group->csg_nr;
dev_dbg(kbdev->dev, "Suspending LRU idle group %d of context %d_%d on slot %d",
lru_idle_group->handle, lru_idle_group->kctx->tgid,
@ -5310,7 +5367,8 @@ static void evict_lru_or_blocked_csg(struct kbase_device *kbdev)
"[%llu] LRU idle group %d of context %d_%d failed to suspend on slot %d (timeout %d ms)",
kbase_backend_get_cycle_cnt(kbdev), lru_idle_group->handle,
lru_idle_group->kctx->tgid, lru_idle_group->kctx->id,
lru_idle_group->csg_nr, kbdev->csf.fw_timeout_ms);
lru_idle_group->csg_nr,
kbase_get_timeout_ms(kbdev, CSF_FIRMWARE_TIMEOUT));
if (kbase_csf_firmware_ping_wait(kbdev, FW_PING_AFTER_ERROR_TIMEOUT_MS))
error_type = DF_PING_REQUEST_TIMEOUT;
schedule_actions_trigger_df(kbdev, lru_idle_group->kctx, error_type);
@ -5323,7 +5381,6 @@ static void schedule_actions(struct kbase_device *kbdev, bool is_tick)
struct kbase_csf_scheduler *scheduler = &kbdev->csf.scheduler;
unsigned long flags;
struct kbase_queue_group *protm_grp;
int ret;
bool skip_scheduling_actions;
bool skip_idle_slots_update;
bool new_protm_top_grp = false;
@ -5332,8 +5389,7 @@ static void schedule_actions(struct kbase_device *kbdev, bool is_tick)
kbase_reset_gpu_assert_prevented(kbdev);
lockdep_assert_held(&scheduler->lock);
ret = kbase_csf_scheduler_wait_mcu_active(kbdev);
if (ret) {
if (kbase_csf_scheduler_wait_mcu_active(kbdev)) {
dev_err(kbdev->dev, "Wait for MCU power on failed on scheduling tick/tock");
return;
}
@ -5658,7 +5714,8 @@ static int suspend_active_queue_groups_on_reset(struct kbase_device *kbdev)
* case.
*/
kbase_gpu_start_cache_clean(kbdev, GPU_COMMAND_CACHE_CLN_INV_L2_LSC);
ret2 = kbase_gpu_wait_cache_clean_timeout(kbdev, kbdev->mmu_or_gpu_cache_op_wait_time_ms);
ret2 = kbase_gpu_wait_cache_clean_timeout(
kbdev, kbase_get_timeout_ms(kbdev, MMU_AS_INACTIVE_WAIT_TIMEOUT));
if (ret2) {
dev_err(kbdev->dev, "[%llu] Timeout waiting for CACHE_CLN_INV_L2_LSC",
kbase_backend_get_cycle_cnt(kbdev));
@ -5755,7 +5812,8 @@ static bool scheduler_handle_reset_in_protected_mode(struct kbase_device *kbdev)
* anyways.
*/
new_val = atomic_inc_return(&scheduler->non_idle_offslot_grps);
KBASE_KTRACE_ADD_CSF_GRP(kbdev, SCHEDULER_NONIDLE_OFFSLOT_GRP_INC, group, new_val);
KBASE_KTRACE_ADD_CSF_GRP(kbdev, SCHEDULER_NONIDLE_OFFSLOT_GRP_INC, group,
(u64)new_val);
}
unlock:
@ -5898,9 +5956,13 @@ static void firmware_aliveness_monitor(struct work_struct *work)
goto exit;
}
kbase_csf_scheduler_wait_mcu_active(kbdev);
if (kbase_csf_scheduler_wait_mcu_active(kbdev)) {
dev_err(kbdev->dev, "Wait for MCU power on failed at fw aliveness monitor");
goto exit;
}
err = kbase_csf_firmware_ping_wait(kbdev, kbdev->csf.fw_timeout_ms);
err = kbase_csf_firmware_ping_wait(kbdev,
kbase_get_timeout_ms(kbdev, CSF_FIRMWARE_TIMEOUT));
if (err) {
/* It is acceptable to enqueue a reset whilst we've prevented
@ -6414,7 +6476,10 @@ static void check_group_sync_update_worker(struct work_struct *work)
#if IS_ENABLED(CONFIG_DEBUG_FS)
if (unlikely(scheduler->state == SCHED_BUSY)) {
queue_work(kctx->csf.sched.sync_update_wq, &kctx->csf.sched.sync_update_work);
queue_work(atomic_read(&kctx->prioritized) ?
kctx->csf.sched.sync_update_wq_high_prio :
kctx->csf.sched.sync_update_wq_normal_prio,
&kctx->csf.sched.sync_update_work);
mutex_unlock(&scheduler->lock);
return;
}
@ -6457,10 +6522,13 @@ static void check_group_sync_update_worker(struct work_struct *work)
static enum kbase_csf_event_callback_action check_group_sync_update_cb(void *param)
{
struct kbase_context *const kctx = param;
struct workqueue_struct *wq = atomic_read(&kctx->prioritized) ?
kctx->csf.sched.sync_update_wq_high_prio :
kctx->csf.sched.sync_update_wq_normal_prio;
KBASE_KTRACE_ADD(kctx->kbdev, SCHEDULER_GROUP_SYNC_UPDATE_EVENT, kctx, 0u);
queue_work(kctx->csf.sched.sync_update_wq, &kctx->csf.sched.sync_update_work);
queue_work(wq, &kctx->csf.sched.sync_update_work);
return KBASE_CSF_EVENT_CALLBACK_KEEP;
}
@ -6483,12 +6551,22 @@ int kbase_csf_scheduler_context_init(struct kbase_context *kctx)
INIT_LIST_HEAD(&kctx->csf.sched.idle_wait_groups);
kctx->csf.sched.sync_update_wq =
alloc_ordered_workqueue("mali_kbase_csf_sync_update_wq", WQ_HIGHPRI);
if (!kctx->csf.sched.sync_update_wq) {
dev_err(kbdev->dev, "Failed to initialize scheduler context workqueue");
kctx->csf.sched.sync_update_wq_high_prio = alloc_ordered_workqueue(
"mali_sync_wq_%i_high_prio", WQ_UNBOUND | WQ_HIGHPRI, kctx->tgid);
if (kctx->csf.sched.sync_update_wq_high_prio == NULL) {
dev_err(kbdev->dev,
"Failed to initialize scheduler context high-priority workqueue");
err = -ENOMEM;
goto alloc_wq_failed;
goto alloc_high_prio_wq_failed;
}
kctx->csf.sched.sync_update_wq_normal_prio =
alloc_ordered_workqueue("mali_sync_wq_%i_normal_prio", 0, kctx->tgid);
if (kctx->csf.sched.sync_update_wq_normal_prio == NULL) {
dev_err(kbdev->dev,
"Failed to initialize scheduler context normal-priority workqueue");
err = -ENOMEM;
goto alloc_normal_prio_wq_failed;
}
INIT_WORK(&kctx->csf.sched.sync_update_work, check_group_sync_update_worker);
@ -6505,8 +6583,10 @@ int kbase_csf_scheduler_context_init(struct kbase_context *kctx)
return err;
event_wait_add_failed:
destroy_workqueue(kctx->csf.sched.sync_update_wq);
alloc_wq_failed:
destroy_workqueue(kctx->csf.sched.sync_update_wq_normal_prio);
alloc_normal_prio_wq_failed:
destroy_workqueue(kctx->csf.sched.sync_update_wq_high_prio);
alloc_high_prio_wq_failed:
kbase_ctx_sched_remove_ctx(kctx);
#if IS_ENABLED(CONFIG_MALI_TRACE_POWER_GPU_WORK_PERIOD)
gpu_metrics_ctx_term(kctx);
@ -6518,7 +6598,8 @@ void kbase_csf_scheduler_context_term(struct kbase_context *kctx)
{
kbase_csf_event_wait_remove(kctx, check_group_sync_update_cb, kctx);
cancel_work_sync(&kctx->csf.sched.sync_update_work);
destroy_workqueue(kctx->csf.sched.sync_update_wq);
destroy_workqueue(kctx->csf.sched.sync_update_wq_normal_prio);
destroy_workqueue(kctx->csf.sched.sync_update_wq_high_prio);
kbase_ctx_sched_remove_ctx(kctx);
#if IS_ENABLED(CONFIG_MALI_TRACE_POWER_GPU_WORK_PERIOD)
@ -6995,6 +7076,7 @@ int kbase_csf_scheduler_handle_runtime_suspend(struct kbase_device *kbdev)
spin_lock_irqsave(&kbdev->hwaccess_lock, flags);
kbdev->pm.backend.exit_gpu_sleep_mode = true;
kbdev->pm.backend.runtime_suspend_abort_reason = ABORT_REASON_NON_IDLE_CGS;
spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags);
kbase_csf_scheduler_invoke_tick(kbdev);
@ -7060,3 +7142,4 @@ void kbase_csf_scheduler_force_wakeup(struct kbase_device *kbdev)
scheduler_wakeup(kbdev, true);
mutex_unlock(&scheduler->lock);
}
KBASE_EXPORT_TEST_API(kbase_csf_scheduler_force_wakeup);

7
drivers/gpu/arm/midgard/csf/mali_kbase_csf_scheduler.h
View File

@ -122,7 +122,7 @@ bool kbase_csf_scheduler_group_events_enabled(struct kbase_device *kbdev,
* Note: Caller must hold the interrupt_lock.
*/
struct kbase_queue_group *kbase_csf_scheduler_get_group_on_slot(struct kbase_device *kbdev,
int slot);
u32 slot);
/**
* kbase_csf_scheduler_group_deschedule() - Deschedule a GPU command queue
@ -591,8 +591,11 @@ int kbase_csf_scheduler_handle_runtime_suspend(struct kbase_device *kbdev);
* @kbdev: Pointer to the device
*
* This function is called when a GPU idle IRQ has been raised.
*
* Return: true if the PM state machine needs to be invoked after the processing
* of GPU idle irq, otherwise false.
*/
void kbase_csf_scheduler_process_gpu_idle_event(struct kbase_device *kbdev);
bool kbase_csf_scheduler_process_gpu_idle_event(struct kbase_device *kbdev);
/**
* kbase_csf_scheduler_get_nr_active_csgs() - Get the number of active CSGs

4
drivers/gpu/arm/midgard/csf/mali_kbase_csf_sync.c
View File

@ -99,11 +99,7 @@ static void kbasep_csf_sync_print_kcpu_fence_wait_or_signal(char *buffer, int *l
struct kbase_kcpu_command *cmd,
const char *cmd_name)
{
#if (KERNEL_VERSION(4, 10, 0) > LINUX_VERSION_CODE)
struct fence *fence = NULL;
#else
struct dma_fence *fence = NULL;
#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(4, 10, 0) */
struct kbase_kcpu_command_fence_info *fence_info;
struct kbase_sync_fence_info info;
const char *timeline_name = NULL;

4
drivers/gpu/arm/midgard/csf/mali_kbase_csf_tiler_heap.c
View File

@ -225,7 +225,7 @@ static void remove_unlinked_chunk(struct kbase_context *kctx,
* For "no user free count", we check that the count is 1 as it is a shrinkable region;
* no other code part within kbase can take a reference to it.
*/
WARN_ON(atomic_read(&chunk->region->no_user_free_count) > 1);
WARN_ON(atomic64_read(&chunk->region->no_user_free_count) > 1);
kbase_va_region_no_user_free_dec(chunk->region);
#if !defined(CONFIG_MALI_VECTOR_DUMP)
chunk->region->flags &= ~KBASE_REG_DONT_NEED;
@ -308,7 +308,7 @@ static struct kbase_csf_tiler_heap_chunk *alloc_new_chunk(struct kbase_context *
* It should be fine and not a security risk if we let the region leak till
* region tracker termination in such a case.
*/
if (unlikely(atomic_read(&chunk->region->no_user_free_count) > 1)) {
if (unlikely(atomic64_read(&chunk->region->no_user_free_count) > 1)) {
dev_err(kctx->kbdev->dev, "Chunk region has no_user_free_count > 1!\n");
goto unroll_region;
}

20
drivers/gpu/arm/midgard/csf/mali_kbase_csf_tiler_heap_reclaim.c
View File

@ -29,7 +29,7 @@
#define HEAP_SHRINKER_SEEKS (DEFAULT_SEEKS + 2)
/* Tiler heap shrinker batch value */
#define HEAP_SHRINKER_BATCH (512)
#define HEAP_SHRINKER_BATCH (512 / (GPU_PAGES_PER_CPU_PAGE))
/* Tiler heap reclaim scan (free) method size for limiting a scan run length */
#define HEAP_RECLAIM_SCAN_BATCH_SIZE (HEAP_SHRINKER_BATCH << 7)
@ -69,8 +69,8 @@ static void detach_ctx_from_heap_reclaim_mgr(struct kbase_context *kctx)
list_del_init(&info->mgr_link);
if (remaining)
WARN_ON(atomic_sub_return(remaining, &scheduler->reclaim_mgr.unused_pages) <
0);
WARN_ON(atomic_sub_return((int)remaining,
&scheduler->reclaim_mgr.unused_pages) < 0);
dev_dbg(kctx->kbdev->dev,
"Reclaim_mgr_detach: ctx_%d_%d, est_pages=0%u, freed_pages=%u", kctx->tgid,
@ -96,7 +96,7 @@ static void attach_ctx_to_heap_reclaim_mgr(struct kbase_context *kctx)
list_add_tail(&info->mgr_link, &scheduler->reclaim_mgr.ctx_lists[prio]);
/* Accumulate the estimated pages to the manager total field */
atomic_add(info->nr_est_unused_pages, &scheduler->reclaim_mgr.unused_pages);
atomic_add((int)info->nr_est_unused_pages, &scheduler->reclaim_mgr.unused_pages);
dev_dbg(kctx->kbdev->dev, "Reclaim_mgr_attach: ctx_%d_%d, est_count_pages=%u", kctx->tgid,
kctx->id, info->nr_est_unused_pages);
@ -201,8 +201,8 @@ static unsigned long reclaim_unused_heap_pages(struct kbase_device *kbdev)
* headers of the individual chunks and buffer descriptors.
*/
kbase_gpu_start_cache_clean(kbdev, GPU_COMMAND_CACHE_CLN_INV_L2);
if (kbase_gpu_wait_cache_clean_timeout(kbdev,
kbdev->mmu_or_gpu_cache_op_wait_time_ms))
if (kbase_gpu_wait_cache_clean_timeout(
kbdev, kbase_get_timeout_ms(kbdev, MMU_AS_INACTIVE_WAIT_TIMEOUT)))
dev_warn(
kbdev->dev,
"[%llu] Timeout waiting for CACHE_CLN_INV_L2 to complete before Tiler heap reclaim",
@ -241,7 +241,7 @@ static unsigned long reclaim_unused_heap_pages(struct kbase_device *kbdev)
u32 rm_cnt = MIN(info->nr_est_unused_pages - info->nr_freed_pages,
freed_pages);
WARN_ON(atomic_sub_return(rm_cnt, &mgr->unused_pages) < 0);
WARN_ON(atomic_sub_return((int)rm_cnt, &mgr->unused_pages) < 0);
/* tracking the freed pages, before a potential detach call */
info->nr_freed_pages += freed_pages;
@ -278,7 +278,7 @@ static unsigned long kbase_csf_tiler_heap_reclaim_count_free_pages(struct kbase_
struct shrink_control *sc)
{
struct kbase_csf_sched_heap_reclaim_mgr *mgr = &kbdev->csf.scheduler.reclaim_mgr;
unsigned long page_cnt = atomic_read(&mgr->unused_pages);
unsigned long page_cnt = (unsigned long)atomic_read(&mgr->unused_pages);
CSTD_UNUSED(sc);
@ -300,14 +300,14 @@ static unsigned long kbase_csf_tiler_heap_reclaim_scan_free_pages(struct kbase_d
/* Wait for roughly 2-ms */
wait_event_timeout(kbdev->csf.event_wait, (scheduler->state != SCHED_BUSY),
msecs_to_jiffies(2));
(long)msecs_to_jiffies(2));
if (!mutex_trylock(&kbdev->csf.scheduler.lock)) {
dev_dbg(kbdev->dev, "Tiler heap reclaim scan see device busy (freed: 0)");
return 0;
}
}
avail = atomic_read(&mgr->unused_pages);
avail = (unsigned long)atomic_read(&mgr->unused_pages);
if (avail)
freed = reclaim_unused_heap_pages(kbdev);

6
drivers/gpu/arm/midgard/csf/mali_kbase_csf_timeout.c
View File

@ -51,7 +51,7 @@ static int set_timeout(struct kbase_device *const kbdev, u64 const timeout)
dev_dbg(kbdev->dev, "New progress timeout: %llu cycles\n", timeout);
atomic64_set(&kbdev->csf.progress_timeout, timeout);
atomic64_set(&kbdev->csf.progress_timeout, (s64)timeout);
kbase_device_set_timeout(kbdev, CSF_SCHED_PROTM_PROGRESS_TIMEOUT, timeout, 1);
return 0;
@ -112,7 +112,7 @@ static ssize_t progress_timeout_store(struct device *const dev, struct device_at
if (err)
return err;
return count;
return (ssize_t)count;
}
/**
@ -179,5 +179,5 @@ void kbase_csf_timeout_term(struct kbase_device *const kbdev)
u64 kbase_csf_timeout_get(struct kbase_device *const kbdev)
{
return atomic64_read(&kbdev->csf.progress_timeout);
return (u64)atomic64_read(&kbdev->csf.progress_timeout);
}

8
drivers/gpu/arm/midgard/csf/mali_kbase_debug_csf_fault.c
View File

@ -88,8 +88,8 @@ bool kbase_debug_csf_fault_notify(struct kbase_device *kbdev, struct kbase_conte
goto unlock;
}
kbdev->csf.dof.kctx_tgid = kctx ? kctx->tgid : 0;
kbdev->csf.dof.kctx_id = kctx ? kctx->id : 0;
kbdev->csf.dof.kctx_tgid = kctx ? (unsigned int)kctx->tgid : 0U;
kbdev->csf.dof.kctx_id = kctx ? kctx->id : 0U;
kbdev->csf.dof.error_code = error;
kbase_debug_csf_fault_wakeup(kbdev);
@ -142,7 +142,7 @@ static ssize_t debug_csf_fault_read(struct file *file, char __user *buffer, size
spin_unlock_irqrestore(&kbdev->csf.dof.lock, flags);
dev_info(kbdev->dev, "debug csf fault info read");
return simple_read_from_buffer(buffer, size, f_pos, buf, count);
return simple_read_from_buffer(buffer, size, f_pos, buf, (size_t)count);
}
static int debug_csf_fault_open(struct inode *in, struct file *file)
@ -197,7 +197,7 @@ static ssize_t debug_csf_fault_write(struct file *file, const char __user *ubuf,
*/
wake_up(&kbdev->csf.dof.dump_wait_wq);
return count;
return (ssize_t)count;
}
static int debug_csf_fault_release(struct inode *in, struct file *file)

3
drivers/gpu/arm/midgard/debug/backend/mali_kbase_debug_coresight_csf.c
View File

@ -778,7 +778,8 @@ KBASE_EXPORT_TEST_API(kbase_debug_coresight_csf_state_check);
bool kbase_debug_coresight_csf_state_wait(struct kbase_device *kbdev,
enum kbase_debug_coresight_csf_state state)
{
const long wait_timeout = kbase_csf_timeout_in_jiffies(kbdev->csf.fw_timeout_ms);
const long wait_timeout =
kbase_csf_timeout_in_jiffies(kbase_get_timeout_ms(kbdev, CSF_FIRMWARE_TIMEOUT));
struct kbase_debug_coresight_csf_config *config_entry, *next_config_entry;
unsigned long flags;
bool success = true;

28
drivers/gpu/arm/midgard/debug/backend/mali_kbase_debug_ktrace_csf.c
View File

@ -27,8 +27,9 @@
void kbasep_ktrace_backend_format_header(char *buffer, int sz, s32 *written)
{
*written += MAX(
snprintf(buffer + *written, MAX(sz - *written, 0), "group,slot,prio,csi,kcpu"), 0);
*written += MAX(snprintf(buffer + *written, (size_t)MAX(sz - *written, 0),
"group,slot,prio,csi,kcpu"),
0);
}
void kbasep_ktrace_backend_format_msg(struct kbase_ktrace_msg *trace_msg, char *buffer, int sz,
@ -43,38 +44,39 @@ void kbasep_ktrace_backend_format_msg(struct kbase_ktrace_msg *trace_msg, char *
if (be_msg->gpu.flags & KBASE_KTRACE_FLAG_CSF_GROUP) {
const s8 slot = be_msg->gpu.csg_nr;
/* group,slot, */
*written += MAX(snprintf(buffer + *written, MAX(sz - *written, 0), "%u,%d,",
*written += MAX(snprintf(buffer + *written, (size_t)MAX(sz - *written, 0), "%u,%d,",
be_msg->gpu.group_handle, slot),
0);
/* prio */
if (slot >= 0)
*written += MAX(snprintf(buffer + *written, MAX(sz - *written, 0), "%u",
be_msg->gpu.slot_prio),
*written += MAX(snprintf(buffer + *written, (size_t)MAX(sz - *written, 0),
"%u", be_msg->gpu.slot_prio),
0);
/* , */
*written += MAX(snprintf(buffer + *written, MAX(sz - *written, 0), ","), 0);
*written += MAX(snprintf(buffer + *written, (size_t)MAX(sz - *written, 0), ","), 0);
} else {
/* No group,slot,prio fields, but ensure ending with "," */
*written += MAX(snprintf(buffer + *written, MAX(sz - *written, 0), ",,,"), 0);
*written +=
MAX(snprintf(buffer + *written, (size_t)MAX(sz - *written, 0), ",,,"), 0);
}
/* queue parts: csi */
if (trace_msg->backend.gpu.flags & KBASE_KTRACE_FLAG_CSF_QUEUE)
*written += MAX(snprintf(buffer + *written, MAX(sz - *written, 0), "%d",
*written += MAX(snprintf(buffer + *written, (size_t)MAX(sz - *written, 0), "%d",
be_msg->gpu.csi_index),
0);
/* , */
*written += MAX(snprintf(buffer + *written, MAX(sz - *written, 0), ","), 0);
*written += MAX(snprintf(buffer + *written, (size_t)MAX(sz - *written, 0), ","), 0);
if (be_msg->gpu.flags & KBASE_KTRACE_FLAG_CSF_KCPU) {
/* kcpu data */
*written +=
MAX(snprintf(buffer + *written, MAX(sz - *written, 0), "kcpu %d (0x%llx)",
be_msg->kcpu.id, be_msg->kcpu.extra_info_val),
0);
*written += MAX(snprintf(buffer + *written, (size_t)MAX(sz - *written, 0),
"kcpu %d (0x%llx)", be_msg->kcpu.id,
be_msg->kcpu.extra_info_val),
0);
}
/* Don't end with a trailing "," - this is a 'standalone' formatted

2
drivers/gpu/arm/midgard/debug/backend/mali_kbase_debug_ktrace_defs_jm.h
View File

@ -98,7 +98,7 @@ union kbase_ktrace_backend {
* KBASE_KTRACE_FLAG_JM_ATOM
*/
u64 gpu_addr;
int atom_number; /* Only valid for KBASE_KTRACE_FLAG_JM_ATOM */
unsigned int atom_number; /* Only valid for KBASE_KTRACE_FLAG_JM_ATOM */
/* Pack smaller members together */
kbase_ktrace_code_t code;
kbase_ktrace_flag_t flags;

23
drivers/gpu/arm/midgard/debug/backend/mali_kbase_debug_ktrace_jm.c
View File

@ -27,7 +27,7 @@
void kbasep_ktrace_backend_format_header(char *buffer, int sz, s32 *written)
{
*written += MAX(snprintf(buffer + *written, MAX(sz - *written, 0),
*written += MAX(snprintf(buffer + *written, (size_t)MAX(sz - *written, 0),
"katom,gpu_addr,jobslot,refcount"),
0);
}
@ -37,8 +37,8 @@ void kbasep_ktrace_backend_format_msg(struct kbase_ktrace_msg *trace_msg, char *
{
/* katom */
if (trace_msg->backend.gpu.flags & KBASE_KTRACE_FLAG_JM_ATOM)
*written += MAX(snprintf(buffer + *written, MAX(sz - *written, 0),
"atom %d (ud: 0x%llx 0x%llx)",
*written += MAX(snprintf(buffer + *written, (size_t)MAX(sz - *written, 0),
"atom %u (ud: 0x%llx 0x%llx)",
trace_msg->backend.gpu.atom_number,
trace_msg->backend.gpu.atom_udata[0],
trace_msg->backend.gpu.atom_udata[1]),
@ -46,31 +46,32 @@ void kbasep_ktrace_backend_format_msg(struct kbase_ktrace_msg *trace_msg, char *
/* gpu_addr */
if (trace_msg->backend.gpu.flags & KBASE_KTRACE_FLAG_BACKEND)
*written += MAX(snprintf(buffer + *written, MAX(sz - *written, 0), ",%.8llx,",
trace_msg->backend.gpu.gpu_addr),
*written += MAX(snprintf(buffer + *written, (size_t)MAX(sz - *written, 0),
",%.8llx,", trace_msg->backend.gpu.gpu_addr),
0);
else
*written += MAX(snprintf(buffer + *written, MAX(sz - *written, 0), ",,"), 0);
*written +=
MAX(snprintf(buffer + *written, (size_t)MAX(sz - *written, 0), ",,"), 0);
/* jobslot */
if (trace_msg->backend.gpu.flags & KBASE_KTRACE_FLAG_JM_JOBSLOT)
*written += MAX(snprintf(buffer + *written, MAX(sz - *written, 0), "%d",
*written += MAX(snprintf(buffer + *written, (size_t)MAX(sz - *written, 0), "%d",
trace_msg->backend.gpu.jobslot),
0);
*written += MAX(snprintf(buffer + *written, MAX(sz - *written, 0), ","), 0);
*written += MAX(snprintf(buffer + *written, (size_t)MAX(sz - *written, 0), ","), 0);
/* refcount */
if (trace_msg->backend.gpu.flags & KBASE_KTRACE_FLAG_JM_REFCOUNT)
*written += MAX(snprintf(buffer + *written, MAX(sz - *written, 0), "%d",
*written += MAX(snprintf(buffer + *written, (size_t)MAX(sz - *written, 0), "%d",
trace_msg->backend.gpu.refcount),
0);
}
void kbasep_ktrace_add_jm(struct kbase_device *kbdev, enum kbase_ktrace_code code,
struct kbase_context *kctx, const struct kbase_jd_atom *katom,
u64 gpu_addr, kbase_ktrace_flag_t flags, int refcount, int jobslot,
u64 info_val)
u64 gpu_addr, kbase_ktrace_flag_t flags, int refcount,
unsigned int jobslot, u64 info_val)
{
unsigned long irqflags;
struct kbase_ktrace_msg *trace_msg;

12
drivers/gpu/arm/midgard/debug/backend/mali_kbase_debug_ktrace_jm.h
View File

@ -42,8 +42,8 @@
*/
void kbasep_ktrace_add_jm(struct kbase_device *kbdev, enum kbase_ktrace_code code,
struct kbase_context *kctx, const struct kbase_jd_atom *katom,
u64 gpu_addr, kbase_ktrace_flag_t flags, int refcount, int jobslot,
u64 info_val);
u64 gpu_addr, kbase_ktrace_flag_t flags, int refcount,
unsigned int jobslot, u64 info_val);
#define KBASE_KTRACE_RBUF_ADD_JM(kbdev, code, kctx, katom, gpu_addr, flags, refcount, jobslot, \
info_val) \
@ -175,7 +175,7 @@ void kbasep_ktrace_add_jm(struct kbase_device *kbdev, enum kbase_ktrace_code cod
do { \
/* capture values that could come from non-pure function calls */ \
u64 __gpu_addr = gpu_addr; \
int __jobslot = jobslot; \
unsigned int __jobslot = jobslot; \
KBASE_KTRACE_RBUF_ADD_JM(kbdev, code, kctx, katom, __gpu_addr, \
KBASE_KTRACE_FLAG_JM_JOBSLOT, 0, __jobslot, 0); \
KBASE_KTRACE_FTRACE_ADD_JM_SLOT(kbdev, code, kctx, katom, __gpu_addr, __jobslot); \
@ -202,7 +202,7 @@ void kbasep_ktrace_add_jm(struct kbase_device *kbdev, enum kbase_ktrace_code cod
do { \
/* capture values that could come from non-pure function calls */ \
u64 __gpu_addr = gpu_addr; \
int __jobslot = jobslot; \
unsigned int __jobslot = jobslot; \
u64 __info_val = info_val; \
KBASE_KTRACE_RBUF_ADD_JM(kbdev, code, kctx, katom, __gpu_addr, \
KBASE_KTRACE_FLAG_JM_JOBSLOT, 0, __jobslot, __info_val); \
@ -234,7 +234,7 @@ void kbasep_ktrace_add_jm(struct kbase_device *kbdev, enum kbase_ktrace_code cod
KBASE_KTRACE_RBUF_ADD_JM(kbdev, code, kctx, katom, __gpu_addr, \
KBASE_KTRACE_FLAG_JM_REFCOUNT, __refcount, 0, 0u); \
KBASE_KTRACE_FTRACE_ADD_JM_REFCOUNT(kbdev, code, kctx, katom, __gpu_addr, \
__refcount); \
(unsigned int)__refcount); \
} while (0)
/**
@ -265,7 +265,7 @@ void kbasep_ktrace_add_jm(struct kbase_device *kbdev, enum kbase_ktrace_code cod
KBASE_KTRACE_FLAG_JM_REFCOUNT, __refcount, 0, \
__info_val); \
KBASE_KTRACE_FTRACE_ADD_JM_REFCOUNT(kbdev, code, kctx, katom, __gpu_addr, \
__refcount, __info_val); \
(unsigned int)__refcount, __info_val); \
} while (0)
/**

16
drivers/gpu/arm/midgard/debug/backend/mali_kbase_debug_linux_ktrace_jm.h
View File

@ -28,7 +28,7 @@
#define _KBASE_DEBUG_LINUX_KTRACE_JM_H_
DECLARE_EVENT_CLASS(mali_jm_slot_template,
TP_PROTO(struct kbase_context *kctx, int jobslot, u64 info_val),
TP_PROTO(struct kbase_context *kctx, unsigned int jobslot, u64 info_val),
TP_ARGS(kctx, jobslot, info_val),
TP_STRUCT__entry(__field(pid_t, kctx_tgid) __field(u32, kctx_id)
__field(unsigned int, jobslot) __field(u64, info_val)),
@ -38,9 +38,9 @@ DECLARE_EVENT_CLASS(mali_jm_slot_template,
TP_printk("kctx=%d_%u jobslot=%u info=0x%llx", __entry->kctx_tgid,
__entry->kctx_id, __entry->jobslot, __entry->info_val));
#define DEFINE_MALI_JM_SLOT_EVENT(name) \
DEFINE_EVENT(mali_jm_slot_template, mali_##name, \
TP_PROTO(struct kbase_context *kctx, int jobslot, u64 info_val), \
#define DEFINE_MALI_JM_SLOT_EVENT(name) \
DEFINE_EVENT(mali_jm_slot_template, mali_##name, \
TP_PROTO(struct kbase_context *kctx, unsigned int jobslot, u64 info_val), \
TP_ARGS(kctx, jobslot, info_val))
DEFINE_MALI_JM_SLOT_EVENT(JM_RETURN_ATOM_TO_JS);
DEFINE_MALI_JM_SLOT_EVENT(JM_MARK_FOR_RETURN_TO_JS);
@ -78,7 +78,7 @@ DEFINE_MALI_JM_SLOT_EVENT(JS_SLOT_PRIO_IS_BLOCKED);
#undef DEFINE_MALI_JM_SLOT_EVENT
DECLARE_EVENT_CLASS(mali_jm_refcount_template,
TP_PROTO(struct kbase_context *kctx, int refcount, u64 info_val),
TP_PROTO(struct kbase_context *kctx, unsigned int refcount, u64 info_val),
TP_ARGS(kctx, refcount, info_val),
TP_STRUCT__entry(__field(pid_t, kctx_tgid) __field(u32, kctx_id)
__field(unsigned int, refcount)
@ -89,9 +89,9 @@ DECLARE_EVENT_CLASS(mali_jm_refcount_template,
TP_printk("kctx=%d_%u refcount=%u info=0x%llx", __entry->kctx_tgid,
__entry->kctx_id, __entry->refcount, __entry->info_val));
#define DEFINE_MALI_JM_REFCOUNT_EVENT(name) \
DEFINE_EVENT(mali_jm_refcount_template, mali_##name, \
TP_PROTO(struct kbase_context *kctx, int refcount, u64 info_val), \
#define DEFINE_MALI_JM_REFCOUNT_EVENT(name) \
DEFINE_EVENT(mali_jm_refcount_template, mali_##name, \
TP_PROTO(struct kbase_context *kctx, unsigned int refcount, u64 info_val), \
TP_ARGS(kctx, refcount, info_val))
DEFINE_MALI_JM_REFCOUNT_EVENT(JS_ADD_JOB);
DEFINE_MALI_JM_REFCOUNT_EVENT(JS_REMOVE_JOB);

14
drivers/gpu/arm/midgard/debug/mali_kbase_debug_ktrace.c
View File

@ -71,13 +71,13 @@ static const char *const kbasep_ktrace_code_string[] = {
static void kbasep_ktrace_format_header(char *buffer, int sz, s32 written)
{
written += MAX(snprintf(buffer + written, MAX(sz - written, 0),
written += MAX(snprintf(buffer + written, (size_t)MAX(sz - written, 0),
"secs,thread_id,cpu,code,kctx,"),
0);
kbasep_ktrace_backend_format_header(buffer, sz, &written);
written += MAX(snprintf(buffer + written, MAX(sz - written, 0),
written += MAX(snprintf(buffer + written, (size_t)MAX(sz - written, 0),
",info_val,ktrace_version=%u.%u", KBASE_KTRACE_VERSION_MAJOR,
KBASE_KTRACE_VERSION_MINOR),
0);
@ -93,7 +93,7 @@ static void kbasep_ktrace_format_msg(struct kbase_ktrace_msg *trace_msg, char *b
*
* secs,thread_id,cpu,code,
*/
written += MAX(snprintf(buffer + written, MAX(sz - written, 0), "%d.%.6d,%d,%d,%s,",
written += MAX(snprintf(buffer + written, (size_t)MAX(sz - written, 0), "%d.%.6d,%d,%d,%s,",
(int)trace_msg->timestamp.tv_sec,
(int)(trace_msg->timestamp.tv_nsec / 1000), trace_msg->thread_id,
trace_msg->cpu,
@ -102,12 +102,12 @@ static void kbasep_ktrace_format_msg(struct kbase_ktrace_msg *trace_msg, char *b
/* kctx part: */
if (trace_msg->kctx_tgid) {
written += MAX(snprintf(buffer + written, MAX(sz - written, 0), "%d_%u",
written += MAX(snprintf(buffer + written, (size_t)MAX(sz - written, 0), "%d_%u",
trace_msg->kctx_tgid, trace_msg->kctx_id),
0);
}
/* Trailing comma */
written += MAX(snprintf(buffer + written, MAX(sz - written, 0), ","), 0);
written += MAX(snprintf(buffer + written, (size_t)MAX(sz - written, 0), ","), 0);
/* Backend parts */
kbasep_ktrace_backend_format_msg(trace_msg, buffer, sz, &written);
@ -119,7 +119,7 @@ static void kbasep_ktrace_format_msg(struct kbase_ktrace_msg *trace_msg, char *b
* Note that the last column is empty, it's simply to hold the ktrace
* version in the header
*/
written += MAX(snprintf(buffer + written, MAX(sz - written, 0), ",0x%.16llx",
written += MAX(snprintf(buffer + written, (size_t)MAX(sz - written, 0), ",0x%.16llx",
(unsigned long long)trace_msg->info_val),
0);
buffer[sz - 1] = 0;
@ -156,7 +156,7 @@ void kbasep_ktrace_msg_init(struct kbase_ktrace *ktrace, struct kbase_ktrace_msg
{
lockdep_assert_held(&ktrace->lock);
trace_msg->thread_id = task_pid_nr(current);
trace_msg->thread_id = (u32)task_pid_nr(current);
trace_msg->cpu = task_cpu(current);
ktime_get_real_ts64(&trace_msg->timestamp);

6
drivers/gpu/arm/midgard/device/backend/mali_kbase_device_csf.c
View File

@ -87,8 +87,8 @@ static int kbase_backend_late_init(struct kbase_device *kbdev)
#ifdef CONFIG_MALI_DEBUG
#if IS_ENABLED(CONFIG_MALI_REAL_HW)
if (kbasep_common_test_interrupt_handlers(kbdev) != 0) {
dev_err(kbdev->dev, "Interrupt assignment check failed.\n");
if (kbase_validate_interrupts(kbdev) != 0) {
dev_err(kbdev->dev, "Interrupt validation failed.\n");
err = -EINVAL;
goto fail_interrupt_test;
}
@ -278,7 +278,7 @@ static const struct kbase_device_init dev_init[] = {
#if !IS_ENABLED(CONFIG_MALI_REAL_HW)
{ kbase_gpu_device_create, kbase_gpu_device_destroy, "Dummy model initialization failed" },
#else /* !IS_ENABLED(CONFIG_MALI_REAL_HW) */
{ assign_irqs, NULL, "IRQ search failed" },
{ kbase_get_irqs, NULL, "IRQ search failed" },
#endif /* !IS_ENABLED(CONFIG_MALI_REAL_HW) */
#if !IS_ENABLED(CONFIG_MALI_NO_MALI)
{ registers_map, registers_unmap, "Register map failed" },

1
drivers/gpu/arm/midgard/device/backend/mali_kbase_device_hw_csf.c
View File

@ -175,4 +175,5 @@ void kbase_gpu_interrupt(struct kbase_device *kbdev, u32 val)
KBASE_KTRACE_ADD(kbdev, CORE_GPU_IRQ_DONE, NULL, val);
}
KBASE_EXPORT_TEST_API(kbase_gpu_interrupt);

1
drivers/gpu/arm/midgard/device/backend/mali_kbase_device_hw_jm.c
View File

@ -101,3 +101,4 @@ void kbase_gpu_interrupt(struct kbase_device *kbdev, u32 val)
KBASE_KTRACE_ADD(kbdev, CORE_GPU_IRQ_DONE, NULL, val);
}
KBASE_EXPORT_TEST_API(kbase_gpu_interrupt);

6
drivers/gpu/arm/midgard/device/backend/mali_kbase_device_jm.c
View File

@ -75,8 +75,8 @@ static int kbase_backend_late_init(struct kbase_device *kbdev)
#ifdef CONFIG_MALI_DEBUG
#if IS_ENABLED(CONFIG_MALI_REAL_HW)
if (kbasep_common_test_interrupt_handlers(kbdev) != 0) {
dev_err(kbdev->dev, "Interrupt assignment check failed.\n");
if (kbase_validate_interrupts(kbdev) != 0) {
dev_err(kbdev->dev, "Interrupt validation failed.\n");
err = -EINVAL;
goto fail_interrupt_test;
}
@ -216,7 +216,7 @@ static const struct kbase_device_init dev_init[] = {
#if !IS_ENABLED(CONFIG_MALI_REAL_HW)
{ kbase_gpu_device_create, kbase_gpu_device_destroy, "Dummy model initialization failed" },
#else /* !IS_ENABLED(CONFIG_MALI_REAL_HW) */
{ assign_irqs, NULL, "IRQ search failed" },
{ kbase_get_irqs, NULL, "IRQ search failed" },
#endif /* !IS_ENABLED(CONFIG_MALI_REAL_HW) */
#if !IS_ENABLED(CONFIG_MALI_NO_MALI)
{ registers_map, registers_unmap, "Register map failed" },

64
drivers/gpu/arm/midgard/device/mali_kbase_device.c
View File

@ -67,7 +67,7 @@
static DEFINE_MUTEX(kbase_dev_list_lock);
static LIST_HEAD(kbase_dev_list);
static int kbase_dev_nr;
static unsigned int kbase_dev_nr;
struct kbase_device *kbase_device_alloc(void)
{
@ -83,9 +83,10 @@ struct kbase_device *kbase_device_alloc(void)
*/
static int kbase_device_all_as_init(struct kbase_device *kbdev)
{
int i, err = 0;
unsigned int i;
int err = 0;
for (i = 0; i < kbdev->nr_hw_address_spaces; i++) {
for (i = 0; i < (unsigned int)kbdev->nr_hw_address_spaces; i++) {
err = kbase_mmu_as_init(kbdev, i);
if (err)
break;
@ -101,12 +102,39 @@ static int kbase_device_all_as_init(struct kbase_device *kbdev)
static void kbase_device_all_as_term(struct kbase_device *kbdev)
{
int i;
unsigned int i;
for (i = 0; i < kbdev->nr_hw_address_spaces; i++)
for (i = 0; i < (unsigned int)kbdev->nr_hw_address_spaces; i++)
kbase_mmu_as_term(kbdev, i);
}
static int pcm_prioritized_process_cb(struct notifier_block *nb, unsigned long action, void *data)
{
#if MALI_USE_CSF
struct kbase_device *const kbdev =
container_of(nb, struct kbase_device, pcm_prioritized_process_nb);
struct pcm_prioritized_process_notifier_data *const notifier_data = data;
int ret = -EINVAL;
switch (action) {
case ADD_PRIORITIZED_PROCESS:
if (kbasep_adjust_prioritized_process(kbdev, true, notifier_data->pid))
ret = 0;
break;
case REMOVE_PRIORITIZED_PROCESS:
if (kbasep_adjust_prioritized_process(kbdev, false, notifier_data->pid))
ret = 0;
break;
}
return ret;
#endif /* MALI_USE_CSF */
return 0;
}
int kbase_device_pcm_dev_init(struct kbase_device *const kbdev)
{
int err = 0;
@ -140,6 +168,18 @@ int kbase_device_pcm_dev_init(struct kbase_device *const kbdev)
dev_info(kbdev->dev,
"Priority control manager successfully loaded");
kbdev->pcm_dev = pcm_dev;
kbdev->pcm_prioritized_process_nb = (struct notifier_block){
.notifier_call = &pcm_prioritized_process_cb,
};
if (pcm_dev->ops.pcm_prioritized_process_notifier_register !=
NULL) {
if (pcm_dev->ops.pcm_prioritized_process_notifier_register(
pcm_dev, &kbdev->pcm_prioritized_process_nb))
dev_warn(
kbdev->dev,
"Failed to register for changes in prioritized processes");
}
}
}
of_node_put(prio_ctrl_node);
@ -151,8 +191,14 @@ int kbase_device_pcm_dev_init(struct kbase_device *const kbdev)
void kbase_device_pcm_dev_term(struct kbase_device *const kbdev)
{
if (kbdev->pcm_dev)
module_put(kbdev->pcm_dev->owner);
struct priority_control_manager_device *const pcm_dev = kbdev->pcm_dev;
if (pcm_dev) {
if (pcm_dev->ops.pcm_prioritized_process_notifier_unregister != NULL)
pcm_dev->ops.pcm_prioritized_process_notifier_unregister(
pcm_dev, &kbdev->pcm_prioritized_process_nb);
module_put(pcm_dev->owner);
}
}
#define KBASE_PAGES_TO_KIB(pages) (((unsigned int)pages) << (PAGE_SHIFT - 10))
@ -253,7 +299,7 @@ int kbase_device_misc_init(struct kbase_device *const kbdev)
if (err)
goto dma_set_mask_failed;
kbdev->nr_hw_address_spaces = kbdev->gpu_props.num_address_spaces;
kbdev->nr_hw_address_spaces = (s8)kbdev->gpu_props.num_address_spaces;
err = kbase_device_all_as_init(kbdev);
if (err)
@ -276,8 +322,6 @@ int kbase_device_misc_init(struct kbase_device *const kbdev)
#endif /* !MALI_USE_CSF */
kbdev->mmu_mode = kbase_mmu_mode_get_aarch64();
kbdev->mmu_or_gpu_cache_op_wait_time_ms =
kbase_get_timeout_ms(kbdev, MMU_AS_INACTIVE_WAIT_TIMEOUT);
mutex_init(&kbdev->kctx_list_lock);
INIT_LIST_HEAD(&kbdev->kctx_list);

8
drivers/gpu/arm/midgard/device/mali_kbase_device_hw.c
View File

@ -48,7 +48,7 @@ bool kbase_is_gpu_removed(struct kbase_device *kbdev)
static int busy_wait_cache_operation(struct kbase_device *kbdev, u32 irq_bit)
{
const ktime_t wait_loop_start = ktime_get_raw();
const u32 wait_time_ms = kbdev->mmu_or_gpu_cache_op_wait_time_ms;
const u32 wait_time_ms = kbase_get_timeout_ms(kbdev, MMU_AS_INACTIVE_WAIT_TIMEOUT);
bool completed = false;
s64 diff;
u32 irq_bits_to_check = irq_bit;
@ -169,7 +169,7 @@ int kbase_gpu_cache_flush_and_busy_wait(struct kbase_device *kbdev, u32 flush_op
irq_mask & ~CLEAN_CACHES_COMPLETED);
/* busy wait irq status to be enabled */
ret = busy_wait_cache_operation(kbdev, (u32)CLEAN_CACHES_COMPLETED);
ret = busy_wait_cache_operation(kbdev, CLEAN_CACHES_COMPLETED);
if (ret)
return ret;
@ -188,7 +188,7 @@ int kbase_gpu_cache_flush_and_busy_wait(struct kbase_device *kbdev, u32 flush_op
kbase_reg_write32(kbdev, GPU_CONTROL_ENUM(GPU_COMMAND), flush_op);
/* 3. Busy-wait irq status to be enabled. */
ret = busy_wait_cache_operation(kbdev, (u32)CLEAN_CACHES_COMPLETED);
ret = busy_wait_cache_operation(kbdev, CLEAN_CACHES_COMPLETED);
if (ret)
return ret;
@ -301,7 +301,7 @@ void kbase_gpu_wait_cache_clean(struct kbase_device *kbdev)
int kbase_gpu_wait_cache_clean_timeout(struct kbase_device *kbdev, unsigned int wait_timeout_ms)
{
long remaining = msecs_to_jiffies(wait_timeout_ms);
long remaining = (long)msecs_to_jiffies(wait_timeout_ms);
int result = 0;
while (remaining && get_cache_clean_flag(kbdev)) {

16
drivers/gpu/arm/midgard/gpu/backend/mali_kbase_gpu_fault_csf.c
View File

@ -146,28 +146,28 @@ const char *kbase_gpu_exception_name(u32 const exception_code)
e = "ADDRESS_SIZE_FAULT_IN";
break;
case CS_FAULT_EXCEPTION_TYPE_ADDRESS_SIZE_FAULT_OUT_0:
e = "ADDRESS_SIZE_FAULT_OUT_0 at level 0";
e = "ADDRESS_SIZE_FAULT_OUT at level 0";
break;
case CS_FAULT_EXCEPTION_TYPE_ADDRESS_SIZE_FAULT_OUT_1:
e = "ADDRESS_SIZE_FAULT_OUT_1 at level 1";
e = "ADDRESS_SIZE_FAULT_OUT at level 1";
break;
case CS_FAULT_EXCEPTION_TYPE_ADDRESS_SIZE_FAULT_OUT_2:
e = "ADDRESS_SIZE_FAULT_OUT_2 at level 2";
e = "ADDRESS_SIZE_FAULT_OUT at level 2";
break;
case CS_FAULT_EXCEPTION_TYPE_ADDRESS_SIZE_FAULT_OUT_3:
e = "ADDRESS_SIZE_FAULT_OUT_3 at level 3";
e = "ADDRESS_SIZE_FAULT_OUT at level 3";
break;
case CS_FAULT_EXCEPTION_TYPE_MEMORY_ATTRIBUTE_FAULT_0:
e = "MEMORY_ATTRIBUTE_FAULT_0 at level 0";
e = "MEMORY_ATTRIBUTE_FAULT at level 0";
break;
case CS_FAULT_EXCEPTION_TYPE_MEMORY_ATTRIBUTE_FAULT_1:
e = "MEMORY_ATTRIBUTE_FAULT_1 at level 1";
e = "MEMORY_ATTRIBUTE_FAULT at level 1";
break;
case CS_FAULT_EXCEPTION_TYPE_MEMORY_ATTRIBUTE_FAULT_2:
e = "MEMORY_ATTRIBUTE_FAULT_2 at level 2";
e = "MEMORY_ATTRIBUTE_FAULT at level 2";
break;
case CS_FAULT_EXCEPTION_TYPE_MEMORY_ATTRIBUTE_FAULT_3:
e = "MEMORY_ATTRIBUTE_FAULT_3 at level 3";
e = "MEMORY_ATTRIBUTE_FAULT at level 3";
break;
/* Any other exception code is unknown */
default:

35
drivers/gpu/arm/midgard/hw_access/mali_kbase_hw_access.h
View File

@ -22,6 +22,8 @@
#ifndef _MALI_KBASE_HW_ACCESS_H_
#define _MALI_KBASE_HW_ACCESS_H_
#include <linux/version_compat_defs.h>
#define KBASE_REGMAP_PERM_READ (1U << 0)
#define KBASE_REGMAP_PERM_WRITE (1U << 1)
#define KBASE_REGMAP_WIDTH_32_BIT (1U << 2)
@ -186,4 +188,37 @@ u32 kbase_regmap_backend_init(struct kbase_device *kbdev);
*/
void kbase_regmap_term(struct kbase_device *kbdev);
/**
* kbase_reg_poll32_timeout - Poll a 32 bit register with timeout
* @kbdev: Kbase device pointer
* @reg_enum: Register enum
* @val: Variable for result of read
* @cond: Condition to be met
* @delay_us: Delay between each poll (in uS)
* @timeout_us: Timeout (in uS)
* @delay_before_read: If true delay for @delay_us before read
*
* Return: 0 if condition is met, -ETIMEDOUT if timed out.
*/
#define kbase_reg_poll32_timeout(kbdev, reg_enum, val, cond, delay_us, timeout_us, \
delay_before_read) \
read_poll_timeout_atomic(kbase_reg_read32, val, cond, delay_us, timeout_us, \
delay_before_read, kbdev, reg_enum)
/**
* kbase_reg_poll64_timeout - Poll a 64 bit register with timeout
* @kbdev: Kbase device pointer
* @reg_enum: Register enum
* @val: Variable for result of read
* @cond: Condition to be met
* @delay_us: Delay between each poll (in uS)
* @timeout_us: Timeout (in uS)
* @delay_before_read: If true delay for @delay_us before read
*
* Return: 0 if condition is met, -ETIMEDOUT if timed out.
*/
#define kbase_reg_poll64_timeout(kbdev, reg_enum, val, cond, delay_us, timeout_us, \
delay_before_read) \
read_poll_timeout_atomic(kbase_reg_read64, val, cond, delay_us, timeout_us, \
delay_before_read, kbdev, reg_enum)
#endif /* _MALI_KBASE_HW_ACCESS_H_ */

24
drivers/gpu/arm/midgard/hw_access/mali_kbase_hw_access_regmap.h
View File

@ -290,10 +290,10 @@
/* THREAD_* registers */
/* THREAD_FEATURES IMPLEMENTATION_TECHNOLOGY values */
#define THREAD_FEATURES_IMPLEMENTATION_TECHNOLOGY_NOT_SPECIFIED 0
#define THREAD_FEATURES_IMPLEMENTATION_TECHNOLOGY_SILICON 1
#define THREAD_FEATURES_IMPLEMENTATION_TECHNOLOGY_FPGA 2
#define THREAD_FEATURES_IMPLEMENTATION_TECHNOLOGY_SOFTWARE 3
#define THREAD_FEATURES_IMPLEMENTATION_TECHNOLOGY_NOT_SPECIFIED 0U
#define THREAD_FEATURES_IMPLEMENTATION_TECHNOLOGY_SILICON 1U
#define THREAD_FEATURES_IMPLEMENTATION_TECHNOLOGY_FPGA 2U
#define THREAD_FEATURES_IMPLEMENTATION_TECHNOLOGY_SOFTWARE 3U
/* End THREAD_* registers */
@ -430,7 +430,7 @@
/* SYSC_ALLOC register */
#define SYSC_ALLOC_R_SYSC_ALLOC0_SHIFT (0)
#define SYSC_ALLOC_R_SYSC_ALLOC0_MASK ((0xF) << SYSC_ALLOC_R_SYSC_ALLOC0_SHIFT)
#define SYSC_ALLOC_R_SYSC_ALLOC0_MASK ((0xFU) << SYSC_ALLOC_R_SYSC_ALLOC0_SHIFT)
#define SYSC_ALLOC_R_SYSC_ALLOC0_GET(reg_val) \
(((reg_val)&SYSC_ALLOC_R_SYSC_ALLOC0_MASK) >> SYSC_ALLOC_R_SYSC_ALLOC0_SHIFT)
#define SYSC_ALLOC_R_SYSC_ALLOC0_SET(reg_val, value) \
@ -438,7 +438,7 @@
(((value) << SYSC_ALLOC_R_SYSC_ALLOC0_SHIFT) & SYSC_ALLOC_R_SYSC_ALLOC0_MASK))
/* End of SYSC_ALLOC_R_SYSC_ALLOC0 values */
#define SYSC_ALLOC_W_SYSC_ALLOC0_SHIFT (4)
#define SYSC_ALLOC_W_SYSC_ALLOC0_MASK ((0xF) << SYSC_ALLOC_W_SYSC_ALLOC0_SHIFT)
#define SYSC_ALLOC_W_SYSC_ALLOC0_MASK ((0xFU) << SYSC_ALLOC_W_SYSC_ALLOC0_SHIFT)
#define SYSC_ALLOC_W_SYSC_ALLOC0_GET(reg_val) \
(((reg_val)&SYSC_ALLOC_W_SYSC_ALLOC0_MASK) >> SYSC_ALLOC_W_SYSC_ALLOC0_SHIFT)
#define SYSC_ALLOC_W_SYSC_ALLOC0_SET(reg_val, value) \
@ -446,7 +446,7 @@
(((value) << SYSC_ALLOC_W_SYSC_ALLOC0_SHIFT) & SYSC_ALLOC_W_SYSC_ALLOC0_MASK))
/* End of SYSC_ALLOC_W_SYSC_ALLOC0 values */
#define SYSC_ALLOC_R_SYSC_ALLOC1_SHIFT (8)
#define SYSC_ALLOC_R_SYSC_ALLOC1_MASK ((0xF) << SYSC_ALLOC_R_SYSC_ALLOC1_SHIFT)
#define SYSC_ALLOC_R_SYSC_ALLOC1_MASK ((0xFU) << SYSC_ALLOC_R_SYSC_ALLOC1_SHIFT)
#define SYSC_ALLOC_R_SYSC_ALLOC1_GET(reg_val) \
(((reg_val)&SYSC_ALLOC_R_SYSC_ALLOC1_MASK) >> SYSC_ALLOC_R_SYSC_ALLOC1_SHIFT)
#define SYSC_ALLOC_R_SYSC_ALLOC1_SET(reg_val, value) \
@ -454,7 +454,7 @@
(((value) << SYSC_ALLOC_R_SYSC_ALLOC1_SHIFT) & SYSC_ALLOC_R_SYSC_ALLOC1_MASK))
/* End of SYSC_ALLOC_R_SYSC_ALLOC1 values */
#define SYSC_ALLOC_W_SYSC_ALLOC1_SHIFT (12)
#define SYSC_ALLOC_W_SYSC_ALLOC1_MASK ((0xF) << SYSC_ALLOC_W_SYSC_ALLOC1_SHIFT)
#define SYSC_ALLOC_W_SYSC_ALLOC1_MASK ((0xFU) << SYSC_ALLOC_W_SYSC_ALLOC1_SHIFT)
#define SYSC_ALLOC_W_SYSC_ALLOC1_GET(reg_val) \
(((reg_val)&SYSC_ALLOC_W_SYSC_ALLOC1_MASK) >> SYSC_ALLOC_W_SYSC_ALLOC1_SHIFT)
#define SYSC_ALLOC_W_SYSC_ALLOC1_SET(reg_val, value) \
@ -462,7 +462,7 @@
(((value) << SYSC_ALLOC_W_SYSC_ALLOC1_SHIFT) & SYSC_ALLOC_W_SYSC_ALLOC1_MASK))
/* End of SYSC_ALLOC_W_SYSC_ALLOC1 values */
#define SYSC_ALLOC_R_SYSC_ALLOC2_SHIFT (16)
#define SYSC_ALLOC_R_SYSC_ALLOC2_MASK ((0xF) << SYSC_ALLOC_R_SYSC_ALLOC2_SHIFT)
#define SYSC_ALLOC_R_SYSC_ALLOC2_MASK ((0xFU) << SYSC_ALLOC_R_SYSC_ALLOC2_SHIFT)
#define SYSC_ALLOC_R_SYSC_ALLOC2_GET(reg_val) \
(((reg_val)&SYSC_ALLOC_R_SYSC_ALLOC2_MASK) >> SYSC_ALLOC_R_SYSC_ALLOC2_SHIFT)
#define SYSC_ALLOC_R_SYSC_ALLOC2_SET(reg_val, value) \
@ -470,7 +470,7 @@
(((value) << SYSC_ALLOC_R_SYSC_ALLOC2_SHIFT) & SYSC_ALLOC_R_SYSC_ALLOC2_MASK))
/* End of SYSC_ALLOC_R_SYSC_ALLOC2 values */
#define SYSC_ALLOC_W_SYSC_ALLOC2_SHIFT (20)
#define SYSC_ALLOC_W_SYSC_ALLOC2_MASK ((0xF) << SYSC_ALLOC_W_SYSC_ALLOC2_SHIFT)
#define SYSC_ALLOC_W_SYSC_ALLOC2_MASK ((0xFU) << SYSC_ALLOC_W_SYSC_ALLOC2_SHIFT)
#define SYSC_ALLOC_W_SYSC_ALLOC2_GET(reg_val) \
(((reg_val)&SYSC_ALLOC_W_SYSC_ALLOC2_MASK) >> SYSC_ALLOC_W_SYSC_ALLOC2_SHIFT)
#define SYSC_ALLOC_W_SYSC_ALLOC2_SET(reg_val, value) \
@ -478,7 +478,7 @@
(((value) << SYSC_ALLOC_W_SYSC_ALLOC2_SHIFT) & SYSC_ALLOC_W_SYSC_ALLOC2_MASK))
/* End of SYSC_ALLOC_W_SYSC_ALLOC2 values */
#define SYSC_ALLOC_R_SYSC_ALLOC3_SHIFT (24)
#define SYSC_ALLOC_R_SYSC_ALLOC3_MASK ((0xF) << SYSC_ALLOC_R_SYSC_ALLOC3_SHIFT)
#define SYSC_ALLOC_R_SYSC_ALLOC3_MASK ((0xFU) << SYSC_ALLOC_R_SYSC_ALLOC3_SHIFT)
#define SYSC_ALLOC_R_SYSC_ALLOC3_GET(reg_val) \
(((reg_val)&SYSC_ALLOC_R_SYSC_ALLOC3_MASK) >> SYSC_ALLOC_R_SYSC_ALLOC3_SHIFT)
#define SYSC_ALLOC_R_SYSC_ALLOC3_SET(reg_val, value) \
@ -486,7 +486,7 @@
(((value) << SYSC_ALLOC_R_SYSC_ALLOC3_SHIFT) & SYSC_ALLOC_R_SYSC_ALLOC3_MASK))
/* End of SYSC_ALLOC_R_SYSC_ALLOC3 values */
#define SYSC_ALLOC_W_SYSC_ALLOC3_SHIFT (28)
#define SYSC_ALLOC_W_SYSC_ALLOC3_MASK ((0xF) << SYSC_ALLOC_W_SYSC_ALLOC3_SHIFT)
#define SYSC_ALLOC_W_SYSC_ALLOC3_MASK ((0xFU) << SYSC_ALLOC_W_SYSC_ALLOC3_SHIFT)
#define SYSC_ALLOC_W_SYSC_ALLOC3_GET(reg_val) \
(((reg_val)&SYSC_ALLOC_W_SYSC_ALLOC3_MASK) >> SYSC_ALLOC_W_SYSC_ALLOC3_SHIFT)
#define SYSC_ALLOC_W_SYSC_ALLOC3_SET(reg_val, value) \

23
drivers/gpu/arm/midgard/hw_access/regmap/mali_kbase_regmap_csf_macros.h
View File

@ -69,6 +69,7 @@
ENUM_OFFSET(n, DOORBELL_BLOCK_ENUM(0, regname), DOORBELL_BLOCK_ENUM(1, regname))
/* register value macros */
/* L2_CONFIG PBHA values */
#define L2_CONFIG_PBHA_HWU_SHIFT GPU_U(12)
#define L2_CONFIG_PBHA_HWU_MASK (GPU_U(0xF) << L2_CONFIG_PBHA_HWU_SHIFT)
@ -79,7 +80,8 @@
(((value) << L2_CONFIG_PBHA_HWU_SHIFT) & L2_CONFIG_PBHA_HWU_MASK))
#define PRFCNT_FEATURES_COUNTER_BLOCK_SIZE_SHIFT (0)
#define PRFCNT_FEATURES_COUNTER_BLOCK_SIZE_MASK ((0xFF) << PRFCNT_FEATURES_COUNTER_BLOCK_SIZE_SHIFT)
#define PRFCNT_FEATURES_COUNTER_BLOCK_SIZE_MASK \
((0xFFU) << PRFCNT_FEATURES_COUNTER_BLOCK_SIZE_SHIFT)
#define PRFCNT_FEATURES_COUNTER_BLOCK_SIZE_GET(reg_val) \
(((reg_val)&PRFCNT_FEATURES_COUNTER_BLOCK_SIZE_MASK) >> \
PRFCNT_FEATURES_COUNTER_BLOCK_SIZE_SHIFT)
@ -401,16 +403,17 @@
(((value) << GPU_FAULTSTATUS_ADDRESS_VALID_SHIFT) & GPU_FAULTSTATUS_ADDRESS_VALID_MASK))
/* GPU IRQ flags */
#define GPU_FAULT (1 << 0) /* A GPU Fault has occurred */
#define GPU_PROTECTED_FAULT (1 << 1) /* A GPU fault has occurred in protected mode */
#define RESET_COMPLETED (1 << 8) /* Set when a reset has completed. */
#define POWER_CHANGED_SINGLE (1 << 9) /* Set when a single core has finished powering up or down. */
#define POWER_CHANGED_ALL (1 << 10) /* Set when all cores have finished powering up or down. */
#define CLEAN_CACHES_COMPLETED (1 << 17) /* Set when a cache clean operation has completed. */
#define DOORBELL_MIRROR (1 << 18) /* Mirrors the doorbell interrupt line to the CPU */
#define MCU_STATUS_GPU_IRQ (1 << 19) /* MCU requires attention */
#define GPU_FAULT (1U << 0) /* A GPU Fault has occurred */
#define GPU_PROTECTED_FAULT (1U << 1) /* A GPU fault has occurred in protected mode */
#define RESET_COMPLETED (1U << 8) /* Set when a reset has completed. */
#define POWER_CHANGED_SINGLE \
(1U << 9) /* Set when a single core has finished powering up or down. */
#define POWER_CHANGED_ALL (1U << 10) /* Set when all cores have finished powering up or down. */
#define CLEAN_CACHES_COMPLETED (1U << 17) /* Set when a cache clean operation has completed. */
#define DOORBELL_MIRROR (1U << 18) /* Mirrors the doorbell interrupt line to the CPU */
#define MCU_STATUS_GPU_IRQ (1U << 19) /* MCU requires attention */
#define FLUSH_PA_RANGE_COMPLETED \
(1 << 20) /* Set when a physical range cache clean operation has completed. */
(1U << 20) /* Set when a physical range cache clean operation has completed. */
/* GPU_FEATURES register */

15
drivers/gpu/arm/midgard/hw_access/regmap/mali_kbase_regmap_jm_macros.h
View File

@ -269,13 +269,14 @@
#define GPU_COMMAND_FLUSH_CACHE_MERGE(cmd1, cmd2) ((cmd1) > (cmd2) ? (cmd1) : (cmd2))
/* IRQ flags */
#define GPU_FAULT (1 << 0) /* A GPU Fault has occurred */
#define MULTIPLE_GPU_FAULTS (1 << 7) /* More than one GPU Fault occurred. */
#define RESET_COMPLETED (1 << 8) /* Set when a reset has completed. */
#define POWER_CHANGED_SINGLE (1 << 9) /* Set when a single core has finished powering up or down. */
#define POWER_CHANGED_ALL (1 << 10) /* Set when all cores have finished powering up or down. */
#define PRFCNT_SAMPLE_COMPLETED (1 << 16) /* Set when a performance count sample has completed. */
#define CLEAN_CACHES_COMPLETED (1 << 17) /* Set when a cache clean operation has completed. */
#define GPU_FAULT (1U << 0) /* A GPU Fault has occurred */
#define MULTIPLE_GPU_FAULTS (1U << 7) /* More than one GPU Fault occurred. */
#define RESET_COMPLETED (1U << 8) /* Set when a reset has completed. */
#define POWER_CHANGED_SINGLE \
(1U << 9) /* Set when a single core has finished powering up or down. */
#define POWER_CHANGED_ALL (1U << 10) /* Set when all cores have finished powering up or down. */
#define PRFCNT_SAMPLE_COMPLETED (1U << 16) /* Set when a performance count sample has completed. */
#define CLEAN_CACHES_COMPLETED (1U << 17) /* Set when a cache clean operation has completed. */
#define FLUSH_PA_RANGE_COMPLETED \
(1 << 20) /* Set when a physical range cache clean operation has completed. */

57
drivers/gpu/arm/midgard/hwcnt/backend/mali_kbase_hwcnt_backend_csf.c
View File

@ -44,6 +44,9 @@
#define HWCNT_BACKEND_WATCHDOG_TIMER_INTERVAL_MS ((u32)1000)
#endif /* IS_FPGA && !NO_MALI */
/* Used to check for a sample in which all counters in the block are disabled */
#define HWCNT_BLOCK_EMPTY_SAMPLE (2)
/**
* enum kbase_hwcnt_backend_csf_dump_state - HWC CSF backend dumping states.
*
@ -339,8 +342,7 @@ kbasep_hwcnt_backend_csf_cc_initial_sample(struct kbase_hwcnt_backend_csf *backe
backend_csf->info->csf_if->get_gpu_cycle_count(backend_csf->info->csf_if->ctx, cycle_counts,
clk_enable_map);
kbase_hwcnt_metadata_for_each_clock(enable_map->metadata, clk)
{
kbase_hwcnt_metadata_for_each_clock(enable_map->metadata, clk) {
if (kbase_hwcnt_clk_enable_map_enabled(clk_enable_map, clk))
backend_csf->prev_cycle_count[clk] = cycle_counts[clk];
}
@ -361,8 +363,7 @@ static void kbasep_hwcnt_backend_csf_cc_update(struct kbase_hwcnt_backend_csf *b
backend_csf->info->csf_if->get_gpu_cycle_count(backend_csf->info->csf_if->ctx, cycle_counts,
backend_csf->clk_enable_map);
kbase_hwcnt_metadata_for_each_clock(backend_csf->info->metadata, clk)
{
kbase_hwcnt_metadata_for_each_clock(backend_csf->info->metadata, clk) {
if (kbase_hwcnt_clk_enable_map_enabled(backend_csf->clk_enable_map, clk)) {
backend_csf->cycle_count_elapsed[clk] =
cycle_counts[clk] - backend_csf->prev_cycle_count[clk];
@ -384,34 +385,28 @@ static u64 kbasep_hwcnt_backend_csf_timestamp_ns(struct kbase_hwcnt_backend *bac
/** kbasep_hwcnt_backend_csf_process_enable_map() - Process the enable_map to
* guarantee headers are
* enabled if any counter is
* required.
* enabled.
*@phys_enable_map: HWC physical enable map to be processed.
*/
static void
kbasep_hwcnt_backend_csf_process_enable_map(struct kbase_hwcnt_physical_enable_map *phys_enable_map)
void kbasep_hwcnt_backend_csf_process_enable_map(
struct kbase_hwcnt_physical_enable_map *phys_enable_map)
{
WARN_ON(!phys_enable_map);
/* Enable header if any counter is required from user, the header is
* controlled by bit 0 of the enable mask.
/* Unconditionally enable each block header and first counter,
* the header is controlled by bit 0 of the enable mask.
*/
phys_enable_map->fe_bm |= 1;
phys_enable_map->fe_bm |= 3;
if (phys_enable_map->tiler_bm)
phys_enable_map->tiler_bm |= 1;
phys_enable_map->tiler_bm |= 3;
if (phys_enable_map->mmu_l2_bm)
phys_enable_map->mmu_l2_bm |= 1;
phys_enable_map->mmu_l2_bm |= 3;
if (phys_enable_map->shader_bm)
phys_enable_map->shader_bm |= 1;
phys_enable_map->shader_bm |= 3;
if (phys_enable_map->fw_bm)
phys_enable_map->fw_bm |= 1;
phys_enable_map->fw_bm |= 3;
if (phys_enable_map->csg_bm)
phys_enable_map->csg_bm |= 1;
phys_enable_map->csg_bm |= 3;
}
@ -429,7 +424,7 @@ static void kbasep_hwcnt_backend_csf_init_layout(
WARN_ON(!prfcnt_info);
WARN_ON(!phys_layout);
shader_core_cnt = fls64(prfcnt_info->core_mask);
shader_core_cnt = (size_t)fls64(prfcnt_info->core_mask);
values_per_block = prfcnt_info->prfcnt_block_size / KBASE_HWCNT_VALUE_HW_BYTES;
fw_block_cnt = div_u64(prfcnt_info->prfcnt_fw_size, prfcnt_info->prfcnt_block_size);
hw_block_cnt = div_u64(prfcnt_info->prfcnt_hw_size, prfcnt_info->prfcnt_block_size);
@ -542,7 +537,8 @@ static void kbasep_hwcnt_backend_csf_update_block_state(
size_t block_idx, blk_stt_t *const block_state, bool fw_in_protected_mode)
{
/* Offset of shader core blocks from the start of the HW blocks in the sample */
size_t shader_core_block_offset = phys_layout->hw_block_cnt - phys_layout->shader_cnt;
size_t shader_core_block_offset =
(size_t)(phys_layout->hw_block_cnt - phys_layout->shader_cnt);
bool is_shader_core_block;
is_shader_core_block = block_idx >= shader_core_block_offset;
@ -608,17 +604,17 @@ static void kbasep_hwcnt_backend_csf_accumulate_sample(
const u32 *old_block = old_sample_buf;
const u32 *new_block = new_sample_buf;
u64 *acc_block = accum_buf;
/* Flag to indicate whether current sample is when exiting protected mode. */
/* Flag to indicate whether current sample is exiting protected mode. */
bool exiting_protm = false;
const size_t values_per_block = phys_layout->values_per_block;
/* The block pointers now point to the first HW block, which is always a CSHW/front-end
* block. The counter enable mask for this block can be checked to determine whether this
* sample is taken after leaving protected mode - this is the only scenario where the CSHW
* block counter enable mask is all-zero. In this case, the values in this sample would not
* be meaningful, so they don't need to be accumulated.
* block counter enable mask has only the first bit set, and no others. In this case,
* the values in this sample would not be meaningful, so they don't need to be accumulated.
*/
exiting_protm = !new_block[phys_layout->enable_mask_offset];
exiting_protm = (new_block[phys_layout->enable_mask_offset] == 1);
for (block_idx = 0; block_idx < phys_layout->block_cnt; block_idx++) {
const u32 old_enable_mask = old_block[phys_layout->enable_mask_offset];
@ -629,7 +625,7 @@ static void kbasep_hwcnt_backend_csf_accumulate_sample(
&block_states[block_idx],
fw_in_protected_mode);
if (new_enable_mask == 0) {
if (!(new_enable_mask & HWCNT_BLOCK_EMPTY_SAMPLE)) {
/* Hardware block was unavailable or we didn't turn on
* any counters. Do nothing.
*/
@ -662,7 +658,7 @@ static void kbasep_hwcnt_backend_csf_accumulate_sample(
* saturating at their maximum value.
*/
if (!clearing_samples) {
if (old_enable_mask == 0) {
if (!(old_enable_mask & HWCNT_BLOCK_EMPTY_SAMPLE)) {
/* Block was previously
* unavailable. Accumulate the new
* counters only, as we know previous
@ -1444,8 +1440,7 @@ static int kbasep_hwcnt_backend_csf_dump_get(struct kbase_hwcnt_backend *backend
return -EINVAL;
/* Extract elapsed cycle count for each clock domain if enabled. */
kbase_hwcnt_metadata_for_each_clock(dst_enable_map->metadata, clk)
{
kbase_hwcnt_metadata_for_each_clock(dst_enable_map->metadata, clk) {
if (!kbase_hwcnt_clk_enable_map_enabled(dst_enable_map->clk_enable_map, clk))
continue;

11
drivers/gpu/arm/midgard/hwcnt/backend/mali_kbase_hwcnt_backend_csf.h
View File

@ -31,6 +31,8 @@
#include "hwcnt/backend/mali_kbase_hwcnt_backend_csf_if.h"
#include "hwcnt/mali_kbase_hwcnt_watchdog_if.h"
struct kbase_hwcnt_physical_enable_map;
/**
* kbase_hwcnt_backend_csf_create() - Create a CSF hardware counter backend
* interface.
@ -127,6 +129,15 @@ void kbase_hwcnt_backend_csf_set_hw_availability(struct kbase_hwcnt_backend_inte
size_t num_l2_slices,
uint64_t shader_present_bitmap);
/** kbasep_hwcnt_backend_csf_process_enable_map() - Process the enable_map to
* guarantee headers are
* enabled if any counter is
* required.
* @phys_enable_map: HWC physical enable map to be processed.
*/
void kbasep_hwcnt_backend_csf_process_enable_map(
struct kbase_hwcnt_physical_enable_map *phys_enable_map);
/**
* kbase_hwcnt_backend_csf_on_prfcnt_sample() - CSF performance counter sample
* complete interrupt handler.

6
drivers/gpu/arm/midgard/hwcnt/backend/mali_kbase_hwcnt_backend_csf_if_fw.c
View File

@ -536,7 +536,7 @@ kbasep_hwcnt_backend_csf_if_fw_dump_enable(struct kbase_hwcnt_backend_csf_if_ctx
(struct kbase_hwcnt_backend_csf_if_fw_ctx *)ctx;
struct kbase_hwcnt_backend_csf_if_fw_ring_buf *fw_ring_buf =
(struct kbase_hwcnt_backend_csf_if_fw_ring_buf *)ring_buf;
u32 max_csg_slots;
u32 csg_mask;
WARN_ON(!ctx);
WARN_ON(!ring_buf);
@ -545,7 +545,7 @@ kbasep_hwcnt_backend_csf_if_fw_dump_enable(struct kbase_hwcnt_backend_csf_if_ctx
kbdev = fw_ctx->kbdev;
global_iface = &kbdev->csf.global_iface;
max_csg_slots = kbdev->csf.global_iface.group_num;
csg_mask = (1 << kbdev->csf.global_iface.group_num) - 1;
/* Configure */
prfcnt_config = GLB_PRFCNT_CONFIG_SIZE_SET(0, fw_ring_buf->buf_count);
@ -570,7 +570,7 @@ kbasep_hwcnt_backend_csf_if_fw_dump_enable(struct kbase_hwcnt_backend_csf_if_ctx
kbase_csf_firmware_global_input(global_iface, GLB_PRFCNT_CSG_EN, enable->csg_bm);
/* Enable all of the CSGs by default. */
kbase_csf_firmware_global_input(global_iface, GLB_PRFCNT_CSG_SELECT, max_csg_slots);
kbase_csf_firmware_global_input(global_iface, GLB_PRFCNT_CSG_SELECT, csg_mask);
/* Configure the HWC set and buffer size */

101
drivers/gpu/arm/midgard/hwcnt/backend/mali_kbase_hwcnt_backend_jm.c
View File

@ -80,34 +80,40 @@ struct kbase_hwcnt_jm_physical_layout {
/**
* struct kbase_hwcnt_backend_jm - Instance of a JM hardware counter backend.
* @info: Info used to create the backend.
* @kctx: KBase context used for GPU memory allocation and
* counter dumping.
* @gpu_dump_va: GPU hardware counter dump buffer virtual address.
* @cpu_dump_va: CPU mapping of gpu_dump_va.
* @vmap: Dump buffer vmap.
* @to_user_buf: HWC sample buffer for client user, size
* metadata.dump_buf_bytes.
* @enabled: True if dumping has been enabled, else false.
* @accum_all_blk_stt: Block State to accumulate on next sample, for all types
* of block.
* @info: Info used to create the backend.
* @kctx: KBase context used for GPU memory allocation and
* counter dumping.
* @gpu_dump_va: GPU hardware counter dump buffer virtual address.
* @cpu_dump_va: CPU mapping of gpu_dump_va.
* @vmap: Dump buffer vmap.
* @to_user_buf: HWC sample buffer for client user, size
* metadata.dump_buf_bytes.
* @enabled: True if dumping has been enabled, else false.
* @accum_all_blk_stt: Block State to accumulate on next sample, for all types
* of block.
* @sampled_all_blk_stt: Block State to accumulate into the current sample, for
* all types of block.
* @pm_core_mask: PM state sync-ed shaders core mask for the enabled
* dumping.
* @curr_config: Current allocated hardware resources to correctly map the
* source raw dump buffer to the destination dump buffer.
* @clk_enable_map: The enable map specifying enabled clock domains.
* @cycle_count_elapsed:
* Cycle count elapsed for a given sample period.
* The top clock cycle, index 0, is read directly from
* hardware, but the other clock domains need to be
* calculated with software estimation.
* @prev_cycle_count: Previous cycle count to calculate the cycle count for
* sample period.
* @rate_listener: Clock rate listener callback state.
* @ccswe_shader_cores: Shader cores cycle count software estimator.
* @phys_layout: Physical memory layout information of HWC sample buffer.
* @debug_core_mask: User-set mask of shader cores that can be used.
* @pm_core_mask: PM state sync-ed shaders core mask for the enabled
* dumping.
* @curr_config: Current allocated hardware resources to correctly map the
* source raw dump buffer to the destination dump buffer.
* @max_core_mask: Core mask of all cores allocated to the GPU (non
* virtualized platforms) or resource group (virtualized
* platforms).
* @max_l2_slices: Maximum number of L2 slices allocated to the GPU (non
* virtualized platforms) or resource group (virtualized
* platforms).
* @clk_enable_map: The enable map specifying enabled clock domains.
* @cycle_count_elapsed: Cycle count elapsed for a given sample period.
* The top clock cycle, index 0, is read directly from
* hardware, but the other clock domains need to be
* calculated with software estimation.
* @prev_cycle_count: Previous cycle count to calculate the cycle count for
* sample period.
* @rate_listener: Clock rate listener callback state.
* @ccswe_shader_cores: Shader cores cycle count software estimator.
* @phys_layout: Physical memory layout information of HWC sample buffer.
*/
struct kbase_hwcnt_backend_jm {
const struct kbase_hwcnt_backend_jm_info *info;
@ -119,8 +125,11 @@ struct kbase_hwcnt_backend_jm {
bool enabled;
blk_stt_t accum_all_blk_stt;
blk_stt_t sampled_all_blk_stt;
u64 debug_core_mask;
u64 pm_core_mask;
struct kbase_hwcnt_curr_config curr_config;
u64 max_core_mask;
size_t max_l2_slices;
u64 clk_enable_map;
u64 cycle_count_elapsed[BASE_MAX_NR_CLOCKS_REGULATORS];
u64 prev_cycle_count[BASE_MAX_NR_CLOCKS_REGULATORS];
@ -355,9 +364,9 @@ kbasep_hwcnt_backend_jm_dump_enable_nolock(struct kbase_hwcnt_backend *backend,
struct kbase_hwcnt_backend_jm *backend_jm = (struct kbase_hwcnt_backend_jm *)backend;
struct kbase_context *kctx;
struct kbase_device *kbdev;
struct kbase_hwcnt_physical_enable_map phys_enable_map;
struct kbase_hwcnt_physical_enable_map phys_enable_map = { 0 };
enum kbase_hwcnt_physical_set phys_counter_set;
struct kbase_instr_hwcnt_enable enable;
struct kbase_instr_hwcnt_enable enable = { 0 };
u64 timestamp_ns;
if (!backend_jm || !enable_map || backend_jm->enabled ||
@ -373,18 +382,21 @@ kbasep_hwcnt_backend_jm_dump_enable_nolock(struct kbase_hwcnt_backend *backend,
kbase_hwcnt_gpu_set_to_physical(&phys_counter_set, backend_jm->info->counter_set);
enable.fe_bm = phys_enable_map.fe_bm;
enable.shader_bm = phys_enable_map.shader_bm;
enable.tiler_bm = phys_enable_map.tiler_bm;
enable.mmu_l2_bm = phys_enable_map.mmu_l2_bm;
enable.counter_set = phys_counter_set;
enable = (struct kbase_instr_hwcnt_enable)
{
.fe_bm = phys_enable_map.fe_bm,
.shader_bm = phys_enable_map.shader_bm,
.tiler_bm = phys_enable_map.tiler_bm,
.mmu_l2_bm = phys_enable_map.mmu_l2_bm,
.counter_set = phys_counter_set,
#if IS_ENABLED(CONFIG_MALI_NO_MALI)
/* The dummy model needs the CPU mapping. */
enable.dump_buffer = (uintptr_t)backend_jm->cpu_dump_va;
/* The dummy model needs the CPU mapping. */
.dump_buffer = (uintptr_t)backend_jm->cpu_dump_va,
#else
enable.dump_buffer = backend_jm->gpu_dump_va;
.dump_buffer = backend_jm->gpu_dump_va,
#endif /* CONFIG_MALI_NO_MALI */
enable.dump_buffer_bytes = backend_jm->info->dump_bytes;
.dump_buffer_bytes = backend_jm->info->dump_bytes,
};
timestamp_ns = kbasep_hwcnt_backend_jm_timestamp_ns(backend);
@ -397,6 +409,10 @@ kbasep_hwcnt_backend_jm_dump_enable_nolock(struct kbase_hwcnt_backend *backend,
if (errcode)
goto error;
backend_jm->debug_core_mask = kbase_pm_ca_get_debug_core_mask(kbdev);
backend_jm->max_l2_slices = backend_jm->info->hwcnt_gpu_info.l2_count;
backend_jm->max_core_mask = backend_jm->info->hwcnt_gpu_info.core_mask;
backend_jm->pm_core_mask = kbase_pm_ca_get_instr_core_mask(kbdev);
backend_jm->enabled = true;
@ -537,8 +553,7 @@ static int kbasep_hwcnt_backend_jm_dump_request(struct kbase_hwcnt_backend *back
*dump_time_ns = kbasep_hwcnt_backend_jm_timestamp_ns(backend);
ret = kbase_instr_hwcnt_request_dump(backend_jm->kctx);
kbase_hwcnt_metadata_for_each_clock(metadata, clk)
{
kbase_hwcnt_metadata_for_each_clock(metadata, clk) {
if (!kbase_hwcnt_clk_enable_map_enabled(backend_jm->clk_enable_map, clk))
continue;
@ -620,8 +635,7 @@ static int kbasep_hwcnt_backend_jm_dump_get(struct kbase_hwcnt_backend *backend,
kbasep_hwcnt_backend_jm_dump_sample(backend_jm);
/* Extract elapsed cycle count for each clock domain if enabled. */
kbase_hwcnt_metadata_for_each_clock(dst_enable_map->metadata, clk)
{
kbase_hwcnt_metadata_for_each_clock(dst_enable_map->metadata, clk) {
if (!kbase_hwcnt_clk_enable_map_enabled(dst_enable_map->clk_enable_map, clk))
continue;
@ -645,8 +659,9 @@ static int kbasep_hwcnt_backend_jm_dump_get(struct kbase_hwcnt_backend *backend,
return errcode;
#endif /* CONFIG_MALI_NO_MALI */
errcode = kbase_hwcnt_jm_dump_get(dst, backend_jm->to_user_buf, dst_enable_map,
backend_jm->pm_core_mask, &backend_jm->curr_config,
accumulate);
backend_jm->pm_core_mask, backend_jm->debug_core_mask,
backend_jm->max_core_mask, backend_jm->max_l2_slices,
&backend_jm->curr_config, accumulate);
if (errcode)
return errcode;

184
drivers/gpu/arm/midgard/hwcnt/mali_kbase_hwcnt_gpu.c
View File

@ -169,7 +169,7 @@ static int kbasep_hwcnt_backend_gpu_metadata_create(const struct kbase_hwcnt_gpu
/* Calculate number of block instances that aren't cores */
non_core_block_count = 2 + gpu_info->l2_count;
/* Calculate number of block instances that are shader cores */
sc_block_count = fls64(gpu_info->core_mask);
sc_block_count = (size_t)fls64(gpu_info->core_mask);
/* Determine the total number of cores */
core_block_count = sc_block_count;
@ -274,7 +274,8 @@ static int kbasep_hwcnt_backend_gpu_metadata_create(const struct kbase_hwcnt_gpu
desc.clk_cnt = gpu_info->clk_cnt;
/* The JM, Tiler, and L2s are always available, and are before cores */
kbase_hwcnt_set_avail_mask(&desc.avail_mask, (1ull << non_core_block_count) - 1, 0);
kbase_hwcnt_set_avail_mask(&desc.avail_mask, 0, 0);
kbase_hwcnt_set_avail_mask_bits(&desc.avail_mask, 0, non_core_block_count, U64_MAX);
kbase_hwcnt_set_avail_mask_bits(&desc.avail_mask, non_core_block_count, sc_block_count,
gpu_info->core_mask);
@ -293,7 +294,7 @@ static size_t kbasep_hwcnt_backend_jm_dump_bytes(const struct kbase_hwcnt_gpu_in
{
WARN_ON(!gpu_info);
return (2 + gpu_info->l2_count + fls64(gpu_info->core_mask)) *
return (2 + gpu_info->l2_count + (size_t)fls64(gpu_info->core_mask)) *
gpu_info->prfcnt_values_per_block * KBASE_HWCNT_VALUE_HW_BYTES;
}
@ -372,33 +373,50 @@ void kbase_hwcnt_csf_metadata_destroy(const struct kbase_hwcnt_metadata *metadat
kbase_hwcnt_metadata_destroy(metadata);
}
static bool is_block_type_shader(const u64 blk_type)
bool kbase_hwcnt_is_block_type_shader(const enum kbase_hwcnt_gpu_v5_block_type blk_type)
{
bool is_shader = false;
if (blk_type == KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_SC ||
blk_type == KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_SC2 ||
blk_type == KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_SC3 ||
blk_type == KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_SC_UNDEFINED)
is_shader = true;
return true;
return is_shader;
return false;
}
static bool is_block_type_l2_cache(const u64 blk_type)
bool kbase_hwcnt_is_block_type_memsys(const enum kbase_hwcnt_gpu_v5_block_type blk_type)
{
bool is_l2_cache = false;
if (blk_type == KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_MEMSYS ||
blk_type == KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_MEMSYS2 ||
blk_type == KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_MEMSYS_UNDEFINED)
is_l2_cache = true;
return true;
return is_l2_cache;
return false;
}
bool kbase_hwcnt_is_block_type_tiler(const enum kbase_hwcnt_gpu_v5_block_type blk_type)
{
if (blk_type == KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_TILER ||
blk_type == KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_TILER_UNDEFINED)
return true;
return false;
}
bool kbase_hwcnt_is_block_type_fe(const enum kbase_hwcnt_gpu_v5_block_type blk_type)
{
if (blk_type == KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_FE ||
blk_type == KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_FE2 ||
blk_type == KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_FE3 ||
blk_type == KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_FE_UNDEFINED)
return true;
return false;
}
int kbase_hwcnt_jm_dump_get(struct kbase_hwcnt_dump_buffer *dst, u64 *src,
const struct kbase_hwcnt_enable_map *dst_enable_map, u64 pm_core_mask,
u64 debug_core_mask, u64 max_core_mask, size_t max_l2_slices,
const struct kbase_hwcnt_curr_config *curr_config, bool accumulate)
{
const struct kbase_hwcnt_metadata *metadata;
@ -406,6 +424,7 @@ int kbase_hwcnt_jm_dump_get(struct kbase_hwcnt_dump_buffer *dst, u64 *src,
const u64 *dump_src = src;
size_t src_offset = 0;
u64 core_mask = pm_core_mask;
u64 shader_present = curr_config->shader_present;
/* Variables to deal with the current configuration */
size_t l2_count = 0;
@ -415,13 +434,12 @@ int kbase_hwcnt_jm_dump_get(struct kbase_hwcnt_dump_buffer *dst, u64 *src,
metadata = dst->metadata;
kbase_hwcnt_metadata_for_each_block(metadata, blk, blk_inst)
{
kbase_hwcnt_metadata_for_each_block(metadata, blk, blk_inst) {
const size_t hdr_cnt = kbase_hwcnt_metadata_block_headers_count(metadata, blk);
const size_t ctr_cnt = kbase_hwcnt_metadata_block_counters_count(metadata, blk);
const u64 blk_type = kbase_hwcnt_metadata_block_type(metadata, blk);
const bool is_shader_core = is_block_type_shader(blk_type);
const bool is_l2_cache = is_block_type_l2_cache(blk_type);
const bool is_shader_core = kbase_hwcnt_is_block_type_shader(blk_type);
const bool is_l2_cache = kbase_hwcnt_is_block_type_memsys(blk_type);
const bool is_undefined = kbase_hwcnt_is_block_type_undefined(blk_type);
blk_stt_t *dst_blk_stt =
kbase_hwcnt_dump_buffer_block_state_instance(dst, blk, blk_inst);
@ -458,25 +476,52 @@ int kbase_hwcnt_jm_dump_get(struct kbase_hwcnt_dump_buffer *dst, u64 *src,
if (blk_valid) {
bool blk_powered;
blk_stt_t current_block_state;
blk_stt_t current_block_state = 0;
if (!is_shader_core) {
/* Under the current PM system, counters will only be
* enabled after all non shader core blocks are powered up.
/* The L2 block must be available at this point, or handled
* differently below.
* Every partition must have a FE and a tiler, so they
* must be implicitly available as part of the current
* configuration.
*/
blk_powered = true;
current_block_state |= KBASE_HWCNT_STATE_AVAILABLE;
} else {
/* Check the PM core mask to see if the shader core is
* powered up.
*/
blk_powered = core_mask & 1;
/* Set availability bits based on whether the core is
* present in both the shader_present AND the core
* mask in sysFS. The core masks are shifted to the
* right at the end of the loop so always check the
* rightmost bit.
*/
if ((shader_present & debug_core_mask) & 0x1)
current_block_state |= KBASE_HWCNT_STATE_AVAILABLE;
else {
/* If this branch is taken, the shader core may
* be:
* * in the max configuration, but not enabled
* through the sysFS core mask
* * in the max configuration, but not in the
* current configuration
* * physically not present
*/
current_block_state |=
KBASE_HWCNT_STATE_UNAVAILABLE;
}
}
current_block_state = (blk_powered) ? KBASE_HWCNT_STATE_ON :
KBASE_HWCNT_STATE_OFF;
/* Note: KBASE_HWCNT_STATE_OFF for non-shader cores (L2, Tiler, JM)
* is handled on this backend's dump_disable function
* is handled on this backend's dump_disable function (since
* they are considered to always be powered here).
*/
current_block_state |= (blk_powered) ? KBASE_HWCNT_STATE_ON :
KBASE_HWCNT_STATE_OFF;
if (accumulate) {
/* Only update existing counter values if block was powered
* and valid
@ -500,10 +545,22 @@ int kbase_hwcnt_jm_dump_get(struct kbase_hwcnt_dump_buffer *dst, u64 *src,
kbase_hwcnt_block_state_set(dst_blk_stt,
current_block_state);
}
} else if (is_l2_cache && !is_undefined) {
/* Defined L2 can only reach here when the partition does not
* own it. Check that the L2 count is within the resource
* group or whole GPU's max L2 count, and if so,
* mark it as unavailable.
*/
if (l2_count <= max_l2_slices) {
kbase_hwcnt_block_state_set(
dst_blk_stt, KBASE_HWCNT_STATE_OFF |
KBASE_HWCNT_STATE_UNAVAILABLE);
}
kbase_hwcnt_dump_buffer_block_zero(dst_blk, (hdr_cnt + ctr_cnt));
} else {
/* Even though the block might be undefined, the user has enabled
* counter collection for it. We should not propagate garbage data,
* or copy/accumulate the block states.
/* Even though the block is undefined, the user has
* enabled counter collection for it. We should not propagate
* garbage data, or copy/accumulate the block states.
*/
if (accumulate) {
/* No-op to preserve existing values */
@ -520,8 +577,13 @@ int kbase_hwcnt_jm_dump_get(struct kbase_hwcnt_dump_buffer *dst, u64 *src,
/* Just increase the src_offset if the HW is available */
if (hw_res_available)
src_offset += (hdr_cnt + ctr_cnt);
if (is_shader_core)
core_mask = core_mask >> 1;
if (is_shader_core) {
/* Shift each core mask right by 1 */
core_mask >>= 1;
debug_core_mask >>= 1;
max_core_mask >>= 1;
shader_present >>= 1;
}
}
return 0;
@ -544,8 +606,7 @@ int kbase_hwcnt_csf_dump_get(struct kbase_hwcnt_dump_buffer *dst, u64 *src,
metadata = dst->metadata;
kbase_hwcnt_metadata_for_each_block(metadata, blk, blk_inst)
{
kbase_hwcnt_metadata_for_each_block(metadata, blk, blk_inst) {
const size_t hdr_cnt = kbase_hwcnt_metadata_block_headers_count(metadata, blk);
const size_t ctr_cnt = kbase_hwcnt_metadata_block_counters_count(metadata, blk);
const uint64_t blk_type = kbase_hwcnt_metadata_block_type(metadata, blk);
@ -650,8 +711,7 @@ void kbase_hwcnt_gpu_enable_map_to_physical(struct kbase_hwcnt_physical_enable_m
metadata = src->metadata;
kbase_hwcnt_metadata_for_each_block(metadata, blk, blk_inst)
{
kbase_hwcnt_metadata_for_each_block(metadata, blk, blk_inst) {
const u64 blk_type = kbase_hwcnt_metadata_block_type(metadata, blk);
const u64 *blk_map = kbase_hwcnt_enable_map_block_instance(src, blk, blk_inst);
const size_t map_stride =
@ -749,14 +809,31 @@ void kbase_hwcnt_gpu_set_to_physical(enum kbase_hwcnt_physical_set *dst, enum kb
void kbase_hwcnt_gpu_enable_map_from_physical(struct kbase_hwcnt_enable_map *dst,
const struct kbase_hwcnt_physical_enable_map *src)
{
const struct kbase_hwcnt_metadata *metadata;
struct kbase_hwcnt_enable_cm cm = {};
u64 fe_bm[EM_COUNT] = { 0 };
u64 shader_bm[EM_COUNT] = { 0 };
u64 tiler_bm[EM_COUNT] = { 0 };
u64 mmu_l2_bm[EM_COUNT] = { 0 };
u64 fw_bm[EM_COUNT] = { 0 };
u64 csg_bm[EM_COUNT] = { 0 };
if (WARN_ON(!src) || WARN_ON(!dst))
return;
kbasep_hwcnt_backend_gpu_block_map_from_physical(src->fe_bm, &cm.fe_bm[EM_LO],
&cm.fe_bm[EM_HI]);
kbasep_hwcnt_backend_gpu_block_map_from_physical(src->shader_bm, &cm.shader_bm[EM_LO],
&cm.shader_bm[EM_HI]);
kbasep_hwcnt_backend_gpu_block_map_from_physical(src->tiler_bm, &cm.tiler_bm[EM_LO],
&cm.tiler_bm[EM_HI]);
kbasep_hwcnt_backend_gpu_block_map_from_physical(src->mmu_l2_bm, &cm.mmu_l2_bm[EM_LO],
&cm.mmu_l2_bm[EM_HI]);
kbasep_hwcnt_backend_gpu_block_map_from_physical(src->fw_bm, &cm.fw_bm[EM_LO],
&cm.fw_bm[EM_HI]);
kbasep_hwcnt_backend_gpu_block_map_from_physical(src->csg_bm, &cm.csg_bm[EM_LO],
&cm.csg_bm[EM_HI]);
kbase_hwcnt_gpu_enable_map_from_cm(dst, &cm);
}
void kbase_hwcnt_gpu_enable_map_from_cm(struct kbase_hwcnt_enable_map *dst,
const struct kbase_hwcnt_enable_cm *src)
{
const struct kbase_hwcnt_metadata *metadata;
size_t blk, blk_inst;
if (WARN_ON(!src) || WARN_ON(!dst))
@ -764,19 +841,7 @@ void kbase_hwcnt_gpu_enable_map_from_physical(struct kbase_hwcnt_enable_map *dst
metadata = dst->metadata;
kbasep_hwcnt_backend_gpu_block_map_from_physical(src->fe_bm, &fe_bm[EM_LO], &fe_bm[EM_HI]);
kbasep_hwcnt_backend_gpu_block_map_from_physical(src->shader_bm, &shader_bm[EM_LO],
&shader_bm[EM_HI]);
kbasep_hwcnt_backend_gpu_block_map_from_physical(src->tiler_bm, &tiler_bm[EM_LO],
&tiler_bm[EM_HI]);
kbasep_hwcnt_backend_gpu_block_map_from_physical(src->mmu_l2_bm, &mmu_l2_bm[EM_LO],
&mmu_l2_bm[EM_HI]);
kbasep_hwcnt_backend_gpu_block_map_from_physical(src->fw_bm, &fw_bm[EM_LO], &fw_bm[EM_HI]);
kbasep_hwcnt_backend_gpu_block_map_from_physical(src->csg_bm, &csg_bm[EM_LO],
&csg_bm[EM_HI]);
kbase_hwcnt_metadata_for_each_block(metadata, blk, blk_inst)
{
kbase_hwcnt_metadata_for_each_block(metadata, blk, blk_inst) {
const u64 blk_type = kbase_hwcnt_metadata_block_type(metadata, blk);
u64 *blk_map = kbase_hwcnt_enable_map_block_instance(dst, blk, blk_inst);
const size_t map_stride =
@ -806,36 +871,36 @@ void kbase_hwcnt_gpu_enable_map_from_physical(struct kbase_hwcnt_enable_map *dst
case KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_FE2:
fallthrough;
case KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_FE3:
blk_map[map_idx] = fe_bm[map_idx];
blk_map[map_idx] = src->fe_bm[map_idx];
break;
case KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_TILER:
blk_map[map_idx] = tiler_bm[map_idx];
blk_map[map_idx] = src->tiler_bm[map_idx];
break;
case KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_SC:
fallthrough;
case KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_SC2:
fallthrough;
case KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_SC3:
blk_map[map_idx] = shader_bm[map_idx];
blk_map[map_idx] = src->shader_bm[map_idx];
break;
case KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_MEMSYS:
fallthrough;
case KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_MEMSYS2:
blk_map[map_idx] = mmu_l2_bm[map_idx];
blk_map[map_idx] = src->mmu_l2_bm[map_idx];
break;
case KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_FW:
fallthrough;
case KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_FW2:
fallthrough;
case KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_FW3:
blk_map[map_idx] = fw_bm[map_idx];
blk_map[map_idx] = src->fw_bm[map_idx];
break;
case KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_CSG:
fallthrough;
case KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_CSG2:
fallthrough;
case KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_CSG3:
blk_map[map_idx] = csg_bm[map_idx];
blk_map[map_idx] = src->csg_bm[map_idx];
break;
default:
WARN(true, "Invalid block type %llu", blk_type);
@ -855,8 +920,7 @@ void kbase_hwcnt_gpu_patch_dump_headers(struct kbase_hwcnt_dump_buffer *buf,
metadata = buf->metadata;
kbase_hwcnt_metadata_for_each_block(metadata, blk, blk_inst)
{
kbase_hwcnt_metadata_for_each_block(metadata, blk, blk_inst) {
u64 *buf_blk = kbase_hwcnt_dump_buffer_block_instance(buf, blk, blk_inst);
const u64 *blk_map =
kbase_hwcnt_enable_map_block_instance(enable_map, blk, blk_inst);

69
drivers/gpu/arm/midgard/hwcnt/mali_kbase_hwcnt_gpu.h
View File

@ -138,6 +138,24 @@ struct kbase_hwcnt_physical_enable_map {
u32 csg_bm;
};
/**
* struct kbase_hwcnt_enable_cm - 128-bit enable counter masks.
* @fe_bm: Front end (JM/CSHW) counters selection bitmask.
* @shader_bm: Shader counters selection bitmask.
* @tiler_bm: Tiler counters selection bitmask.
* @mmu_l2_bm: MMU_L2 counters selection bitmask.
* @fw_bm: CSF firmware counters selection bitmask.
* @csg_bm: CSF CSG counters selection bitmask.
*/
struct kbase_hwcnt_enable_cm {
u64 fe_bm[2];
u64 shader_bm[2];
u64 tiler_bm[2];
u64 mmu_l2_bm[2];
u64 fw_bm[2];
u64 csg_bm[2];
};
/*
* Values for Hardware Counter SET_SELECT value.
* Directly passed to HW.
@ -275,16 +293,23 @@ void kbase_hwcnt_csf_metadata_destroy(const struct kbase_hwcnt_metadata *metadat
* kbase_hwcnt_jm_dump_get() - Copy or accumulate enabled counters from the raw
* dump buffer in src into the dump buffer
* abstraction in dst.
* @dst: Non-NULL pointer to destination dump buffer.
* @src: Non-NULL pointer to source raw dump buffer, of same length
* as dump_buf_bytes in the metadata of destination dump
* buffer.
* @dst_enable_map: Non-NULL pointer to enable map specifying enabled values.
* @pm_core_mask: PM state synchronized shaders core mask with the dump.
* @curr_config: Current allocated hardware resources to correctly map the
* source raw dump buffer to the destination dump buffer.
* @accumulate: True if counters in source should be accumulated into
* destination, rather than copied.
* @dst: Non-NULL pointer to destination dump buffer.
* @src: Non-NULL pointer to source raw dump buffer, of same length
* as dump_buf_bytes in the metadata of destination dump
* buffer.
* @dst_enable_map: Non-NULL pointer to enable map specifying enabled values.
* @pm_core_mask: PM state synchronized shaders core mask with the dump.
* @debug_core_mask: User-set mask of cores to be used by the GPU.
* @max_core_mask: Core mask of all cores allocated to the GPU (non
* virtualized platforms) or resource group (virtualized
* platforms).
* @max_l2_slices: Maximum number of L2 slices allocated to the GPU (non
* virtualised platforms) or resource group (virtualized
* platforms).
* @curr_config: Current allocated hardware resources to correctly map the
* source raw dump buffer to the destination dump buffer.
* @accumulate: True if counters in source should be accumulated into
* destination, rather than copied.
*
* The dst and dst_enable_map MUST have been created from the same metadata as
* returned from the call to kbase_hwcnt_jm_metadata_create as was used to get
@ -294,8 +319,9 @@ void kbase_hwcnt_csf_metadata_destroy(const struct kbase_hwcnt_metadata *metadat
*/
int kbase_hwcnt_jm_dump_get(struct kbase_hwcnt_dump_buffer *dst, u64 *src,
const struct kbase_hwcnt_enable_map *dst_enable_map,
const u64 pm_core_mask,
const struct kbase_hwcnt_curr_config *curr_config, bool accumulate);
const u64 pm_core_mask, u64 debug_core_mask, u64 max_core_mask,
size_t max_l2_slices, const struct kbase_hwcnt_curr_config *curr_config,
bool accumulate);
/**
* kbase_hwcnt_csf_dump_get() - Copy or accumulate enabled counters from the raw
@ -420,4 +446,23 @@ void kbase_hwcnt_gpu_enable_map_from_physical(struct kbase_hwcnt_enable_map *dst
void kbase_hwcnt_gpu_patch_dump_headers(struct kbase_hwcnt_dump_buffer *buf,
const struct kbase_hwcnt_enable_map *enable_map);
bool kbase_hwcnt_is_block_type_shader(const enum kbase_hwcnt_gpu_v5_block_type blk_type);
bool kbase_hwcnt_is_block_type_memsys(const enum kbase_hwcnt_gpu_v5_block_type blk_type);
bool kbase_hwcnt_is_block_type_tiler(const enum kbase_hwcnt_gpu_v5_block_type blk_type);
bool kbase_hwcnt_is_block_type_fe(const enum kbase_hwcnt_gpu_v5_block_type blk_type);
/**
* kbase_hwcnt_gpu_enable_map_from_cm() - Builds enable map abstraction from
* counter selection bitmasks.
* @dst: Non-NULL pointer to destination enable map abstraction.
* @src: Non-NULL pointer to source counter selection bitmasks.
*
* The dst must have been created from a metadata returned from a call to
* kbase_hwcnt_jm_metadata_create or kbase_hwcnt_csf_metadata_create.
*/
void kbase_hwcnt_gpu_enable_map_from_cm(struct kbase_hwcnt_enable_map *dst,
const struct kbase_hwcnt_enable_cm *src);
#endif /* _KBASE_HWCNT_GPU_H_ */

34
drivers/gpu/arm/midgard/hwcnt/mali_kbase_hwcnt_types.c
View File

@ -208,8 +208,7 @@ void kbase_hwcnt_dump_buffer_zero(struct kbase_hwcnt_dump_buffer *dst,
metadata = dst->metadata;
kbase_hwcnt_metadata_for_each_block(metadata, blk, blk_inst)
{
kbase_hwcnt_metadata_for_each_block(metadata, blk, blk_inst) {
u64 *dst_blk;
size_t val_cnt;
@ -248,8 +247,7 @@ void kbase_hwcnt_dump_buffer_zero_non_enabled(struct kbase_hwcnt_dump_buffer *ds
metadata = dst->metadata;
kbase_hwcnt_metadata_for_each_block(metadata, blk, blk_inst)
{
kbase_hwcnt_metadata_for_each_block(metadata, blk, blk_inst) {
u64 *dst_blk = kbase_hwcnt_dump_buffer_block_instance(dst, blk, blk_inst);
blk_stt_t *dst_blk_stt =
kbase_hwcnt_dump_buffer_block_state_instance(dst, blk, blk_inst);
@ -291,8 +289,7 @@ void kbase_hwcnt_dump_buffer_copy(struct kbase_hwcnt_dump_buffer *dst,
metadata = dst->metadata;
kbase_hwcnt_metadata_for_each_block(metadata, blk, blk_inst)
{
kbase_hwcnt_metadata_for_each_block(metadata, blk, blk_inst) {
u64 *dst_blk;
const u64 *src_blk;
blk_stt_t *dst_blk_stt;
@ -312,8 +309,7 @@ void kbase_hwcnt_dump_buffer_copy(struct kbase_hwcnt_dump_buffer *dst,
kbase_hwcnt_block_state_copy(dst_blk_stt, src_blk_stt);
}
kbase_hwcnt_metadata_for_each_clock(metadata, clk)
{
kbase_hwcnt_metadata_for_each_clock(metadata, clk) {
if (kbase_hwcnt_clk_enable_map_enabled(dst_enable_map->clk_enable_map, clk))
dst->clk_cnt_buf[clk] = src->clk_cnt_buf[clk];
}
@ -334,8 +330,7 @@ void kbase_hwcnt_dump_buffer_copy_strict(struct kbase_hwcnt_dump_buffer *dst,
metadata = dst->metadata;
kbase_hwcnt_metadata_for_each_block(metadata, blk, blk_inst)
{
kbase_hwcnt_metadata_for_each_block(metadata, blk, blk_inst) {
u64 *dst_blk = kbase_hwcnt_dump_buffer_block_instance(dst, blk, blk_inst);
const u64 *src_blk = kbase_hwcnt_dump_buffer_block_instance(src, blk, blk_inst);
blk_stt_t *dst_blk_stt =
@ -358,8 +353,7 @@ void kbase_hwcnt_dump_buffer_copy_strict(struct kbase_hwcnt_dump_buffer *dst,
kbase_hwcnt_block_state_set(dst_blk_stt, KBASE_HWCNT_STATE_UNKNOWN);
}
kbase_hwcnt_metadata_for_each_clock(metadata, clk)
{
kbase_hwcnt_metadata_for_each_clock(metadata, clk) {
bool clk_enabled =
kbase_hwcnt_clk_enable_map_enabled(dst_enable_map->clk_enable_map, clk);
@ -382,8 +376,7 @@ void kbase_hwcnt_dump_buffer_accumulate(struct kbase_hwcnt_dump_buffer *dst,
metadata = dst->metadata;
kbase_hwcnt_metadata_for_each_block(metadata, blk, blk_inst)
{
kbase_hwcnt_metadata_for_each_block(metadata, blk, blk_inst) {
u64 *dst_blk;
const u64 *src_blk;
blk_stt_t *dst_blk_stt;
@ -405,8 +398,7 @@ void kbase_hwcnt_dump_buffer_accumulate(struct kbase_hwcnt_dump_buffer *dst,
kbase_hwcnt_block_state_accumulate(dst_blk_stt, src_blk_stt);
}
kbase_hwcnt_metadata_for_each_clock(metadata, clk)
{
kbase_hwcnt_metadata_for_each_clock(metadata, clk) {
if (kbase_hwcnt_clk_enable_map_enabled(dst_enable_map->clk_enable_map, clk))
dst->clk_cnt_buf[clk] += src->clk_cnt_buf[clk];
}
@ -427,8 +419,7 @@ void kbase_hwcnt_dump_buffer_accumulate_strict(struct kbase_hwcnt_dump_buffer *d
metadata = dst->metadata;
kbase_hwcnt_metadata_for_each_block(metadata, blk, blk_inst)
{
kbase_hwcnt_metadata_for_each_block(metadata, blk, blk_inst) {
u64 *dst_blk = kbase_hwcnt_dump_buffer_block_instance(dst, blk, blk_inst);
const u64 *src_blk = kbase_hwcnt_dump_buffer_block_instance(src, blk, blk_inst);
const u64 *blk_em =
@ -455,8 +446,7 @@ void kbase_hwcnt_dump_buffer_accumulate_strict(struct kbase_hwcnt_dump_buffer *d
kbase_hwcnt_block_state_set(dst_blk_stt, KBASE_HWCNT_STATE_UNKNOWN);
}
kbase_hwcnt_metadata_for_each_clock(metadata, clk)
{
kbase_hwcnt_metadata_for_each_clock(metadata, clk) {
if (kbase_hwcnt_clk_enable_map_enabled(dst_enable_map->clk_enable_map, clk))
dst->clk_cnt_buf[clk] += src->clk_cnt_buf[clk];
else
@ -477,14 +467,12 @@ void kbase_hwcnt_dump_buffer_block_state_update(struct kbase_hwcnt_dump_buffer *
metadata = dst->metadata;
kbase_hwcnt_metadata_for_each_block(metadata, blk, blk_inst)
{
kbase_hwcnt_metadata_for_each_block(metadata, blk, blk_inst) {
if (kbase_hwcnt_metadata_block_instance_avail(metadata, blk, blk_inst) &&
kbase_hwcnt_enable_map_block_enabled(dst_enable_map, blk, blk_inst)) {
blk_stt_t *dst_blk_stt =
kbase_hwcnt_dump_buffer_block_state_instance(dst, blk, blk_inst);
/* Block is available and enabled, so update the block state */
*dst_blk_stt |= blk_stt_val;
}
}

5
drivers/gpu/arm/midgard/hwcnt/mali_kbase_hwcnt_types.h
View File

@ -321,7 +321,7 @@ static inline void kbase_hwcnt_cp_avail_mask(struct kbase_hwcnt_avail_mask *dst_
* placed is expected to be fully contained by the array of bitmask elements.
* @length_in_bits: The length of the value being placed in the bitmask. Assumed to be no more
* than 64 bits in length.
* @value: Pointer to the source value to be written into the bitmask.
* @value: The source value to be written into the bitmask.
*/
static inline void kbase_hwcnt_set_avail_mask_bits(struct kbase_hwcnt_avail_mask *avail_mask,
size_t offset_in_bits, size_t length_in_bits,
@ -929,8 +929,7 @@ kbase_hwcnt_enable_map_any_enabled(const struct kbase_hwcnt_enable_map *enable_m
if (enable_map->metadata->clk_cnt > 0 && (enable_map->clk_enable_map & clk_enable_map_mask))
return true;
kbase_hwcnt_metadata_for_each_block(enable_map->metadata, blk, blk_inst)
{
kbase_hwcnt_metadata_for_each_block(enable_map->metadata, blk, blk_inst) {
if (kbase_hwcnt_enable_map_block_enabled(enable_map, blk, blk_inst))
return true;
}

6
drivers/gpu/arm/midgard/ipa/backend/mali_kbase_ipa_counter_common_csf.c
View File

@ -68,7 +68,7 @@ static s64 kbase_ipa_group_energy(s32 coeff, u64 counter_value)
/* Range: 0 < counter_value < 2^38 */
/* Range: -2^59 < ret < 2^59 (as -2^21 < coeff < 2^21) */
return counter_value * (s64)coeff;
return (s64)counter_value * (s64)coeff;
}
/**
@ -183,7 +183,7 @@ static int calculate_coeff(struct kbase_ipa_counter_model_data *model_data,
/* Range: 0 <= coeff < 2^63 */
if (total_energy >= 0)
coeff = total_energy;
coeff = (u64)total_energy;
else
dev_dbg(model_data->kbdev->dev, "Energy value came negative as %lld", total_energy);
@ -224,7 +224,7 @@ static int calculate_coeff(struct kbase_ipa_counter_model_data *model_data,
/* Scale by user-specified integer factor.
* Range: 0 <= coeff_mul < 2^43
*/
coeff_mul = coeff * model_data->scaling_factor;
coeff_mul = coeff * (u64)model_data->scaling_factor;
/* The power models have results with units
* mW/(MHz V^2), i.e. nW/(Hz V^2). With precision of 1/1000000, this

4
drivers/gpu/arm/midgard/ipa/backend/mali_kbase_ipa_counter_common_jm.c
View File

@ -211,7 +211,7 @@ int kbase_ipa_vinstr_dynamic_coeff(struct kbase_ipa_model *model, u32 *coeffp)
/* Range: 0 <= coeff < 2^57 */
if (energy > 0)
coeff = energy;
coeff = (u64)energy;
/* Range: 0 <= coeff < 2^57 (because active_cycles >= 1). However, this
* can be constrained further: Counter values can only be increased by
@ -244,7 +244,7 @@ int kbase_ipa_vinstr_dynamic_coeff(struct kbase_ipa_model *model, u32 *coeffp)
/* Scale by user-specified integer factor.
* Range: 0 <= coeff_mul < 2^57
*/
coeff_mul = coeff * model_data->scaling_factor;
coeff_mul = coeff * (u64)model_data->scaling_factor;
/* The power models have results with units
* mW/(MHz V^2), i.e. nW/(Hz V^2). With precision of 1/1000000, this

4
drivers/gpu/arm/midgard/ipa/mali_kbase_ipa.c
View File

@ -174,7 +174,7 @@ int kbase_ipa_model_add_param_string(struct kbase_ipa_model *model, const char *
of_node_put(model_dt_node);
if (err && dt_required) {
strncpy(addr, "", size - 1);
strscpy(addr, "", size);
dev_warn(model->kbdev->dev, "Error %d, no DT entry: %s.%s = \'%s\'\n", err,
model->ops->name, name, addr);
err = 0;
@ -182,7 +182,7 @@ int kbase_ipa_model_add_param_string(struct kbase_ipa_model *model, const char *
} else if (err && !dt_required) {
origin = "default";
} else /* !err */ {
strncpy(addr, string_prop_value, size - 1);
strscpy(addr, string_prop_value, size);
origin = "DT";
}

2
drivers/gpu/arm/midgard/ipa/mali_kbase_ipa_debugfs.c
View File

@ -97,7 +97,7 @@ static ssize_t param_string_set(struct file *file, const char __user *user_buf,
struct kbase_ipa_model_param *param = file->private_data;
struct kbase_ipa_model *model = param->model;
char *old_str = NULL;
ssize_t ret = count;
ssize_t ret = (ssize_t)count;
size_t buf_size;
int err;

3
drivers/gpu/arm/midgard/ipa/mali_kbase_ipa_simple.c
View File

@ -294,6 +294,9 @@ static int kbase_simple_power_model_recalculate(struct kbase_ipa_model *model)
if (!strnlen(model_data->tz_name, sizeof(model_data->tz_name))) {
model_data->gpu_tz = NULL;
dev_warn(model->kbdev->dev,
"No thermal zone specified, will use the default temperature value of %u",
FALLBACK_STATIC_TEMPERATURE);
} else {
char tz_name[THERMAL_NAME_LENGTH];
u32 string_len = strscpy(tz_name, model_data->tz_name, sizeof(tz_name));

47
drivers/gpu/arm/midgard/jm/mali_kbase_jm_defs.h
View File

@ -29,6 +29,8 @@
#include "mali_kbase_js_defs.h"
#include <linux/version_compat_defs.h>
/* Dump Job slot trace on error (only active if KBASE_KTRACE_ENABLE != 0) */
#define KBASE_KTRACE_DUMP_ON_JOB_SLOT_ERROR 1
@ -70,29 +72,29 @@
#define KBASE_DISABLE_SCHEDULING_HARD_STOPS 0
/* Atom has been previously soft-stopped */
#define KBASE_KATOM_FLAG_BEEN_SOFT_STOPPED (1 << 1)
#define KBASE_KATOM_FLAG_BEEN_SOFT_STOPPED (1U << 1)
/* Atom has been previously retried to execute */
#define KBASE_KATOM_FLAGS_RERUN (1 << 2)
#define KBASE_KATOM_FLAGS_RERUN (1U << 2)
/* Atom submitted with JOB_CHAIN_FLAG bit set in JS_CONFIG_NEXT register, helps
* to disambiguate short-running job chains during soft/hard stopping of jobs
*/
#define KBASE_KATOM_FLAGS_JOBCHAIN (1 << 3)
#define KBASE_KATOM_FLAGS_JOBCHAIN (1U << 3)
/* Atom has been previously hard-stopped. */
#define KBASE_KATOM_FLAG_BEEN_HARD_STOPPED (1 << 4)
#define KBASE_KATOM_FLAG_BEEN_HARD_STOPPED (1U << 4)
/* Atom has caused us to enter disjoint state */
#define KBASE_KATOM_FLAG_IN_DISJOINT (1 << 5)
#define KBASE_KATOM_FLAG_IN_DISJOINT (1U << 5)
/* Atom blocked on cross-slot dependency */
#define KBASE_KATOM_FLAG_X_DEP_BLOCKED (1 << 7)
#define KBASE_KATOM_FLAG_X_DEP_BLOCKED (1U << 7)
/* Atom has fail dependency on cross-slot dependency */
#define KBASE_KATOM_FLAG_FAIL_BLOCKER (1 << 8)
#define KBASE_KATOM_FLAG_FAIL_BLOCKER (1U << 8)
/* Atom is currently in the list of atoms blocked on cross-slot dependencies */
#define KBASE_KATOM_FLAG_JSCTX_IN_X_DEP_LIST (1 << 9)
#define KBASE_KATOM_FLAG_JSCTX_IN_X_DEP_LIST (1U << 9)
/* Atom requires GPU to be in protected mode */
#define KBASE_KATOM_FLAG_PROTECTED (1 << 11)
#define KBASE_KATOM_FLAG_PROTECTED (1U << 11)
/* Atom has been stored in runnable_tree */
#define KBASE_KATOM_FLAG_JSCTX_IN_TREE (1 << 12)
#define KBASE_KATOM_FLAG_JSCTX_IN_TREE (1U << 12)
/* Atom is waiting for L2 caches to power up in order to enter protected mode */
#define KBASE_KATOM_FLAG_HOLDING_L2_REF_PROT (1 << 13)
#define KBASE_KATOM_FLAG_HOLDING_L2_REF_PROT (1U << 13)
/* SW related flags about types of JS_COMMAND action
* NOTE: These must be masked off by JS_COMMAND_MASK
@ -131,6 +133,9 @@
* @JM_DEFAULT_JS_FREE_TIMEOUT: Maximum timeout to wait for JS_COMMAND_NEXT
* to be updated on HW side so a Job Slot is
* considered free.
* @KBASE_PRFCNT_ACTIVE_TIMEOUT: Waiting time for prfcnt to be ready.
* @KBASE_CLEAN_CACHE_TIMEOUT: Waiting time for cache flush to complete.
* @KBASE_AS_INACTIVE_TIMEOUT: Waiting time for MCU address space to become inactive.
* @KBASE_TIMEOUT_SELECTOR_COUNT: Number of timeout selectors.
* @KBASE_DEFAULT_TIMEOUT: Fallthrough in case an invalid timeout is
* passed.
@ -138,7 +143,9 @@
enum kbase_timeout_selector {
MMU_AS_INACTIVE_WAIT_TIMEOUT,
JM_DEFAULT_JS_FREE_TIMEOUT,
KBASE_PRFCNT_ACTIVE_TIMEOUT,
KBASE_CLEAN_CACHE_TIMEOUT,
KBASE_AS_INACTIVE_TIMEOUT,
/* Must be the last in the enum */
KBASE_TIMEOUT_SELECTOR_COUNT,
KBASE_DEFAULT_TIMEOUT = JM_DEFAULT_JS_FREE_TIMEOUT
@ -526,13 +533,7 @@ struct kbase_jd_atom {
/* Use the functions/API defined in mali_kbase_fence.h to
* when working with this sub struct
*/
#if IS_ENABLED(CONFIG_SYNC_FILE)
#if (KERNEL_VERSION(4, 10, 0) > LINUX_VERSION_CODE)
struct fence *fence_in;
#else
struct dma_fence *fence_in;
#endif
#endif
/* This points to the dma-buf output fence for this atom. If
* this is NULL then there is no fence for this atom and the
* following fields related to dma_fence may have invalid data.
@ -544,20 +545,12 @@ struct kbase_jd_atom {
* regardless of the event_code of the katom (signal also on
* failure).
*/
#if (KERNEL_VERSION(4, 10, 0) > LINUX_VERSION_CODE)
struct fence *fence;
#else
struct dma_fence *fence;
#endif
/* This is the callback object that is registered for the fence_in.
* The callback is invoked when the fence_in is signaled.
*/
#if (KERNEL_VERSION(4, 10, 0) > LINUX_VERSION_CODE)
struct fence_cb fence_cb;
#else
struct dma_fence_cb fence_cb;
#endif
bool fence_cb_added;
unsigned int context;
@ -857,7 +850,7 @@ struct jsctx_queue {
* @current_setup: Stores the MMU configuration for this address space.
*/
struct kbase_as {
int number;
unsigned int number;
struct workqueue_struct *pf_wq;
struct work_struct work_pagefault;
struct work_struct work_busfault;

2
drivers/gpu/arm/midgard/jm/mali_kbase_jm_js.h
View File

@ -906,7 +906,7 @@ static inline void kbase_js_runpool_dec_context_count(struct kbase_device *kbdev
*/
static inline void kbase_js_sched_all(struct kbase_device *kbdev)
{
kbase_js_sched(kbdev, (1 << kbdev->gpu_props.num_job_slots) - 1);
kbase_js_sched(kbdev, (1U << kbdev->gpu_props.num_job_slots) - 1U);
}
extern const int kbasep_js_atom_priority_to_relative[BASE_JD_NR_PRIO_LEVELS];

403
drivers/gpu/arm/midgard/mali_base_hwconfig_issues.h
View File

@ -66,9 +66,12 @@ enum base_hw_issue {
BASE_HW_ISSUE_GPU2021PRO_290,
BASE_HW_ISSUE_TITANHW_2710,
BASE_HW_ISSUE_TITANHW_2679,
BASE_HW_ISSUE_TITANHW_2922,
BASE_HW_ISSUE_GPU2022PRO_148,
BASE_HW_ISSUE_TITANHW_2922,
BASE_HW_ISSUE_TITANHW_2952,
BASE_HW_ISSUE_KRAKEHW_2151,
BASE_HW_ISSUE_TITANHW_2938,
BASE_HW_ISSUE_KRAKEHW_2269,
BASE_HW_ISSUE_END
};
@ -82,7 +85,7 @@ __attribute__((unused)) static const enum base_hw_issue base_hw_issues_tMIx_r0p0
BASE_HW_ISSUE_TMIX_8343, BASE_HW_ISSUE_TMIX_8463, BASE_HW_ISSUE_TMIX_8456,
BASE_HW_ISSUE_TMIX_8438, BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TTRX_921,
BASE_HW_ISSUE_GPU2017_1336, BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_GPU2022PRO_148,
BASE_HW_ISSUE_END
BASE_HW_ISSUE_TITANHW_2938, BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tMIx_r0p0[] = {
@ -92,7 +95,7 @@ __attribute__((unused)) static const enum base_hw_issue base_hw_issues_tMIx_r0p0
BASE_HW_ISSUE_TMIX_8343, BASE_HW_ISSUE_TMIX_8463, BASE_HW_ISSUE_TMIX_8456,
BASE_HW_ISSUE_TMIX_8438, BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TTRX_921,
BASE_HW_ISSUE_GPU2017_1336, BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_GPU2022PRO_148,
BASE_HW_ISSUE_END
BASE_HW_ISSUE_TITANHW_2938, BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tMIx_r0p1[] = {
@ -102,129 +105,139 @@ __attribute__((unused)) static const enum base_hw_issue base_hw_issues_tMIx_r0p1
BASE_HW_ISSUE_TMIX_8343, BASE_HW_ISSUE_TMIX_8463, BASE_HW_ISSUE_TMIX_8456,
BASE_HW_ISSUE_TMIX_8438, BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TTRX_921,
BASE_HW_ISSUE_GPU2017_1336, BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_GPU2022PRO_148,
BASE_HW_ISSUE_END
BASE_HW_ISSUE_TITANHW_2938, BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_model_tMIx[] = {
BASE_HW_ISSUE_5736, BASE_HW_ISSUE_9435, BASE_HW_ISSUE_TMIX_7891,
BASE_HW_ISSUE_TMIX_7940, BASE_HW_ISSUE_TMIX_8042, BASE_HW_ISSUE_TMIX_8133,
BASE_HW_ISSUE_TMIX_8138, BASE_HW_ISSUE_TMIX_8206, BASE_HW_ISSUE_TMIX_8343,
BASE_HW_ISSUE_TMIX_8456, BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TITANHW_2710,
BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_END
BASE_HW_ISSUE_5736, BASE_HW_ISSUE_9435, BASE_HW_ISSUE_TMIX_7891,
BASE_HW_ISSUE_TMIX_7940, BASE_HW_ISSUE_TMIX_8042, BASE_HW_ISSUE_TMIX_8133,
BASE_HW_ISSUE_TMIX_8138, BASE_HW_ISSUE_TMIX_8206, BASE_HW_ISSUE_TMIX_8343,
BASE_HW_ISSUE_TMIX_8456, BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TITANHW_2710,
BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_TITANHW_2938, BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tHEx_r0p0[] = {
BASE_HW_ISSUE_9435, BASE_HW_ISSUE_10682, BASE_HW_ISSUE_11054,
BASE_HW_ISSUE_TMIX_7891, BASE_HW_ISSUE_TMIX_8042, BASE_HW_ISSUE_TMIX_8133,
BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_GPU2017_1336,
BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_END
BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_TITANHW_2938,
BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tHEx_r0p1[] = {
BASE_HW_ISSUE_9435, BASE_HW_ISSUE_10682, BASE_HW_ISSUE_11054,
BASE_HW_ISSUE_TMIX_7891, BASE_HW_ISSUE_TMIX_8042, BASE_HW_ISSUE_TMIX_8133,
BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_GPU2017_1336,
BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_END
BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_TITANHW_2938,
BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tHEx_r0p2[] = {
BASE_HW_ISSUE_9435, BASE_HW_ISSUE_10682, BASE_HW_ISSUE_11054,
BASE_HW_ISSUE_TMIX_7891, BASE_HW_ISSUE_TMIX_8042, BASE_HW_ISSUE_TMIX_8133,
BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_GPU2017_1336,
BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_END
BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_TITANHW_2938,
BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tHEx_r0p3[] = {
BASE_HW_ISSUE_9435, BASE_HW_ISSUE_10682, BASE_HW_ISSUE_TMIX_7891,
BASE_HW_ISSUE_TMIX_8042, BASE_HW_ISSUE_TMIX_8133, BASE_HW_ISSUE_TSIX_2033,
BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_GPU2017_1336, BASE_HW_ISSUE_TITANHW_2710,
BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_END
BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_TITANHW_2938, BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_model_tHEx[] = {
BASE_HW_ISSUE_5736, BASE_HW_ISSUE_9435, BASE_HW_ISSUE_TMIX_7891,
BASE_HW_ISSUE_TMIX_8042, BASE_HW_ISSUE_TMIX_8133, BASE_HW_ISSUE_TSIX_2033,
BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_END
BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_TITANHW_2938,
BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tSIx_r0p0[] = {
BASE_HW_ISSUE_9435, BASE_HW_ISSUE_11054, BASE_HW_ISSUE_TMIX_8133,
BASE_HW_ISSUE_TSIX_1116, BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TSIX_1792,
BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_GPU2017_1336, BASE_HW_ISSUE_TTRX_3464,
BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_END
BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_TITANHW_2938,
BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tSIx_r0p1[] = {
BASE_HW_ISSUE_9435, BASE_HW_ISSUE_11054, BASE_HW_ISSUE_TMIX_8133,
BASE_HW_ISSUE_TSIX_1116, BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TSIX_1792,
BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_GPU2017_1336, BASE_HW_ISSUE_TTRX_3464,
BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_END
BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_TITANHW_2938,
BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tSIx_r1p0[] = {
BASE_HW_ISSUE_9435, BASE_HW_ISSUE_11054, BASE_HW_ISSUE_TMIX_8133,
BASE_HW_ISSUE_TSIX_1116, BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TTRX_921,
BASE_HW_ISSUE_GPU2017_1336, BASE_HW_ISSUE_TTRX_3464, BASE_HW_ISSUE_TITANHW_2710,
BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_END
BASE_HW_ISSUE_9435, BASE_HW_ISSUE_11054, BASE_HW_ISSUE_TMIX_8133,
BASE_HW_ISSUE_TSIX_1116, BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TTRX_921,
BASE_HW_ISSUE_GPU2017_1336, BASE_HW_ISSUE_TTRX_3464, BASE_HW_ISSUE_TITANHW_2710,
BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_TITANHW_2938, BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tSIx_r1p1[] = {
BASE_HW_ISSUE_9435, BASE_HW_ISSUE_TMIX_8133, BASE_HW_ISSUE_TSIX_1116,
BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_GPU2017_1336,
BASE_HW_ISSUE_TTRX_3464, BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_GPU2022PRO_148,
BASE_HW_ISSUE_END
BASE_HW_ISSUE_9435, BASE_HW_ISSUE_TMIX_8133, BASE_HW_ISSUE_TSIX_1116,
BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_GPU2017_1336,
BASE_HW_ISSUE_TTRX_3464, BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_GPU2022PRO_148,
BASE_HW_ISSUE_TITANHW_2938, BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_model_tSIx[] = {
BASE_HW_ISSUE_5736, BASE_HW_ISSUE_9435, BASE_HW_ISSUE_TMIX_8133,
BASE_HW_ISSUE_TSIX_1116, BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TTRX_3464,
BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_END
BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_TITANHW_2938,
BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tDVx_r0p0[] = {
BASE_HW_ISSUE_9435, BASE_HW_ISSUE_TMIX_8133, BASE_HW_ISSUE_TSIX_1116,
BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_GPU2017_1336,
BASE_HW_ISSUE_TTRX_3464, BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_GPU2022PRO_148,
BASE_HW_ISSUE_END
BASE_HW_ISSUE_9435, BASE_HW_ISSUE_TMIX_8133, BASE_HW_ISSUE_TSIX_1116,
BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_GPU2017_1336,
BASE_HW_ISSUE_TTRX_3464, BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_GPU2022PRO_148,
BASE_HW_ISSUE_TITANHW_2938, BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_model_tDVx[] = {
BASE_HW_ISSUE_5736, BASE_HW_ISSUE_9435, BASE_HW_ISSUE_TMIX_8133,
BASE_HW_ISSUE_TSIX_1116, BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TTRX_3464,
BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_END
BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_TITANHW_2938,
BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tNOx_r0p0[] = {
BASE_HW_ISSUE_9435, BASE_HW_ISSUE_TMIX_8133, BASE_HW_ISSUE_TSIX_1116,
BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TNOX_1194, BASE_HW_ISSUE_TTRX_921,
BASE_HW_ISSUE_GPU2017_1336, BASE_HW_ISSUE_TTRX_3464, BASE_HW_ISSUE_TITANHW_2710,
BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_END
BASE_HW_ISSUE_9435, BASE_HW_ISSUE_TMIX_8133, BASE_HW_ISSUE_TSIX_1116,
BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TNOX_1194, BASE_HW_ISSUE_TTRX_921,
BASE_HW_ISSUE_GPU2017_1336, BASE_HW_ISSUE_TTRX_3464, BASE_HW_ISSUE_TITANHW_2710,
BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_TITANHW_2938, BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_model_tNOx[] = {
BASE_HW_ISSUE_5736, BASE_HW_ISSUE_9435, BASE_HW_ISSUE_TMIX_8133,
BASE_HW_ISSUE_TSIX_1116, BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TTRX_3464,
BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_END
BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_TITANHW_2938,
BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tGOx_r0p0[] = {
BASE_HW_ISSUE_9435, BASE_HW_ISSUE_TMIX_8133, BASE_HW_ISSUE_TSIX_1116,
BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TNOX_1194, BASE_HW_ISSUE_TTRX_921,
BASE_HW_ISSUE_GPU2017_1336, BASE_HW_ISSUE_TTRX_3464, BASE_HW_ISSUE_TITANHW_2710,
BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_END
BASE_HW_ISSUE_9435, BASE_HW_ISSUE_TMIX_8133, BASE_HW_ISSUE_TSIX_1116,
BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TNOX_1194, BASE_HW_ISSUE_TTRX_921,
BASE_HW_ISSUE_GPU2017_1336, BASE_HW_ISSUE_TTRX_3464, BASE_HW_ISSUE_TITANHW_2710,
BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_TITANHW_2938, BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tGOx_r1p0[] = {
BASE_HW_ISSUE_9435, BASE_HW_ISSUE_TMIX_8133, BASE_HW_ISSUE_TSIX_1116,
BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TGOX_R1_1234, BASE_HW_ISSUE_TTRX_921,
BASE_HW_ISSUE_GPU2017_1336, BASE_HW_ISSUE_TTRX_3464, BASE_HW_ISSUE_TITANHW_2710,
BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_END
BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_TITANHW_2938, BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_model_tGOx[] = {
BASE_HW_ISSUE_5736, BASE_HW_ISSUE_9435, BASE_HW_ISSUE_TMIX_8133,
BASE_HW_ISSUE_TSIX_1116, BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TTRX_3464,
BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_END
BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_TITANHW_2938,
BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tTRx_r0p0[] = {
@ -235,7 +248,7 @@ __attribute__((unused)) static const enum base_hw_issue base_hw_issues_tTRx_r0p0
BASE_HW_ISSUE_TTRX_3083, BASE_HW_ISSUE_TTRX_3470,
BASE_HW_ISSUE_TTRX_3464, BASE_HW_ISSUE_TTRX_3485,
BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_GPU2022PRO_148,
BASE_HW_ISSUE_END
BASE_HW_ISSUE_TITANHW_2938, BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tTRx_r0p1[] = {
@ -246,24 +259,32 @@ __attribute__((unused)) static const enum base_hw_issue base_hw_issues_tTRx_r0p1
BASE_HW_ISSUE_TTRX_3083, BASE_HW_ISSUE_TTRX_3470,
BASE_HW_ISSUE_TTRX_3464, BASE_HW_ISSUE_TTRX_3485,
BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_GPU2022PRO_148,
BASE_HW_ISSUE_END
BASE_HW_ISSUE_TITANHW_2938, BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tTRx_r0p2[] = {
BASE_HW_ISSUE_9435, BASE_HW_ISSUE_TSIX_2033,
BASE_HW_ISSUE_TTRX_1337, BASE_HW_ISSUE_TTRX_2968_TTRX_3162,
BASE_HW_ISSUE_TTRX_3076, BASE_HW_ISSUE_TTRX_921,
BASE_HW_ISSUE_TTRX_3414, BASE_HW_ISSUE_GPU2017_1336,
BASE_HW_ISSUE_TTRX_3083, BASE_HW_ISSUE_TTRX_3470,
BASE_HW_ISSUE_TTRX_3464, BASE_HW_ISSUE_TITANHW_2710,
BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_END
BASE_HW_ISSUE_9435,
BASE_HW_ISSUE_TSIX_2033,
BASE_HW_ISSUE_TTRX_1337,
BASE_HW_ISSUE_TTRX_2968_TTRX_3162,
BASE_HW_ISSUE_TTRX_3076,
BASE_HW_ISSUE_TTRX_921,
BASE_HW_ISSUE_TTRX_3414,
BASE_HW_ISSUE_GPU2017_1336,
BASE_HW_ISSUE_TTRX_3083,
BASE_HW_ISSUE_TTRX_3470,
BASE_HW_ISSUE_TTRX_3464,
BASE_HW_ISSUE_TITANHW_2710,
BASE_HW_ISSUE_GPU2022PRO_148,
BASE_HW_ISSUE_TITANHW_2938,
BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_model_tTRx[] = {
BASE_HW_ISSUE_5736, BASE_HW_ISSUE_9435, BASE_HW_ISSUE_TSIX_2033,
BASE_HW_ISSUE_TTRX_1337, BASE_HW_ISSUE_TTRX_3414, BASE_HW_ISSUE_TTRX_3083,
BASE_HW_ISSUE_TTRX_3470, BASE_HW_ISSUE_TTRX_3464, BASE_HW_ISSUE_TITANHW_2710,
BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_END
BASE_HW_ISSUE_5736, BASE_HW_ISSUE_9435, BASE_HW_ISSUE_TSIX_2033,
BASE_HW_ISSUE_TTRX_1337, BASE_HW_ISSUE_TTRX_3414, BASE_HW_ISSUE_TTRX_3083,
BASE_HW_ISSUE_TTRX_3470, BASE_HW_ISSUE_TTRX_3464, BASE_HW_ISSUE_TITANHW_2710,
BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_TITANHW_2938, BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tNAx_r0p0[] = {
@ -274,24 +295,32 @@ __attribute__((unused)) static const enum base_hw_issue base_hw_issues_tNAx_r0p0
BASE_HW_ISSUE_TTRX_3083, BASE_HW_ISSUE_TTRX_3470,
BASE_HW_ISSUE_TTRX_3464, BASE_HW_ISSUE_TTRX_3485,
BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_GPU2022PRO_148,
BASE_HW_ISSUE_END
BASE_HW_ISSUE_TITANHW_2938, BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tNAx_r0p1[] = {
BASE_HW_ISSUE_9435, BASE_HW_ISSUE_TSIX_2033,
BASE_HW_ISSUE_TTRX_1337, BASE_HW_ISSUE_TTRX_2968_TTRX_3162,
BASE_HW_ISSUE_TTRX_3076, BASE_HW_ISSUE_TTRX_921,
BASE_HW_ISSUE_TTRX_3414, BASE_HW_ISSUE_GPU2017_1336,
BASE_HW_ISSUE_TTRX_3083, BASE_HW_ISSUE_TTRX_3470,
BASE_HW_ISSUE_TTRX_3464, BASE_HW_ISSUE_TITANHW_2710,
BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_END
BASE_HW_ISSUE_9435,
BASE_HW_ISSUE_TSIX_2033,
BASE_HW_ISSUE_TTRX_1337,
BASE_HW_ISSUE_TTRX_2968_TTRX_3162,
BASE_HW_ISSUE_TTRX_3076,
BASE_HW_ISSUE_TTRX_921,
BASE_HW_ISSUE_TTRX_3414,
BASE_HW_ISSUE_GPU2017_1336,
BASE_HW_ISSUE_TTRX_3083,
BASE_HW_ISSUE_TTRX_3470,
BASE_HW_ISSUE_TTRX_3464,
BASE_HW_ISSUE_TITANHW_2710,
BASE_HW_ISSUE_GPU2022PRO_148,
BASE_HW_ISSUE_TITANHW_2938,
BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_model_tNAx[] = {
BASE_HW_ISSUE_5736, BASE_HW_ISSUE_9435, BASE_HW_ISSUE_TSIX_2033,
BASE_HW_ISSUE_TTRX_1337, BASE_HW_ISSUE_TTRX_3414, BASE_HW_ISSUE_TTRX_3083,
BASE_HW_ISSUE_TTRX_3470, BASE_HW_ISSUE_TTRX_3464, BASE_HW_ISSUE_TITANHW_2710,
BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_END
BASE_HW_ISSUE_5736, BASE_HW_ISSUE_9435, BASE_HW_ISSUE_TSIX_2033,
BASE_HW_ISSUE_TTRX_1337, BASE_HW_ISSUE_TTRX_3414, BASE_HW_ISSUE_TTRX_3083,
BASE_HW_ISSUE_TTRX_3470, BASE_HW_ISSUE_TTRX_3464, BASE_HW_ISSUE_TITANHW_2710,
BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_TITANHW_2938, BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tBEx_r0p0[] = {
@ -301,41 +330,62 @@ __attribute__((unused)) static const enum base_hw_issue base_hw_issues_tBEx_r0p0
BASE_HW_ISSUE_TTRX_3083, BASE_HW_ISSUE_TTRX_3470,
BASE_HW_ISSUE_TTRX_3464, BASE_HW_ISSUE_TTRX_3485,
BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_GPU2022PRO_148,
BASE_HW_ISSUE_END
BASE_HW_ISSUE_TITANHW_2938, BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tBEx_r0p1[] = {
BASE_HW_ISSUE_9435, BASE_HW_ISSUE_TSIX_2033,
BASE_HW_ISSUE_TTRX_1337, BASE_HW_ISSUE_TTRX_2968_TTRX_3162,
BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_TTRX_3414,
BASE_HW_ISSUE_TTRX_3083, BASE_HW_ISSUE_TTRX_3470,
BASE_HW_ISSUE_TTRX_3464, BASE_HW_ISSUE_TITANHW_2710,
BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_END
BASE_HW_ISSUE_9435,
BASE_HW_ISSUE_TSIX_2033,
BASE_HW_ISSUE_TTRX_1337,
BASE_HW_ISSUE_TTRX_2968_TTRX_3162,
BASE_HW_ISSUE_TTRX_921,
BASE_HW_ISSUE_TTRX_3414,
BASE_HW_ISSUE_TTRX_3083,
BASE_HW_ISSUE_TTRX_3470,
BASE_HW_ISSUE_TTRX_3464,
BASE_HW_ISSUE_TITANHW_2710,
BASE_HW_ISSUE_GPU2022PRO_148,
BASE_HW_ISSUE_TITANHW_2938,
BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tBEx_r1p0[] = {
BASE_HW_ISSUE_9435, BASE_HW_ISSUE_TSIX_2033,
BASE_HW_ISSUE_TTRX_1337, BASE_HW_ISSUE_TTRX_2968_TTRX_3162,
BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_TTRX_3414,
BASE_HW_ISSUE_TTRX_3083, BASE_HW_ISSUE_TTRX_3470,
BASE_HW_ISSUE_TTRX_3464, BASE_HW_ISSUE_TITANHW_2710,
BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_END
BASE_HW_ISSUE_9435,
BASE_HW_ISSUE_TSIX_2033,
BASE_HW_ISSUE_TTRX_1337,
BASE_HW_ISSUE_TTRX_2968_TTRX_3162,
BASE_HW_ISSUE_TTRX_921,
BASE_HW_ISSUE_TTRX_3414,
BASE_HW_ISSUE_TTRX_3083,
BASE_HW_ISSUE_TTRX_3470,
BASE_HW_ISSUE_TTRX_3464,
BASE_HW_ISSUE_TITANHW_2710,
BASE_HW_ISSUE_GPU2022PRO_148,
BASE_HW_ISSUE_TITANHW_2938,
BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tBEx_r1p1[] = {
BASE_HW_ISSUE_9435, BASE_HW_ISSUE_TSIX_2033,
BASE_HW_ISSUE_TTRX_1337, BASE_HW_ISSUE_TTRX_2968_TTRX_3162,
BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_TTRX_3414,
BASE_HW_ISSUE_TTRX_3083, BASE_HW_ISSUE_TTRX_3470,
BASE_HW_ISSUE_TTRX_3464, BASE_HW_ISSUE_TITANHW_2710,
BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_END
BASE_HW_ISSUE_9435,
BASE_HW_ISSUE_TSIX_2033,
BASE_HW_ISSUE_TTRX_1337,
BASE_HW_ISSUE_TTRX_2968_TTRX_3162,
BASE_HW_ISSUE_TTRX_921,
BASE_HW_ISSUE_TTRX_3414,
BASE_HW_ISSUE_TTRX_3083,
BASE_HW_ISSUE_TTRX_3470,
BASE_HW_ISSUE_TTRX_3464,
BASE_HW_ISSUE_TITANHW_2710,
BASE_HW_ISSUE_GPU2022PRO_148,
BASE_HW_ISSUE_TITANHW_2938,
BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_model_tBEx[] = {
BASE_HW_ISSUE_5736, BASE_HW_ISSUE_9435, BASE_HW_ISSUE_TSIX_2033,
BASE_HW_ISSUE_TTRX_1337, BASE_HW_ISSUE_TTRX_3414, BASE_HW_ISSUE_TTRX_3083,
BASE_HW_ISSUE_TTRX_3470, BASE_HW_ISSUE_TTRX_3464, BASE_HW_ISSUE_TITANHW_2710,
BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_END
BASE_HW_ISSUE_5736, BASE_HW_ISSUE_9435, BASE_HW_ISSUE_TSIX_2033,
BASE_HW_ISSUE_TTRX_1337, BASE_HW_ISSUE_TTRX_3414, BASE_HW_ISSUE_TTRX_3083,
BASE_HW_ISSUE_TTRX_3470, BASE_HW_ISSUE_TTRX_3464, BASE_HW_ISSUE_TITANHW_2710,
BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_TITANHW_2938, BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_lBEx_r1p0[] = {
@ -345,152 +395,223 @@ __attribute__((unused)) static const enum base_hw_issue base_hw_issues_lBEx_r1p0
BASE_HW_ISSUE_TTRX_3083, BASE_HW_ISSUE_TTRX_3470,
BASE_HW_ISSUE_TTRX_3464, BASE_HW_ISSUE_TTRX_3485,
BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_GPU2022PRO_148,
BASE_HW_ISSUE_END
BASE_HW_ISSUE_TITANHW_2938, BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_lBEx_r1p1[] = {
BASE_HW_ISSUE_9435, BASE_HW_ISSUE_TSIX_2033,
BASE_HW_ISSUE_TTRX_1337, BASE_HW_ISSUE_TTRX_2968_TTRX_3162,
BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_TTRX_3414,
BASE_HW_ISSUE_TTRX_3083, BASE_HW_ISSUE_TTRX_3470,
BASE_HW_ISSUE_TTRX_3464, BASE_HW_ISSUE_TITANHW_2710,
BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_END
BASE_HW_ISSUE_9435,
BASE_HW_ISSUE_TSIX_2033,
BASE_HW_ISSUE_TTRX_1337,
BASE_HW_ISSUE_TTRX_2968_TTRX_3162,
BASE_HW_ISSUE_TTRX_921,
BASE_HW_ISSUE_TTRX_3414,
BASE_HW_ISSUE_TTRX_3083,
BASE_HW_ISSUE_TTRX_3470,
BASE_HW_ISSUE_TTRX_3464,
BASE_HW_ISSUE_TITANHW_2710,
BASE_HW_ISSUE_GPU2022PRO_148,
BASE_HW_ISSUE_TITANHW_2938,
BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tBAx_r0p0[] = {
BASE_HW_ISSUE_9435, BASE_HW_ISSUE_TSIX_2033,
BASE_HW_ISSUE_TTRX_1337, BASE_HW_ISSUE_TTRX_2968_TTRX_3162,
BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_TTRX_3414,
BASE_HW_ISSUE_TTRX_3083, BASE_HW_ISSUE_TTRX_3470,
BASE_HW_ISSUE_TTRX_3464, BASE_HW_ISSUE_TITANHW_2710,
BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_END
BASE_HW_ISSUE_9435,
BASE_HW_ISSUE_TSIX_2033,
BASE_HW_ISSUE_TTRX_1337,
BASE_HW_ISSUE_TTRX_2968_TTRX_3162,
BASE_HW_ISSUE_TTRX_921,
BASE_HW_ISSUE_TTRX_3414,
BASE_HW_ISSUE_TTRX_3083,
BASE_HW_ISSUE_TTRX_3470,
BASE_HW_ISSUE_TTRX_3464,
BASE_HW_ISSUE_TITANHW_2710,
BASE_HW_ISSUE_GPU2022PRO_148,
BASE_HW_ISSUE_TITANHW_2938,
BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tBAx_r0p1[] = {
BASE_HW_ISSUE_9435,
BASE_HW_ISSUE_TSIX_2033,
BASE_HW_ISSUE_TTRX_1337,
BASE_HW_ISSUE_TTRX_2968_TTRX_3162,
BASE_HW_ISSUE_TTRX_921,
BASE_HW_ISSUE_TTRX_3414,
BASE_HW_ISSUE_TTRX_3083,
BASE_HW_ISSUE_TTRX_3470,
BASE_HW_ISSUE_TTRX_3464,
BASE_HW_ISSUE_TITANHW_2710,
BASE_HW_ISSUE_GPU2022PRO_148,
BASE_HW_ISSUE_TITANHW_2938,
BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tBAx_r0p2[] = {
BASE_HW_ISSUE_9435,
BASE_HW_ISSUE_TSIX_2033,
BASE_HW_ISSUE_TTRX_1337,
BASE_HW_ISSUE_TTRX_2968_TTRX_3162,
BASE_HW_ISSUE_TTRX_921,
BASE_HW_ISSUE_TTRX_3414,
BASE_HW_ISSUE_TTRX_3083,
BASE_HW_ISSUE_TTRX_3470,
BASE_HW_ISSUE_TTRX_3464,
BASE_HW_ISSUE_TITANHW_2710,
BASE_HW_ISSUE_GPU2022PRO_148,
BASE_HW_ISSUE_TITANHW_2938,
BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tBAx_r1p0[] = {
BASE_HW_ISSUE_9435, BASE_HW_ISSUE_TSIX_2033,
BASE_HW_ISSUE_TTRX_1337, BASE_HW_ISSUE_TTRX_2968_TTRX_3162,
BASE_HW_ISSUE_TTRX_921, BASE_HW_ISSUE_TTRX_3414,
BASE_HW_ISSUE_TTRX_3083, BASE_HW_ISSUE_TTRX_3470,
BASE_HW_ISSUE_TTRX_3464, BASE_HW_ISSUE_TITANHW_2710,
BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_END
BASE_HW_ISSUE_9435,
BASE_HW_ISSUE_TSIX_2033,
BASE_HW_ISSUE_TTRX_1337,
BASE_HW_ISSUE_TTRX_2968_TTRX_3162,
BASE_HW_ISSUE_TTRX_921,
BASE_HW_ISSUE_TTRX_3414,
BASE_HW_ISSUE_TTRX_3083,
BASE_HW_ISSUE_TTRX_3470,
BASE_HW_ISSUE_TTRX_3464,
BASE_HW_ISSUE_TITANHW_2710,
BASE_HW_ISSUE_GPU2022PRO_148,
BASE_HW_ISSUE_TITANHW_2938,
BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_model_tBAx[] = {
BASE_HW_ISSUE_5736, BASE_HW_ISSUE_9435, BASE_HW_ISSUE_TSIX_2033,
BASE_HW_ISSUE_TTRX_1337, BASE_HW_ISSUE_TTRX_3414, BASE_HW_ISSUE_TTRX_3083,
BASE_HW_ISSUE_TTRX_3470, BASE_HW_ISSUE_TTRX_3464, BASE_HW_ISSUE_TITANHW_2710,
BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_END
BASE_HW_ISSUE_5736, BASE_HW_ISSUE_9435, BASE_HW_ISSUE_TSIX_2033,
BASE_HW_ISSUE_TTRX_1337, BASE_HW_ISSUE_TTRX_3414, BASE_HW_ISSUE_TTRX_3083,
BASE_HW_ISSUE_TTRX_3470, BASE_HW_ISSUE_TTRX_3464, BASE_HW_ISSUE_TITANHW_2710,
BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_TITANHW_2938, BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tODx_r0p0[] = {
BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TTRX_1337, BASE_HW_ISSUE_GPU2019_3212,
BASE_HW_ISSUE_GPU2019_3878, BASE_HW_ISSUE_GPU2019_3901, BASE_HW_ISSUE_TITANHW_2710,
BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_END
BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_TITANHW_2938, BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_model_tODx[] = {
BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TTRX_1337, BASE_HW_ISSUE_GPU2019_3212,
BASE_HW_ISSUE_GPU2019_3878, BASE_HW_ISSUE_GPU2019_3901, BASE_HW_ISSUE_TITANHW_2710,
BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_END
BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_TITANHW_2938, BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tGRx_r0p0[] = {
BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TTRX_1337, BASE_HW_ISSUE_GPU2019_3878,
BASE_HW_ISSUE_GPU2019_3901, BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_GPU2022PRO_148,
BASE_HW_ISSUE_END
BASE_HW_ISSUE_TITANHW_2938, BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_model_tGRx[] = {
BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TTRX_1337, BASE_HW_ISSUE_GPU2019_3878,
BASE_HW_ISSUE_GPU2019_3901, BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_GPU2022PRO_148,
BASE_HW_ISSUE_END
BASE_HW_ISSUE_TITANHW_2938, BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tVAx_r0p0[] = {
BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TTRX_1337, BASE_HW_ISSUE_GPU2019_3878,
BASE_HW_ISSUE_GPU2019_3901, BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_GPU2022PRO_148,
BASE_HW_ISSUE_END
BASE_HW_ISSUE_TITANHW_2938, BASE_HW_ISSUE_TITANHW_2938, BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_model_tVAx[] = {
BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TTRX_1337, BASE_HW_ISSUE_GPU2019_3878,
BASE_HW_ISSUE_GPU2019_3901, BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_GPU2022PRO_148,
BASE_HW_ISSUE_END
BASE_HW_ISSUE_TITANHW_2938, BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tTUx_r0p0[] = {
BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TTRX_1337, BASE_HW_ISSUE_TURSEHW_1997,
BASE_HW_ISSUE_GPU2019_3878, BASE_HW_ISSUE_TURSEHW_2716, BASE_HW_ISSUE_GPU2019_3901,
BASE_HW_ISSUE_GPU2021PRO_290, BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_TITANHW_2679,
BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_END
BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_TITANHW_2938, BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tTUx_r0p1[] = {
BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TTRX_1337, BASE_HW_ISSUE_TURSEHW_1997,
BASE_HW_ISSUE_GPU2019_3878, BASE_HW_ISSUE_TURSEHW_2716, BASE_HW_ISSUE_GPU2019_3901,
BASE_HW_ISSUE_GPU2021PRO_290, BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_TITANHW_2679,
BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_TITANHW_2922, BASE_HW_ISSUE_END
BASE_HW_ISSUE_TSIX_2033,
BASE_HW_ISSUE_TTRX_1337,
BASE_HW_ISSUE_TURSEHW_1997,
BASE_HW_ISSUE_GPU2019_3878,
BASE_HW_ISSUE_TURSEHW_2716,
BASE_HW_ISSUE_GPU2019_3901,
BASE_HW_ISSUE_GPU2021PRO_290,
BASE_HW_ISSUE_TITANHW_2710,
BASE_HW_ISSUE_TITANHW_2679,
BASE_HW_ISSUE_GPU2022PRO_148,
BASE_HW_ISSUE_TITANHW_2922,
BASE_HW_ISSUE_TITANHW_2938,
BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_model_tTUx[] = {
BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TTRX_1337, BASE_HW_ISSUE_GPU2019_3878,
BASE_HW_ISSUE_TURSEHW_2716, BASE_HW_ISSUE_GPU2019_3901, BASE_HW_ISSUE_GPU2021PRO_290,
BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_TITANHW_2679, BASE_HW_ISSUE_GPU2022PRO_148,
BASE_HW_ISSUE_TITANHW_2922, BASE_HW_ISSUE_END
BASE_HW_ISSUE_TITANHW_2922, BASE_HW_ISSUE_TITANHW_2938, BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tTUx_r1p0[] = {
BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TTRX_1337, BASE_HW_ISSUE_GPU2019_3878,
BASE_HW_ISSUE_TURSEHW_2716, BASE_HW_ISSUE_GPU2019_3901, BASE_HW_ISSUE_GPU2021PRO_290,
BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_TITANHW_2679, BASE_HW_ISSUE_GPU2022PRO_148,
BASE_HW_ISSUE_TITANHW_2922, BASE_HW_ISSUE_END
BASE_HW_ISSUE_TITANHW_2922, BASE_HW_ISSUE_TITANHW_2938, BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tTUx_r1p1[] = {
BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TTRX_1337, BASE_HW_ISSUE_GPU2019_3878,
BASE_HW_ISSUE_TURSEHW_2716, BASE_HW_ISSUE_GPU2019_3901, BASE_HW_ISSUE_GPU2021PRO_290,
BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_TITANHW_2679, BASE_HW_ISSUE_GPU2022PRO_148,
BASE_HW_ISSUE_TITANHW_2922, BASE_HW_ISSUE_END
BASE_HW_ISSUE_TITANHW_2922, BASE_HW_ISSUE_TITANHW_2938, BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tTUx_r1p2[] = {
BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TTRX_1337, BASE_HW_ISSUE_GPU2019_3878,
BASE_HW_ISSUE_TURSEHW_2716, BASE_HW_ISSUE_GPU2019_3901, BASE_HW_ISSUE_GPU2021PRO_290,
BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_TITANHW_2679, BASE_HW_ISSUE_GPU2022PRO_148,
BASE_HW_ISSUE_TITANHW_2922, BASE_HW_ISSUE_END
BASE_HW_ISSUE_TITANHW_2922, BASE_HW_ISSUE_TITANHW_2938, BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tTUx_r1p3[] = {
BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TTRX_1337, BASE_HW_ISSUE_GPU2019_3878,
BASE_HW_ISSUE_TURSEHW_2716, BASE_HW_ISSUE_GPU2019_3901, BASE_HW_ISSUE_GPU2021PRO_290,
BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_TITANHW_2679, BASE_HW_ISSUE_GPU2022PRO_148,
BASE_HW_ISSUE_TITANHW_2922, BASE_HW_ISSUE_END
BASE_HW_ISSUE_TITANHW_2922, BASE_HW_ISSUE_TITANHW_2938, BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_model_tTIx[] = {
BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TTRX_1337,
BASE_HW_ISSUE_TURSEHW_2716, BASE_HW_ISSUE_GPU2021PRO_290,
BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_TITANHW_2679,
BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_TITANHW_2922,
BASE_HW_ISSUE_TITANHW_2952, BASE_HW_ISSUE_END
BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TTRX_1337, BASE_HW_ISSUE_TURSEHW_2716,
BASE_HW_ISSUE_GPU2021PRO_290, BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_TITANHW_2679,
BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_TITANHW_2922, BASE_HW_ISSUE_TITANHW_2952,
BASE_HW_ISSUE_TITANHW_2938, BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tTIx_r0p0[] = {
BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TTRX_1337,
BASE_HW_ISSUE_TURSEHW_2716, BASE_HW_ISSUE_GPU2021PRO_290,
BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_TITANHW_2679,
BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_TITANHW_2922,
BASE_HW_ISSUE_TITANHW_2952, BASE_HW_ISSUE_END
BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TTRX_1337, BASE_HW_ISSUE_TURSEHW_2716,
BASE_HW_ISSUE_GPU2021PRO_290, BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_TITANHW_2679,
BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_TITANHW_2922, BASE_HW_ISSUE_TITANHW_2952,
BASE_HW_ISSUE_TITANHW_2938, BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tTIx_r0p1[] = {
BASE_HW_ISSUE_TSIX_2033, BASE_HW_ISSUE_TTRX_1337, BASE_HW_ISSUE_TURSEHW_2716,
BASE_HW_ISSUE_GPU2021PRO_290, BASE_HW_ISSUE_TITANHW_2710, BASE_HW_ISSUE_TITANHW_2679,
BASE_HW_ISSUE_GPU2022PRO_148, BASE_HW_ISSUE_TITANHW_2938, BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tKRx_r0p0[] = {
BASE_HW_ISSUE_TTRX_1337, BASE_HW_ISSUE_TURSEHW_2716, BASE_HW_ISSUE_GPU2022PRO_148,
BASE_HW_ISSUE_KRAKEHW_2151, BASE_HW_ISSUE_KRAKEHW_2269, BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_tKRx_r0p1[] = {
BASE_HW_ISSUE_TTRX_1337, BASE_HW_ISSUE_TURSEHW_2716, BASE_HW_ISSUE_GPU2022PRO_148,
BASE_HW_ISSUE_END
BASE_HW_ISSUE_KRAKEHW_2269, BASE_HW_ISSUE_END
};
__attribute__((unused)) static const enum base_hw_issue base_hw_issues_model_tKRx[] = {
BASE_HW_ISSUE_TTRX_1337, BASE_HW_ISSUE_TURSEHW_2716, BASE_HW_ISSUE_GPU2022PRO_148,
BASE_HW_ISSUE_END
BASE_HW_ISSUE_TTRX_1337, BASE_HW_ISSUE_TURSEHW_2716, BASE_HW_ISSUE_GPU2022PRO_148,
BASE_HW_ISSUE_KRAKEHW_2151, BASE_HW_ISSUE_KRAKEHW_2269, BASE_HW_ISSUE_END
};

88
drivers/gpu/arm/midgard/mali_kbase.h
View File

@ -26,25 +26,6 @@
#include <mali_kbase_debug.h>
#include <linux/atomic.h>
#include <linux/highmem.h>
#include <linux/hrtimer.h>
#include <linux/ktime.h>
#include <linux/list.h>
#include <linux/mm.h>
#include <linux/mutex.h>
#include <linux/rwsem.h>
#include <linux/sched.h>
#if (KERNEL_VERSION(4, 11, 0) <= LINUX_VERSION_CODE)
#include <linux/sched/mm.h>
#endif
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/vmalloc.h>
#include <linux/wait.h>
#include <linux/workqueue.h>
#include <linux/interrupt.h>
#include <uapi/gpu/arm/midgard/mali_base_kernel.h>
#include <mali_kbase_linux.h>
#include <linux/version_compat_defs.h>
@ -75,18 +56,39 @@
#include "ipa/mali_kbase_ipa.h"
#if MALI_USE_CSF
#include "csf/mali_kbase_csf.h"
#endif
#if IS_ENABLED(CONFIG_GPU_TRACEPOINTS)
#include <trace/events/gpu.h>
#endif
#include "mali_linux_trace.h"
#include <linux/atomic.h>
#include <linux/highmem.h>
#include <linux/hrtimer.h>
#include <linux/ktime.h>
#include <linux/list.h>
#include <linux/mm.h>
#include <linux/mutex.h>
#include <linux/rwsem.h>
#include <linux/sched.h>
#if (KERNEL_VERSION(4, 11, 0) <= LINUX_VERSION_CODE)
#include <linux/sched/mm.h>
#endif
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/vmalloc.h>
#include <linux/wait.h>
#include <linux/workqueue.h>
#include <linux/interrupt.h>
#define KBASE_DRV_NAME "mali"
#define KBASE_TIMELINE_NAME KBASE_DRV_NAME ".timeline"
#if MALI_USE_CSF
#include "csf/mali_kbase_csf.h"
/* Physical memory group ID for CSF user I/O.
*/
#define KBASE_MEM_GROUP_CSF_IO BASE_MEM_GROUP_DEFAULT
@ -169,7 +171,16 @@ unsigned long kbase_context_get_unmapped_area(struct kbase_context *kctx, const
const unsigned long len, const unsigned long pgoff,
const unsigned long flags);
int assign_irqs(struct kbase_device *kbdev);
/**
* kbase_get_irqs() - Get GPU interrupts from the device tree.
*
* @kbdev: The kbase device structure of the device
*
* This function must be called once only when a kbase device is initialized.
*
* Return: 0 on success. Error code (negative) on failure.
*/
int kbase_get_irqs(struct kbase_device *kbdev);
int kbase_sysfs_init(struct kbase_device *kbdev);
void kbase_sysfs_term(struct kbase_device *kbdev);
@ -271,7 +282,7 @@ int kbase_jd_submit(struct kbase_context *kctx, void __user *user_addr, u32 nr_a
*/
void kbase_jd_done_worker(struct work_struct *data);
void kbase_jd_done(struct kbase_jd_atom *katom, int slot_nr, ktime_t *end_timestamp,
void kbase_jd_done(struct kbase_jd_atom *katom, unsigned int slot_nr, ktime_t *end_timestamp,
kbasep_js_atom_done_code done_code);
void kbase_jd_cancel(struct kbase_device *kbdev, struct kbase_jd_atom *katom);
void kbase_jd_zap_context(struct kbase_context *kctx);
@ -352,7 +363,7 @@ int kbase_job_slot_softstop_start_rp(struct kbase_context *kctx, struct kbase_va
*
* Where possible any job in the next register is evicted before the soft-stop.
*/
void kbase_job_slot_softstop(struct kbase_device *kbdev, int js,
void kbase_job_slot_softstop(struct kbase_device *kbdev, unsigned int js,
struct kbase_jd_atom *target_katom);
void kbase_job_slot_softstop_swflags(struct kbase_device *kbdev, unsigned int js,
@ -534,7 +545,7 @@ static inline void kbase_pm_set_gpu_lost(struct kbase_device *kbdev, bool gpu_lo
const int cur_val = atomic_xchg(&kbdev->pm.gpu_lost, new_val);
if (new_val != cur_val)
KBASE_KTRACE_ADD(kbdev, ARB_GPU_LOST, NULL, new_val);
KBASE_KTRACE_ADD(kbdev, ARB_GPU_LOST, NULL, (u64)new_val);
}
#endif
@ -636,16 +647,17 @@ int kbase_pm_force_mcu_wakeup_after_sleep(struct kbase_device *kbdev);
*
* Return: the atom's ID.
*/
static inline int kbase_jd_atom_id(struct kbase_context *kctx, const struct kbase_jd_atom *katom)
static inline unsigned int kbase_jd_atom_id(struct kbase_context *kctx,
const struct kbase_jd_atom *katom)
{
int result;
unsigned int result;
KBASE_DEBUG_ASSERT(kctx);
KBASE_DEBUG_ASSERT(katom);
KBASE_DEBUG_ASSERT(katom->kctx == kctx);
result = katom - &kctx->jctx.atoms[0];
KBASE_DEBUG_ASSERT(result >= 0 && result <= BASE_JD_ATOM_COUNT);
KBASE_DEBUG_ASSERT(result <= BASE_JD_ATOM_COUNT);
return result;
}
@ -767,6 +779,22 @@ int kbase_device_pcm_dev_init(struct kbase_device *const kbdev);
*/
void kbase_device_pcm_dev_term(struct kbase_device *const kbdev);
#if MALI_USE_CSF
/**
* kbasep_adjust_prioritized_process() - Adds or removes the specified PID from
* the list of prioritized processes.
*
* @kbdev: Pointer to the structure for the kbase device
* @add: True if the process should be prioritized, false otherwise
* @tgid: The process/thread group ID
*
* Return: true if the operation was successful, false otherwise
*/
bool kbasep_adjust_prioritized_process(struct kbase_device *kbdev, bool add, uint32_t tgid);
#endif /* MALI_USE_CSF */
/**
* KBASE_DISJOINT_STATE_INTERLEAVED_CONTEXT_COUNT_THRESHOLD - If a job is soft stopped
* and the number of contexts is >= this value it is reported as a disjoint event
@ -786,9 +814,9 @@ void kbase_device_pcm_dev_term(struct kbase_device *const kbdev);
*
* Return: sampled value of kfile::fops_count.
*/
static inline u32 kbase_file_fops_count(struct kbase_file *kfile)
static inline int kbase_file_fops_count(struct kbase_file *kfile)
{
u32 fops_count;
int fops_count;
spin_lock(&kfile->lock);
fops_count = kfile->fops_count;

4
drivers/gpu/arm/midgard/mali_kbase_as_fault_debugfs.h
View File

@ -22,6 +22,8 @@
#ifndef _KBASE_AS_FAULT_DEBUG_FS_H
#define _KBASE_AS_FAULT_DEBUG_FS_H
#include <mali_kbase.h>
/**
* kbase_as_fault_debugfs_init() - Add debugfs files for reporting page faults
*
@ -35,7 +37,7 @@ void kbase_as_fault_debugfs_init(struct kbase_device *kbdev);
* @kbdev: Pointer to kbase_device
* @as_no: The address space the fault occurred on
*/
static inline void kbase_as_fault_debugfs_new(struct kbase_device *kbdev, int as_no)
static inline void kbase_as_fault_debugfs_new(struct kbase_device *kbdev, unsigned int as_no)
{
#if IS_ENABLED(CONFIG_DEBUG_FS)
#ifdef CONFIG_MALI_DEBUG

3
drivers/gpu/arm/midgard/mali_kbase_cache_policy.c
View File

@ -23,7 +23,8 @@
* Cache Policy API.
*/
#include "mali_kbase_cache_policy.h"
#include <mali_kbase_cache_policy.h>
#include <mali_kbase.h>
/*
* The output flags should be a combination of the following values:

3
drivers/gpu/arm/midgard/mali_kbase_cache_policy.h
View File

@ -26,8 +26,7 @@
#ifndef _KBASE_CACHE_POLICY_H_
#define _KBASE_CACHE_POLICY_H_
#include "mali_kbase.h"
#include <uapi/gpu/arm/midgard/mali_base_kernel.h>
#include <linux/types.h>
/**
* kbase_cache_enabled - Choose the cache policy for a specific region

5
drivers/gpu/arm/midgard/mali_kbase_ccswe.c
View File

@ -32,13 +32,14 @@ static u64 kbasep_ccswe_cycle_at_no_lock(struct kbase_ccswe *self, u64 timestamp
lockdep_assert_held(&self->access);
diff_ns = timestamp_ns - self->timestamp_ns;
diff_ns = (s64)(timestamp_ns - self->timestamp_ns);
gpu_freq = diff_ns > 0 ? self->gpu_freq : self->prev_gpu_freq;
diff_s = div_s64(diff_ns, NSEC_PER_SEC);
diff_ns -= diff_s * NSEC_PER_SEC;
return self->cycles_elapsed + diff_s * gpu_freq + div_s64(diff_ns * gpu_freq, NSEC_PER_SEC);
return self->cycles_elapsed + (u64)diff_s * gpu_freq +
(u64)div_s64(diff_ns * gpu_freq, NSEC_PER_SEC);
}
void kbase_ccswe_init(struct kbase_ccswe *self)

1
drivers/gpu/arm/midgard/mali_kbase_ccswe.h
View File

@ -22,6 +22,7 @@
#ifndef _KBASE_CCSWE_H_
#define _KBASE_CCSWE_H_
#include <linux/types.h>
#include <linux/spinlock.h>
/**

4
drivers/gpu/arm/midgard/mali_kbase_config.h
View File

@ -26,9 +26,9 @@
#ifndef _KBASE_CONFIG_H_
#define _KBASE_CONFIG_H_
#include <linux/mm.h>
#include <mali_malisw.h>
#include <backend/gpu/mali_kbase_backend_config.h>
#include <linux/mm.h>
/* Forward declaration of struct kbase_device */
struct kbase_device;

31
drivers/gpu/arm/midgard/mali_kbase_config_defaults.h
View File

@ -219,6 +219,19 @@ enum {
#define KCPU_FENCE_SIGNAL_TIMEOUT_CYCLES (1000000000ull)
#endif
/* Timeout for polling the GPU in clock cycles.
*
* Based on 10s timeout based on original MAX_LOOPS value.
*/
#define IPA_INACTIVE_TIMEOUT_CYCLES (1000000000ull)
/* Timeout for polling the GPU for the MCU status in clock cycles.
*
* Based on 120s timeout based on original MAX_LOOPS value.
*/
#define CSF_FIRMWARE_STOP_TIMEOUT_CYCLES (12000000000ull)
/* Waiting timeout for task execution on an endpoint. Based on the
* DEFAULT_PROGRESS_TIMEOUT.
*
@ -250,6 +263,24 @@ enum {
#endif /* !MALI_USE_CSF */
/* Timeout for polling the GPU PRFCNT_ACTIVE bit in clock cycles.
*
* Based on 120s timeout at 100MHz, based on original MAX_LOOPS value.
*/
#define KBASE_PRFCNT_ACTIVE_TIMEOUT_CYCLES (12000000000ull)
/* Timeout for polling the GPU for a cache flush in clock cycles.
*
* Based on 120ms timeout at 100MHz, based on original MAX_LOOPS value.
*/
#define KBASE_CLEAN_CACHE_TIMEOUT_CYCLES (12000000ull)
/* Timeout for polling the GPU for an AS command to complete in clock cycles.
*
* Based on 120s timeout at 100MHz, based on original MAX_LOOPS value.
*/
#define KBASE_AS_INACTIVE_TIMEOUT_CYCLES (12000000000ull)
/* Default timeslice that a context is scheduled in for, in nanoseconds.
*
* When a context has used up this amount of time across its jobs, it is

362
drivers/gpu/arm/midgard/mali_kbase_core_linux.c
View File

@ -128,7 +128,7 @@
* @minor: Kernel minor version
*/
#define KBASE_API_VERSION(major, minor) \
((((major)&0xFFF) << 20) | (((minor)&0xFFF) << 8) | ((0 & 0xFF) << 0))
((((major)&0xFFFU) << 20U) | (((minor)&0xFFFU) << 8U) | ((0U & 0xFFU) << 0U))
/**
* struct mali_kbase_capability_def - kbase capabilities table
@ -525,26 +525,28 @@ static struct kbase_device *to_kbase_device(struct device *dev)
return dev_get_drvdata(dev);
}
int assign_irqs(struct kbase_device *kbdev)
/**
* get_irqs - Get interrupts information from the device tree.
*
* @kbdev: Kbase device.
* @pdev: Platform device of the kbase device
*
* Read interrupt number and flag for 'JOB', 'MMU' and 'GPU' interrupts
* from the device tree and fill them into the struct of the kbase device.
*
* Return: 0 on successful reading of all the entries JOB, MMU and GPU interrupts.
* -EINVAL on failure for all other cases.
*
*/
static int get_irqs(struct kbase_device *kbdev, struct platform_device *pdev)
{
int i;
static const char *const irq_names_caps[] = { "JOB", "MMU", "GPU" };
#if IS_ENABLED(CONFIG_OF)
static const char *const irq_names[] = { "job", "mmu", "gpu" };
#endif
struct platform_device *pdev;
size_t i;
if (!kbdev)
return -ENODEV;
pdev = to_platform_device(kbdev->dev);
for (i = 0; i < ARRAY_SIZE(irq_names_caps); i++) {
struct irq_data *irqdata;
int irq;
#if IS_ENABLED(CONFIG_OF)
/* We recommend using Upper case for the irq names in dts, but if
* there are devices in the world using Lower case then we should
* avoid breaking support for them. So try using names in Upper case
@ -552,24 +554,42 @@ int assign_irqs(struct kbase_device *kbdev)
* we assume there is no IRQ resource specified for the GPU.
*/
irq = platform_get_irq_byname(pdev, irq_names_caps[i]);
if (irq < 0)
irq = platform_get_irq_byname(pdev, irq_names[i]);
#else
irq = platform_get_irq(pdev, i);
#endif /* CONFIG_OF */
if (irq < 0) {
dev_err(kbdev->dev, "No IRQ resource '%s'\n", irq_names_caps[i]);
return irq;
static const char *const irq_names[] = { "job", "mmu", "gpu" };
irq = platform_get_irq_byname(pdev, irq_names[i]);
}
kbdev->irqs[i].irq = irq;
kbdev->irqs[i].flags = irqd_get_trigger_type(irq_get_irq_data(irq));
if (irq < 0)
return irq;
kbdev->irqs[i].irq = (u32)irq;
irqdata = irq_get_irq_data((unsigned int)irq);
if (likely(irqdata))
kbdev->irqs[i].flags = irqd_get_trigger_type(irqdata);
else
return -EINVAL;
kbdev->nr_irqs++;
}
return 0;
}
int kbase_get_irqs(struct kbase_device *kbdev)
{
int result;
struct platform_device *pdev = to_platform_device(kbdev->dev);
kbdev->nr_irqs = 0;
result = get_irqs(kbdev, pdev);
if (result)
dev_err(kbdev->dev, "Invalid or No interrupt resources");
return result;
}
/* Find a particular kbase device (as specified by minor number), or find the "first" device if -1 is specified */
struct kbase_device *kbase_find_device(int minor)
{
@ -618,19 +638,19 @@ static ssize_t write_ctx_infinite_cache(struct file *f, const char __user *ubuf,
else
kbase_ctx_flag_clear(kctx, KCTX_INFINITE_CACHE);
return size;
return (ssize_t)size;
}
static ssize_t read_ctx_infinite_cache(struct file *f, char __user *ubuf, size_t size, loff_t *off)
{
struct kbase_context *kctx = f->private_data;
char buf[32];
int count;
size_t count;
bool value;
value = kbase_ctx_flag(kctx, KCTX_INFINITE_CACHE);
count = scnprintf(buf, sizeof(buf), "%s\n", value ? "Y" : "N");
count = (size_t)scnprintf(buf, sizeof(buf), "%s\n", value ? "Y" : "N");
return simple_read_from_buffer(ubuf, size, off, buf, count);
}
@ -669,19 +689,19 @@ static ssize_t write_ctx_force_same_va(struct file *f, const char __user *ubuf,
kbase_ctx_flag_clear(kctx, KCTX_FORCE_SAME_VA);
}
return size;
return (ssize_t)size;
}
static ssize_t read_ctx_force_same_va(struct file *f, char __user *ubuf, size_t size, loff_t *off)
{
struct kbase_context *kctx = f->private_data;
char buf[32];
int count;
size_t count;
bool value;
value = kbase_ctx_flag(kctx, KCTX_FORCE_SAME_VA);
count = scnprintf(buf, sizeof(buf), "%s\n", value ? "Y" : "N");
count = (size_t)scnprintf(buf, sizeof(buf), "%s\n", value ? "Y" : "N");
return simple_read_from_buffer(ubuf, size, off, buf, count);
}
@ -759,7 +779,7 @@ static int kbase_open(struct inode *inode, struct file *filp)
struct kbase_file *kfile;
int ret = 0;
kbdev = kbase_find_device(iminor(inode));
kbdev = kbase_find_device((int)iminor(inode));
if (!kbdev)
return -ENODEV;
@ -901,7 +921,7 @@ static int kbase_api_get_gpuprops(struct kbase_file *kfile,
}
if (get_props->size == 0)
return kprops->prop_buffer_size;
return (int)kprops->prop_buffer_size;
if (get_props->size < kprops->prop_buffer_size)
return -EINVAL;
@ -909,7 +929,7 @@ static int kbase_api_get_gpuprops(struct kbase_file *kfile,
kprops->prop_buffer_size);
if (err)
return -EFAULT;
return kprops->prop_buffer_size;
return (int)kprops->prop_buffer_size;
}
#if !MALI_USE_CSF
@ -1111,8 +1131,8 @@ static int kbase_api_get_cpu_gpu_timeinfo(struct kbase_context *kctx,
timeinfo->out.cycle_counter = cycle_cnt;
if (flags & BASE_TIMEINFO_MONOTONIC_FLAG) {
timeinfo->out.sec = ts.tv_sec;
timeinfo->out.nsec = ts.tv_nsec;
timeinfo->out.sec = (u64)ts.tv_sec;
timeinfo->out.nsec = (u32)ts.tv_nsec;
}
kbase_pm_context_idle(kctx->kbdev);
@ -1139,14 +1159,14 @@ static int kbase_api_get_ddk_version(struct kbase_context *kctx,
struct kbase_ioctl_get_ddk_version *version)
{
int ret;
uint len = sizeof(KERNEL_SIDE_DDK_VERSION_STRING);
int len = sizeof(KERNEL_SIDE_DDK_VERSION_STRING);
CSTD_UNUSED(kctx);
if (version->version_buffer == 0)
return len;
if (version->size < len)
if (version->size < (u32)len)
return -EOVERFLOW;
ret = copy_to_user(u64_to_user_ptr(version->version_buffer), KERNEL_SIDE_DDK_VERSION_STRING,
@ -2192,7 +2212,7 @@ static ssize_t kbase_read(struct file *filp, char __user *buf, size_t count, lof
struct kbase_file *const kfile = filp->private_data;
struct kbase_context *kctx;
struct base_jd_event_v2 uevent;
int out_count = 0;
size_t out_count = 0;
ssize_t err = 0;
CSTD_UNUSED(f_pos);
@ -2430,13 +2450,15 @@ static ssize_t power_policy_show(struct device *dev, struct device_attribute *at
for (i = 0; i < policy_count && ret < (ssize_t)PAGE_SIZE; i++) {
if (policy_list[i] == current_policy)
ret += scnprintf(buf + ret, PAGE_SIZE - ret, "[%s] ", policy_list[i]->name);
ret += scnprintf(buf + ret, (size_t)(PAGE_SIZE - ret), "[%s] ",
policy_list[i]->name);
else
ret += scnprintf(buf + ret, PAGE_SIZE - ret, "%s ", policy_list[i]->name);
ret += scnprintf(buf + ret, (size_t)(PAGE_SIZE - ret), "%s ",
policy_list[i]->name);
}
if (ret < (ssize_t)PAGE_SIZE - 1) {
ret += scnprintf(buf + ret, PAGE_SIZE - ret, "\n");
ret += scnprintf(buf + ret, (size_t)(PAGE_SIZE - ret), "\n");
} else {
buf[PAGE_SIZE - 2] = '\n';
buf[PAGE_SIZE - 1] = '\0';
@ -2493,7 +2515,7 @@ static ssize_t power_policy_store(struct device *dev, struct device_attribute *a
kbase_pm_set_policy(kbdev, new_policy);
return count;
return (ssize_t)count;
}
/*
@ -2532,22 +2554,22 @@ static ssize_t core_mask_show(struct device *dev, struct device_attribute *attr,
spin_lock_irqsave(&kbdev->hwaccess_lock, flags);
#if MALI_USE_CSF
ret += scnprintf(buf + ret, PAGE_SIZE - ret, "Current debug core mask : 0x%llX\n",
ret += scnprintf(buf + ret, (size_t)(PAGE_SIZE - ret), "Current debug core mask : 0x%llX\n",
kbdev->pm.debug_core_mask);
ret += scnprintf(buf + ret, PAGE_SIZE - ret, "Current desired core mask : 0x%llX\n",
kbase_pm_ca_get_core_mask(kbdev));
ret += scnprintf(buf + ret, PAGE_SIZE - ret, "Current in use core mask : 0x%llX\n",
kbdev->pm.backend.shaders_avail);
ret += scnprintf(buf + ret, (size_t)(PAGE_SIZE - ret),
"Current desired core mask : 0x%llX\n", kbase_pm_ca_get_core_mask(kbdev));
ret += scnprintf(buf + ret, (size_t)(PAGE_SIZE - ret),
"Current in use core mask : 0x%llX\n", kbdev->pm.backend.shaders_avail);
#else
ret += scnprintf(buf + ret, PAGE_SIZE - ret, "Current core mask (JS0) : 0x%llX\n",
ret += scnprintf(buf + ret, (size_t)(PAGE_SIZE - ret), "Current core mask (JS0) : 0x%llX\n",
kbdev->pm.debug_core_mask[0]);
ret += scnprintf(buf + ret, PAGE_SIZE - ret, "Current core mask (JS1) : 0x%llX\n",
ret += scnprintf(buf + ret, (size_t)(PAGE_SIZE - ret), "Current core mask (JS1) : 0x%llX\n",
kbdev->pm.debug_core_mask[1]);
ret += scnprintf(buf + ret, PAGE_SIZE - ret, "Current core mask (JS2) : 0x%llX\n",
ret += scnprintf(buf + ret, (size_t)(PAGE_SIZE - ret), "Current core mask (JS2) : 0x%llX\n",
kbdev->pm.debug_core_mask[2]);
#endif /* MALI_USE_CSF */
ret += scnprintf(buf + ret, PAGE_SIZE - ret, "Available core mask : 0x%llX\n",
ret += scnprintf(buf + ret, (size_t)(PAGE_SIZE - ret), "Available core mask : 0x%llX\n",
kbdev->gpu_props.shader_present);
spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags);
@ -2580,7 +2602,7 @@ static ssize_t core_mask_store(struct device *dev, struct device_attribute *attr
#endif /* MALI_USE_CSF */
int items;
ssize_t err = count;
ssize_t err = (ssize_t)count;
unsigned long flags;
u64 shader_present;
@ -2733,7 +2755,7 @@ static ssize_t soft_job_timeout_store(struct device *dev, struct device_attribut
atomic_set(&kbdev->js_data.soft_job_timeout_ms, soft_job_timeout_ms);
return count;
return (ssize_t)count;
}
/**
@ -2768,14 +2790,14 @@ static u32 timeout_ms_to_ticks(struct kbase_device *kbdev, long timeout_ms, int
u32 old_ticks)
{
if (timeout_ms > 0) {
u64 ticks = timeout_ms * 1000000ULL;
u64 ticks = (u64)timeout_ms * 1000000ULL;
do_div(ticks, kbdev->js_data.scheduling_period_ns);
if (!ticks)
return 1;
return ticks;
} else if (timeout_ms < 0) {
return default_ticks;
return (u32)default_ticks;
} else {
return old_ticks;
}
@ -2859,7 +2881,7 @@ static ssize_t js_timeouts_store(struct device *dev, struct device_attribute *at
spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags);
return count;
return (ssize_t)count;
}
dev_err(kbdev->dev,
@ -3041,7 +3063,7 @@ static ssize_t js_scheduling_period_store(struct device *dev, struct device_attr
dev_dbg(kbdev->dev, "JS scheduling period: %dms\n", js_scheduling_period);
return count;
return (ssize_t)count;
}
/**
@ -3102,7 +3124,7 @@ static ssize_t js_softstop_always_store(struct device *dev, struct device_attrib
kbdev->js_data.softstop_always = (bool)softstop_always;
dev_dbg(kbdev->dev, "Support for softstop on a single context: %s\n",
(kbdev->js_data.softstop_always) ? "Enabled" : "Disabled");
return count;
return (ssize_t)count;
}
static ssize_t js_softstop_always_show(struct device *dev, struct device_attribute *attr,
@ -3191,7 +3213,8 @@ static ssize_t debug_command_show(struct device *dev, struct device_attribute *a
return -ENODEV;
for (i = 0; i < KBASEP_DEBUG_COMMAND_COUNT && ret < (ssize_t)PAGE_SIZE; i++)
ret += scnprintf(buf + ret, PAGE_SIZE - ret, "%s\n", debug_commands[i].str);
ret += scnprintf(buf + ret, (size_t)(PAGE_SIZE - ret), "%s\n",
debug_commands[i].str);
if (ret >= (ssize_t)PAGE_SIZE) {
buf[PAGE_SIZE - 2] = '\n';
@ -3233,7 +3256,7 @@ static ssize_t debug_command_store(struct device *dev, struct device_attribute *
for (i = 0; i < KBASEP_DEBUG_COMMAND_COUNT; i++) {
if (sysfs_streq(debug_commands[i].str, buf)) {
debug_commands[i].func(kbdev);
return count;
return (ssize_t)count;
}
}
@ -3287,6 +3310,7 @@ static ssize_t gpuinfo_show(struct device *dev, struct device_attribute *attr, c
{ .id = GPU_ID_PRODUCT_LODX, .name = "Mali-G610" },
{ .id = GPU_ID_PRODUCT_TGRX, .name = "Mali-G510" },
{ .id = GPU_ID_PRODUCT_TVAX, .name = "Mali-G310" },
{ .id = GPU_ID_PRODUCT_LTUX, .name = "Mali-G615" },
{ .id = GPU_ID_PRODUCT_LTIX, .name = "Mali-G620" },
{ .id = GPU_ID_PRODUCT_TKRX, .name = "Mali-TKRX" },
{ .id = GPU_ID_PRODUCT_LKRX, .name = "Mali-LKRX" },
@ -3352,6 +3376,7 @@ static ssize_t gpuinfo_show(struct device *dev, struct device_attribute *attr, c
dev_dbg(kbdev->dev, "GPU ID_Name: %s (ID: 0x%x), nr_cores(%u)\n", product_name,
product_id, nr_cores);
}
#endif /* MALI_USE_CSF */
return scnprintf(buf, PAGE_SIZE, "%s %d cores r%dp%d 0x%08X\n", product_name,
@ -3392,10 +3417,10 @@ static ssize_t dvfs_period_store(struct device *dev, struct device_attribute *at
return -EINVAL;
}
kbdev->pm.dvfs_period = dvfs_period;
kbdev->pm.dvfs_period = (u32)dvfs_period;
dev_dbg(kbdev->dev, "DVFS period: %dms\n", dvfs_period);
return count;
return (ssize_t)count;
}
/**
@ -3531,7 +3556,7 @@ static ssize_t pm_poweroff_store(struct device *dev, struct device_attribute *at
if (poweroff_gpu_ticks != 0)
dev_warn(kbdev->dev, "Separate GPU poweroff delay no longer supported.\n");
return count;
return (ssize_t)count;
}
/**
@ -3617,7 +3642,7 @@ static ssize_t reset_timeout_store(struct device *dev, struct device_attribute *
kbdev->reset_timeout_ms = reset_timeout;
dev_dbg(kbdev->dev, "Reset timeout: %ums\n", reset_timeout);
return count;
return (ssize_t)count;
}
/**
@ -3834,13 +3859,13 @@ static DEVICE_ATTR_RW(lp_mem_pool_max_size);
/**
* show_simplified_mem_pool_max_size - Show the maximum size for the memory
* pool 0 of small (4KiB) pages.
* pool 0 of small (4KiB/16KiB/64KiB) pages.
* @dev: The device this sysfs file is for.
* @attr: The attributes of the sysfs file.
* @buf: The output buffer to receive the max size.
*
* This function is called to get the maximum size for the memory pool 0 of
* small (4KiB) pages. It is assumed that the maximum size value is same for
* small pages. It is assumed that the maximum size value is same for
* all the pools.
*
* Return: The number of bytes output to @buf.
@ -3861,14 +3886,14 @@ static ssize_t show_simplified_mem_pool_max_size(struct device *dev, struct devi
/**
* set_simplified_mem_pool_max_size - Set the same maximum size for all the
* memory pools of small (4KiB) pages.
* memory pools of small (4KiB/16KiB/64KiB) pages.
* @dev: The device with sysfs file is for
* @attr: The attributes of the sysfs file
* @buf: The value written to the sysfs file
* @count: The number of bytes written to the sysfs file
*
* This function is called to set the same maximum size for all the memory
* pools of small (4KiB) pages.
* pools of small pages.
*
* Return: The number of bytes output to @buf.
*/
@ -3877,7 +3902,7 @@ static ssize_t set_simplified_mem_pool_max_size(struct device *dev, struct devic
{
struct kbase_device *const kbdev = to_kbase_device(dev);
unsigned long new_size;
int gid;
size_t gid;
int err;
CSTD_UNUSED(attr);
@ -3892,7 +3917,7 @@ static ssize_t set_simplified_mem_pool_max_size(struct device *dev, struct devic
for (gid = 0; gid < MEMORY_GROUP_MANAGER_NR_GROUPS; ++gid)
kbase_mem_pool_debugfs_set_max_size(kbdev->mem_pools.small, gid, (size_t)new_size);
return count;
return (ssize_t)count;
}
static DEVICE_ATTR(max_size, 0600, show_simplified_mem_pool_max_size,
@ -3944,7 +3969,7 @@ static ssize_t set_simplified_lp_mem_pool_max_size(struct device *dev,
{
struct kbase_device *const kbdev = to_kbase_device(dev);
unsigned long new_size;
int gid;
size_t gid;
int err;
CSTD_UNUSED(attr);
@ -3959,7 +3984,7 @@ static ssize_t set_simplified_lp_mem_pool_max_size(struct device *dev,
for (gid = 0; gid < MEMORY_GROUP_MANAGER_NR_GROUPS; ++gid)
kbase_mem_pool_debugfs_set_max_size(kbdev->mem_pools.large, gid, (size_t)new_size);
return count;
return (ssize_t)count;
}
static DEVICE_ATTR(lp_max_size, 0600, show_simplified_lp_mem_pool_max_size,
@ -3967,15 +3992,15 @@ static DEVICE_ATTR(lp_max_size, 0600, show_simplified_lp_mem_pool_max_size,
/**
* show_simplified_ctx_default_max_size - Show the default maximum size for the
* memory pool 0 of small (4KiB) pages.
* memory pool 0 of small (4KiB/16KiB/64KiB) pages.
* @dev: The device this sysfs file is for.
* @attr: The attributes of the sysfs file.
* @buf: The output buffer to receive the pool size.
*
* This function is called to get the default ctx maximum size for the memory
* pool 0 of small (4KiB) pages. It is assumed that maximum size value is same
* pool 0 of small pages. It is assumed that maximum size value is same
* for all the pools. The maximum size for the pool of large (2MiB) pages will
* be same as max size of the pool of small (4KiB) pages in terms of bytes.
* be same as max size of the pool of small pages in terms of bytes.
*
* Return: The number of bytes output to @buf.
*/
@ -4032,7 +4057,7 @@ static ssize_t set_simplified_ctx_default_max_size(struct device *dev,
kbase_mem_pool_group_config_set_max_size(&kbdev->mem_pool_defaults, (size_t)new_size);
return count;
return (ssize_t)count;
}
static DEVICE_ATTR(ctx_default_max_size, 0600, show_simplified_ctx_default_max_size,
@ -4102,7 +4127,7 @@ static ssize_t js_ctx_scheduling_mode_store(struct device *dev, struct device_at
}
if (new_js_ctx_scheduling_mode == kbdev->js_ctx_scheduling_mode)
return count;
return (ssize_t)count;
mutex_lock(&kbdev->kctx_list_lock);
spin_lock_irqsave(&kbdev->hwaccess_lock, flags);
@ -4119,7 +4144,7 @@ static ssize_t js_ctx_scheduling_mode_store(struct device *dev, struct device_at
dev_dbg(kbdev->dev, "JS ctx scheduling mode: %u\n", new_js_ctx_scheduling_mode);
return count;
return (ssize_t)count;
}
static DEVICE_ATTR_RW(js_ctx_scheduling_mode);
@ -4175,7 +4200,7 @@ static ssize_t update_serialize_jobs_setting(struct kbase_device *kbdev, const c
return -EINVAL;
}
return count;
return (ssize_t)count;
}
#if IS_ENABLED(CONFIG_DEBUG_FS)
@ -4290,15 +4315,15 @@ static ssize_t show_serialize_jobs_sysfs(struct device *dev, struct device_attri
for (i = 0; i < NR_SERIALIZE_JOBS_SETTINGS; i++) {
if (kbdev->serialize_jobs == serialize_jobs_settings[i].setting)
ret += scnprintf(buf + ret, PAGE_SIZE - ret, "[%s]",
ret += scnprintf(buf + ret, (size_t)(PAGE_SIZE - ret), "[%s]",
serialize_jobs_settings[i].name);
else
ret += scnprintf(buf + ret, PAGE_SIZE - ret, "%s ",
ret += scnprintf(buf + ret, (size_t)(PAGE_SIZE - ret), "%s ",
serialize_jobs_settings[i].name);
}
if (ret < (ssize_t)(PAGE_SIZE - 1)) {
ret += scnprintf(buf + ret, PAGE_SIZE - ret, "\n");
ret += scnprintf(buf + ret, (size_t)(PAGE_SIZE - ret), "\n");
} else {
buf[PAGE_SIZE - 2] = '\n';
buf[PAGE_SIZE - 1] = '\0';
@ -4690,7 +4715,7 @@ int power_control_init(struct kbase_device *kbdev)
* operating with a partial initialization of clocks.
*/
for (i = 0; i < BASE_MAX_NR_CLOCKS_REGULATORS; i++) {
kbdev->clocks[i] = of_clk_get(kbdev->dev->of_node, i);
kbdev->clocks[i] = of_clk_get(kbdev->dev->of_node, (int)i);
if (IS_ERR(kbdev->clocks[i])) {
err = PTR_ERR(kbdev->clocks[i]);
kbdev->clocks[i] = NULL;
@ -5247,6 +5272,93 @@ early_exit:
#if MALI_USE_CSF
bool kbasep_adjust_prioritized_process(struct kbase_device *kbdev, bool add, uint32_t tgid)
{
struct kbase_context *kctx;
bool found_contexts = false;
mutex_lock(&kbdev->kctx_list_lock);
list_for_each_entry(kctx, &kbdev->kctx_list, kctx_list_link) {
if (kctx->tgid == tgid) {
if (add)
dev_dbg(kbdev->dev,
"Adding context %pK of process %u to prioritized list\n",
(void *)kctx, tgid);
else
dev_dbg(kbdev->dev,
"Removing context %pK of process %u from prioritized list\n",
(void *)kctx, tgid);
atomic_set(&kctx->prioritized, add);
found_contexts = true;
}
}
mutex_unlock(&kbdev->kctx_list_lock);
if (found_contexts)
kbase_csf_scheduler_kick(kbdev);
return found_contexts;
}
static ssize_t add_prioritized_process_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
struct kbase_device *kbdev;
int ret;
unsigned int tgid;
CSTD_UNUSED(attr);
kbdev = to_kbase_device(dev);
if (!kbdev)
return -ENODEV;
ret = kstrtouint(buf, 0, &tgid);
if (ret || tgid == 0) {
dev_err(kbdev->dev, "Invalid PID specified\n");
return -EINVAL;
}
if (unlikely(!kbasep_adjust_prioritized_process(kbdev, true, tgid))) {
dev_err(kbdev->dev, "Non-existent PID specified\n");
return -EINVAL;
}
return count;
}
static DEVICE_ATTR_WO(add_prioritized_process);
static ssize_t remove_prioritized_process_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
struct kbase_device *kbdev;
int ret;
unsigned int tgid;
CSTD_UNUSED(attr);
kbdev = to_kbase_device(dev);
if (!kbdev)
return -ENODEV;
ret = kstrtouint(buf, 0, &tgid);
if (ret || tgid == 0) {
dev_err(kbdev->dev, "Invalid PID specified\n");
return -EINVAL;
}
if (unlikely(!kbasep_adjust_prioritized_process(kbdev, false, tgid))) {
dev_err(kbdev->dev, "Non-existent PID specified\n");
return -EINVAL;
}
return count;
}
static DEVICE_ATTR_WO(remove_prioritized_process);
/**
* csg_scheduling_period_store - Store callback for the csg_scheduling_period
* sysfs file.
@ -5286,7 +5398,7 @@ static ssize_t csg_scheduling_period_store(struct device *dev, struct device_att
dev_dbg(kbdev->dev, "CSG scheduling period: %ums\n", csg_scheduling_period);
kbase_csf_scheduler_unlock(kbdev);
return count;
return (ssize_t)count;
}
/**
@ -5350,16 +5462,16 @@ static ssize_t fw_timeout_store(struct device *dev, struct device_attribute *att
"Couldn't process fw_timeout write operation.\n"
"Use format 'fw_timeout_ms', and fw_timeout_ms > 0\n"
"Default fw_timeout: %u",
kbase_get_timeout_ms(kbdev, CSF_FIRMWARE_PING_TIMEOUT));
kbase_get_timeout_ms(kbdev, CSF_FIRMWARE_TIMEOUT));
return -EINVAL;
}
kbase_csf_scheduler_lock(kbdev);
kbdev->csf.fw_timeout_ms = fw_timeout;
kbase_device_set_timeout_ms(kbdev, CSF_FIRMWARE_TIMEOUT, fw_timeout);
kbase_csf_scheduler_unlock(kbdev);
dev_dbg(kbdev->dev, "Firmware timeout: %ums\n", fw_timeout);
return count;
return (ssize_t)count;
}
/**
@ -5383,7 +5495,7 @@ static ssize_t fw_timeout_show(struct device *dev, struct device_attribute *attr
if (!kbdev)
return -ENODEV;
ret = scnprintf(buf, PAGE_SIZE, "%u\n", kbdev->csf.fw_timeout_ms);
ret = scnprintf(buf, PAGE_SIZE, "%u\n", kbase_get_timeout_ms(kbdev, CSF_FIRMWARE_TIMEOUT));
return ret;
}
@ -5409,7 +5521,7 @@ static ssize_t idle_hysteresis_time_store(struct device *dev, struct device_attr
const char *buf, size_t count)
{
struct kbase_device *kbdev;
u32 dur = 0;
u32 dur_us = 0;
CSTD_UNUSED(attr);
@ -5417,7 +5529,7 @@ static ssize_t idle_hysteresis_time_store(struct device *dev, struct device_attr
if (!kbdev)
return -ENODEV;
if (kstrtou32(buf, 0, &dur)) {
if (kstrtou32(buf, 0, &dur_us)) {
dev_err(kbdev->dev, "Couldn't process idle_hysteresis_time write operation.\n"
"Use format <idle_hysteresis_time>\n");
return -EINVAL;
@ -5426,9 +5538,9 @@ static ssize_t idle_hysteresis_time_store(struct device *dev, struct device_attr
/* In sysFs, The unit of the input value of idle_hysteresis_time is us.
* But the unit of the input parameter of this function is ns, so multiply by 1000
*/
kbase_csf_firmware_set_gpu_idle_hysteresis_time(kbdev, dur * NSEC_PER_USEC);
kbase_csf_firmware_set_gpu_idle_hysteresis_time(kbdev, (u64)dur_us * NSEC_PER_USEC);
return count;
return (ssize_t)count;
}
/**
@ -5438,7 +5550,7 @@ static ssize_t idle_hysteresis_time_store(struct device *dev, struct device_attr
* @attr: The attributes of the sysfs file.
* @buf: The output buffer to receive the GPU information.
*
* This function is called to get the current idle hysteresis duration in ms.
* This function is called to get the current idle hysteresis duration in us.
*
* Return: The number of bytes output to @buf.
*/
@ -5447,7 +5559,7 @@ static ssize_t idle_hysteresis_time_show(struct device *dev, struct device_attri
{
struct kbase_device *kbdev;
ssize_t ret;
u32 dur;
u64 dur_us;
CSTD_UNUSED(attr);
@ -5455,9 +5567,9 @@ static ssize_t idle_hysteresis_time_show(struct device *dev, struct device_attri
if (!kbdev)
return -ENODEV;
/* The unit of return value of idle_hysteresis_time_show is us, So divide by 1000.*/
dur = kbase_csf_firmware_get_gpu_idle_hysteresis_time(kbdev) / NSEC_PER_USEC;
ret = scnprintf(buf, PAGE_SIZE, "%u\n", dur);
/* The unit of return value of idle_hysteresis_time_show is us, So divide by 1000 */
dur_us = div_u64(kbase_csf_firmware_get_gpu_idle_hysteresis_time(kbdev), NSEC_PER_USEC);
ret = scnprintf(buf, PAGE_SIZE, "%u\n", (u32)dur_us);
return ret;
}
@ -5484,19 +5596,19 @@ static ssize_t idle_hysteresis_time_ns_store(struct device *dev, struct device_a
const char *buf, size_t count)
{
struct kbase_device *kbdev;
u32 dur = 0;
u64 dur_ns = 0;
kbdev = to_kbase_device(dev);
if (!kbdev)
return -ENODEV;
if (kstrtou32(buf, 0, &dur)) {
if (kstrtou64(buf, 0, &dur_ns)) {
dev_err(kbdev->dev, "Couldn't process idle_hysteresis_time_ns write operation.\n"
"Use format <idle_hysteresis_time_ns>\n");
return -EINVAL;
}
kbase_csf_firmware_set_gpu_idle_hysteresis_time(kbdev, dur);
kbase_csf_firmware_set_gpu_idle_hysteresis_time(kbdev, dur_ns);
return count;
}
@ -5518,14 +5630,14 @@ static ssize_t idle_hysteresis_time_ns_show(struct device *dev, struct device_at
{
struct kbase_device *kbdev;
ssize_t ret;
u32 dur;
u64 dur_ns;
kbdev = to_kbase_device(dev);
if (!kbdev)
return -ENODEV;
dur = kbase_csf_firmware_get_gpu_idle_hysteresis_time(kbdev);
ret = scnprintf(buf, PAGE_SIZE, "%u\n", dur);
dur_ns = kbase_csf_firmware_get_gpu_idle_hysteresis_time(kbdev);
ret = scnprintf(buf, PAGE_SIZE, "%llu\n", dur_ns);
return ret;
}
@ -5549,16 +5661,16 @@ static ssize_t mcu_shader_pwroff_timeout_show(struct device *dev, struct device_
char *const buf)
{
struct kbase_device *kbdev = dev_get_drvdata(dev);
u32 pwroff;
u64 pwroff_us;
CSTD_UNUSED(attr);
if (!kbdev)
return -ENODEV;
/* The unit of return value of the function is us, So divide by 1000.*/
pwroff = kbase_csf_firmware_get_mcu_core_pwroff_time(kbdev) / NSEC_PER_USEC;
return scnprintf(buf, PAGE_SIZE, "%u\n", pwroff);
/* The unit of return value of the function is us, So divide by 1000 */
pwroff_us = div_u64(kbase_csf_firmware_get_mcu_core_pwroff_time(kbdev), NSEC_PER_USEC);
return scnprintf(buf, PAGE_SIZE, "%u\n", (u32)pwroff_us);
}
/**
@ -5579,7 +5691,7 @@ static ssize_t mcu_shader_pwroff_timeout_store(struct device *dev, struct device
const char *buf, size_t count)
{
struct kbase_device *kbdev = dev_get_drvdata(dev);
u32 dur;
u32 dur_us;
const struct kbase_pm_policy *current_policy;
bool always_on;
@ -5589,20 +5701,20 @@ static ssize_t mcu_shader_pwroff_timeout_store(struct device *dev, struct device
if (!kbdev)
return -ENODEV;
if (kstrtouint(buf, 0, &dur))
if (kstrtou32(buf, 0, &dur_us))
return -EINVAL;
current_policy = kbase_pm_get_policy(kbdev);
always_on = current_policy == &kbase_pm_always_on_policy_ops;
if (dur == 0 && !always_on)
if (dur_us == 0 && !always_on)
return -EINVAL;
/* In sysFs, The unit of the input value of mcu_shader_pwroff_timeout is us.
* But the unit of the input parameter of this function is ns, so multiply by 1000
*/
kbase_csf_firmware_set_mcu_core_pwroff_time(kbdev, dur * NSEC_PER_USEC);
kbase_csf_firmware_set_mcu_core_pwroff_time(kbdev, (u64)dur_us * NSEC_PER_USEC);
return count;
return (ssize_t)count;
}
static DEVICE_ATTR_RW(mcu_shader_pwroff_timeout);
@ -5624,13 +5736,13 @@ static ssize_t mcu_shader_pwroff_timeout_ns_show(struct device *dev, struct devi
char *const buf)
{
struct kbase_device *kbdev = dev_get_drvdata(dev);
u32 pwroff;
u64 pwroff_ns;
if (!kbdev)
return -ENODEV;
pwroff = kbase_csf_firmware_get_mcu_core_pwroff_time(kbdev);
return scnprintf(buf, PAGE_SIZE, "%u\n", pwroff);
pwroff_ns = kbase_csf_firmware_get_mcu_core_pwroff_time(kbdev);
return scnprintf(buf, PAGE_SIZE, "%llu\n", pwroff_ns);
}
/**
@ -5651,7 +5763,7 @@ static ssize_t mcu_shader_pwroff_timeout_ns_store(struct device *dev, struct dev
const char *buf, size_t count)
{
struct kbase_device *kbdev = dev_get_drvdata(dev);
u32 dur;
u64 dur_ns;
const struct kbase_pm_policy *current_policy;
bool always_on;
@ -5659,15 +5771,15 @@ static ssize_t mcu_shader_pwroff_timeout_ns_store(struct device *dev, struct dev
if (!kbdev)
return -ENODEV;
if (kstrtouint(buf, 0, &dur))
if (kstrtou64(buf, 0, &dur_ns))
return -EINVAL;
current_policy = kbase_pm_get_policy(kbdev);
always_on = current_policy == &kbase_pm_always_on_policy_ops;
if (dur == 0 && !always_on)
if (dur_ns == 0 && !always_on)
return -EINVAL;
kbase_csf_firmware_set_mcu_core_pwroff_time(kbdev, dur);
kbase_csf_firmware_set_mcu_core_pwroff_time(kbdev, dur_ns);
return count;
}
@ -5702,6 +5814,8 @@ static struct attribute *kbase_attrs[] = {
&dev_attr_js_scheduling_period.attr,
#else
&dev_attr_csg_scheduling_period.attr,
&dev_attr_add_prioritized_process.attr,
&dev_attr_remove_prioritized_process.attr,
&dev_attr_fw_timeout.attr,
&dev_attr_idle_hysteresis_time.attr,
&dev_attr_idle_hysteresis_time_ns.attr,
@ -5859,6 +5973,10 @@ static int kbase_platform_device_probe(struct platform_device *pdev)
#endif
dev_info(kbdev->dev, "Probed as %s\n", dev_name(kbdev->mdev.this_device));
if (PAGE_SHIFT != 12)
dev_warn(kbdev->dev, "Experimental feature: %s with Page Size of %luKiB",
dev_name(kbdev->mdev.this_device), PAGE_SIZE / 1024);
kbase_increment_device_id();
#if (KERNEL_VERSION(5, 3, 0) <= LINUX_VERSION_CODE)
mutex_unlock(&kbase_probe_mutex);
@ -6150,8 +6268,8 @@ void kbase_trace_mali_pm_status(u32 dev_id, u32 event, u64 value)
void kbase_trace_mali_job_slots_event(u32 dev_id, u32 event, const struct kbase_context *kctx,
u8 atom_id)
{
trace_mali_job_slots_event(dev_id, event, (kctx != NULL ? kctx->tgid : 0),
(kctx != NULL ? kctx->pid : 0), atom_id);
trace_mali_job_slots_event(dev_id, event, (kctx != NULL ? (u32)kctx->tgid : 0U),
(kctx != NULL ? (u32)kctx->pid : 0U), atom_id);
}
void kbase_trace_mali_page_fault_insert_pages(u32 dev_id, int event, u32 value)

11
drivers/gpu/arm/midgard/mali_kbase_ctx_sched.c
View File

@ -45,7 +45,7 @@ static int kbase_ktrace_get_ctx_refcnt(struct kbase_context *kctx)
int kbase_ctx_sched_init(struct kbase_device *kbdev)
{
int as_present = (1U << kbdev->nr_hw_address_spaces) - 1;
int as_present = (1 << kbdev->nr_hw_address_spaces) - 1;
/* These two must be recalculated if nr_hw_address_spaces changes
* (e.g. for HW workarounds)
@ -133,7 +133,8 @@ int kbase_ctx_sched_retain_ctx(struct kbase_context *kctx)
}
kctx->as_nr = free_as;
kbdev->as_to_kctx[free_as] = kctx;
KBASE_TLSTREAM_TL_KBASE_CTX_ASSIGN_AS(kbdev, kctx->id, free_as);
KBASE_TLSTREAM_TL_KBASE_CTX_ASSIGN_AS(kbdev, kctx->id,
(u32)free_as);
kbase_mmu_update(kbdev, &kctx->mmu, kctx->as_nr);
}
} else {
@ -198,7 +199,7 @@ void kbase_ctx_sched_release_ctx(struct kbase_context *kctx)
}
}
KBASE_KTRACE_ADD(kbdev, SCHED_RELEASE_CTX, kctx, new_ref_count);
KBASE_KTRACE_ADD(kbdev, SCHED_RELEASE_CTX, kctx, (u64)new_ref_count);
}
void kbase_ctx_sched_remove_ctx(struct kbase_context *kctx)
@ -340,7 +341,7 @@ bool kbase_ctx_sched_inc_refcount_nolock(struct kbase_context *kctx)
kbase_ctx_sched_retain_ctx_refcount(kctx);
KBASE_KTRACE_ADD(kctx->kbdev, SCHED_RETAIN_CTX_NOLOCK, kctx,
kbase_ktrace_get_ctx_refcnt(kctx));
(u64)kbase_ktrace_get_ctx_refcnt(kctx));
result = true;
}
@ -408,7 +409,7 @@ bool kbase_ctx_sched_inc_refcount_if_as_valid(struct kbase_context *kctx)
kbdev->as_free &= ~(1u << kctx->as_nr);
KBASE_KTRACE_ADD(kbdev, SCHED_RETAIN_CTX_NOLOCK, kctx,
kbase_ktrace_get_ctx_refcnt(kctx));
(u64)kbase_ktrace_get_ctx_refcnt(kctx));
added_ref = true;
}

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