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https://github.com/nxp-imx/linux-imx.git
synced 2025-07-08 10:25:20 +02:00
ANDROID: KVM: arm64: Consolidate allowed and restricted guest cpu feature checks
The definitions for allowed and restricted cpu features for
protected guests, which are based on feature registers were
defined and checked for separately. This resulted in an
inconsistency when checking if pointer authentication is allowed,
which resulted in trapping it for protected guests despite it
being allowed.
To avoid this happening in the future, consolidate the
definitions into one. Use that new definition to construct the
guest view of the feature registers for consistency.
Bug: 278749606
Change-Id: Ia290b98a44ca533578add5ab4ca06888eb62e507
Fixes: 6c30bfb18d ("KVM: arm64: Add handlers for protected VM System Registers")
Reported-by: Mostafa Saleh <smostafa@google.com>
Signed-off-by: Fuad Tabba <tabba@google.com>
This commit is contained in:
Fuad Tabba
parent
c7b8a41d0f
commit
d4474bddf8
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@ -47,11 +47,8 @@ void pkvm_host_reclaim_page(struct kvm *host_kvm, phys_addr_t ipa);
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* machines, depending on the mode KVM is running in and on the type of guest
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* that is running.
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*
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* The ALLOW masks represent a bitmask of feature fields that are allowed
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* without any restrictions as long as they are supported by the system.
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*
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* The RESTRICT_UNSIGNED masks, if present, represent unsigned fields for
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* features that are restricted to support at most the specified feature.
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* Each field in the masks represents the highest supported *unsigned* value for
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* the feature, if supported by the system.
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*
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* If a feature field is not present in either, than it is not supported.
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*
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@ -67,15 +64,7 @@ void pkvm_host_reclaim_page(struct kvm *host_kvm, phys_addr_t ipa);
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* - Floating-point and Advanced SIMD
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* - GICv3(+) system register interface
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* - Data Independent Timing
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*/
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#define PVM_ID_AA64PFR0_ALLOW (\
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ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_FP) | \
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ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AdvSIMD) | \
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ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC) | \
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ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_DIT) \
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)
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/*
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*
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* Restrict to the following *unsigned* features for protected VMs:
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* - AArch64 guests only (no support for AArch32 guests):
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* AArch32 adds complexity in trap handling, emulation, condition codes,
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@ -84,7 +73,11 @@ void pkvm_host_reclaim_page(struct kvm *host_kvm, phys_addr_t ipa);
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* - RAS (v1)
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* Supported by KVM
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*/
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#define PVM_ID_AA64PFR0_RESTRICT_UNSIGNED (\
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#define PVM_ID_AA64PFR0_ALLOW (\
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ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_FP) | \
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ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AdvSIMD) | \
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ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC) | \
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ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_DIT) | \
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FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL0), ID_AA64PFR0_EL1_ELx_64BIT_ONLY) | \
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FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL1), ID_AA64PFR0_EL1_ELx_64BIT_ONLY) | \
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FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL2), ID_AA64PFR0_EL1_ELx_64BIT_ONLY) | \
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@ -111,20 +104,16 @@ void pkvm_host_reclaim_page(struct kvm *host_kvm, phys_addr_t ipa);
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* - Distinction between Secure and Non-secure Memory
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* - Mixed-endian at EL0 only
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* - Non-context synchronizing exception entry and exit
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*
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* Restrict to the following *unsigned* features for protected VMs:
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* - 40-bit IPA
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* - 16-bit ASID
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*/
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#define PVM_ID_AA64MMFR0_ALLOW (\
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ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_BIGEND) | \
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ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_SNSMEM) | \
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ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_BIGENDEL0) | \
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ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_EXS) \
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)
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/*
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* Restrict to the following *unsigned* features for protected VMs:
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* - 40-bit IPA
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* - 16-bit ASID
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*/
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#define PVM_ID_AA64MMFR0_RESTRICT_UNSIGNED (\
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ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_EXS) | \
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FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_PARANGE), ID_AA64MMFR0_EL1_PARANGE_40) | \
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FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_ASIDBITS), ID_AA64MMFR0_EL1_ASIDBITS_16) \
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)
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@ -227,15 +216,6 @@ void pkvm_host_reclaim_page(struct kvm *host_kvm, phys_addr_t ipa);
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)
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/* Restrict pointer authentication to the basic version. */
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#define PVM_ID_AA64ISAR1_RESTRICT_UNSIGNED (\
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FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA), ID_AA64ISAR1_EL1_APA_PAuth) | \
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FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API), ID_AA64ISAR1_EL1_API_PAuth) \
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)
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#define PVM_ID_AA64ISAR2_RESTRICT_UNSIGNED (\
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FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3), ID_AA64ISAR2_EL1_APA3_PAuth) \
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)
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#define PVM_ID_AA64ISAR1_ALLOW (\
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ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_DPB) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_JSCVT) | \
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@ -248,13 +228,16 @@ void pkvm_host_reclaim_page(struct kvm *host_kvm, phys_addr_t ipa);
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ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_SPECRES) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_BF16) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_DGH) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_I8MM) \
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ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_I8MM) | \
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FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA), ID_AA64ISAR1_EL1_APA_PAuth) | \
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FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API), ID_AA64ISAR1_EL1_API_PAuth) \
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)
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#define PVM_ID_AA64ISAR2_ALLOW (\
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ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_ATS1A) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_MOPS) \
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ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_MOPS) | \
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FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3), ID_AA64ISAR2_EL1_APA3_PAuth) \
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)
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@ -331,8 +314,8 @@ void pkvm_host_reclaim_page(struct kvm *host_kvm, phys_addr_t ipa);
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#define HFGxTR_nLS64 HFGxTR_EL2_nACCDATA_EL1
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#define PVM_HFGXTR_EL2_SET \
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(FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_RAS), PVM_ID_AA64PFR0_RESTRICT_UNSIGNED) >= ID_AA64PFR0_EL1_RAS_IMP ? 0ULL : HFGxTR_RAS_IMP) | \
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(FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_RAS), PVM_ID_AA64PFR0_RESTRICT_UNSIGNED) >= ID_AA64PFR0_EL1_RAS_V1P1 ? 0ULL : HFGxTR_RAS_V1P1) | \
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(FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_RAS), PVM_ID_AA64PFR0_ALLOW) >= ID_AA64PFR0_EL1_RAS_IMP ? 0ULL : HFGxTR_RAS_IMP) | \
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(FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_RAS), PVM_ID_AA64PFR0_ALLOW) >= ID_AA64PFR0_EL1_RAS_V1P1 ? 0ULL : HFGxTR_RAS_V1P1) | \
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(FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC), PVM_ID_AA64PFR0_ALLOW) ? 0ULL : HFGxTR_GIC) | \
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(FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2), PVM_ID_AA64PFR0_ALLOW) ? 0ULL : HFGxTR_CSV2) | \
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(FIELD_GET(ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_LO), PVM_ID_AA64MMFR1_ALLOW) ? 0ULL : HFGxTR_LOR) | \
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@ -454,8 +437,8 @@ void pkvm_host_reclaim_page(struct kvm *host_kvm, phys_addr_t ipa);
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0
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#define PVM_HCRX_EL2_CLR \
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(FIELD_GET(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA), PVM_ID_AA64ISAR1_RESTRICT_UNSIGNED) < ID_AA64ISAR1_EL1_APA_PAuth_LR ? 0ULL : HCRX_nPAuth_LR) | \
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(FIELD_GET(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API), PVM_ID_AA64ISAR1_RESTRICT_UNSIGNED) < ID_AA64ISAR1_EL1_APA_PAuth_LR ? 0ULL : HCRX_nPAuth_LR) | \
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(FIELD_GET(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA), PVM_ID_AA64ISAR1_ALLOW) < ID_AA64ISAR1_EL1_APA_PAuth_LR ? 0ULL : HCRX_nPAuth_LR) | \
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(FIELD_GET(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API), PVM_ID_AA64ISAR1_ALLOW) < ID_AA64ISAR1_EL1_APA_PAuth_LR ? 0ULL : HCRX_nPAuth_LR) | \
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(FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_GCS), PVM_ID_AA64PFR1_ALLOW) ? 0ULL : HCRX_nGCS) | \
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(FIELD_GET(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_SYSREG_128), PVM_ID_AA64ISAR2_ALLOW) ? 0ULL : HCRX_nSYSREG128) | \
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(FIELD_GET(ARM64_FEATURE_MASK(ID_AA64MMFR3_EL1_ADERR), PVM_ID_AA64MMFR3_ALLOW) ? 0ULL : HCRX_nADERR) | \
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@ -384,7 +384,7 @@ static int pkvm_check_extension(struct kvm *kvm, long ext, int kvm_cap)
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break;
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case KVM_CAP_ARM_SVE:
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r = kvm_cap && FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_SVE),
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PVM_ID_AA64PFR0_RESTRICT_UNSIGNED);
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PVM_ID_AA64PFR0_ALLOW);
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break;
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case KVM_CAP_ARM_PTRAUTH_ADDRESS:
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r = kvm_cap &&
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@ -85,9 +85,9 @@ static void pvm_init_traps_aa64pfr0(struct kvm_vcpu *vcpu)
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/* Protected KVM does not support AArch32 guests. */
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BUILD_BUG_ON(FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL0),
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PVM_ID_AA64PFR0_RESTRICT_UNSIGNED) != ID_AA64PFR0_EL1_ELx_64BIT_ONLY);
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PVM_ID_AA64PFR0_ALLOW) != ID_AA64PFR0_EL1_ELx_64BIT_ONLY);
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BUILD_BUG_ON(FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL1),
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PVM_ID_AA64PFR0_RESTRICT_UNSIGNED) != ID_AA64PFR0_EL1_ELx_64BIT_ONLY);
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PVM_ID_AA64PFR0_ALLOW) != ID_AA64PFR0_EL1_ELx_64BIT_ONLY);
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/*
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* Linux guests assume support for floating-point and Advanced SIMD. Do
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@ -510,11 +510,11 @@ static void pkvm_vcpu_init_features_from_host(struct pkvm_hyp_vcpu *hyp_vcpu)
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if (FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), PVM_ID_AA64DFR0_ALLOW))
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set_bit(KVM_ARM_VCPU_PMU_V3, allowed_features);
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if (FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_SVE), PVM_ID_AA64PFR0_RESTRICT_UNSIGNED))
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if (FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_SVE), PVM_ID_AA64PFR0_ALLOW))
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set_bit(KVM_ARM_VCPU_SVE, allowed_features);
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if (FIELD_GET(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API), PVM_ID_AA64ISAR1_RESTRICT_UNSIGNED) &&
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FIELD_GET(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA), PVM_ID_AA64ISAR1_RESTRICT_UNSIGNED))
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if (FIELD_GET(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API), PVM_ID_AA64ISAR1_ALLOW) &&
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FIELD_GET(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA), PVM_ID_AA64ISAR1_ALLOW))
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set_bit(KVM_ARM_VCPU_PTRAUTH_ADDRESS, allowed_features);
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if (FIELD_GET(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI), PVM_ID_AA64ISAR1_ALLOW) &&
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@ -53,7 +53,6 @@ static void inject_undef64(struct kvm_vcpu *vcpu)
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/*
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* Returns the restricted features values of the feature register based on the
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* limitations in restrict_fields.
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* A feature id field value of 0b0000 does not impose any restrictions.
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* Note: Use only for unsigned feature field values.
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*/
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static u64 get_restricted_features_unsigned(u64 sys_reg_val,
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@ -86,33 +85,32 @@ static u64 get_restricted_features_unsigned(u64 sys_reg_val,
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static u64 get_pvm_id_aa64pfr0(const struct kvm_vcpu *vcpu)
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{
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u64 set_mask = 0;
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u64 allow_mask = PVM_ID_AA64PFR0_ALLOW;
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set_mask |= get_restricted_features_unsigned(id_aa64pfr0_el1_sys_val,
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PVM_ID_AA64PFR0_RESTRICT_UNSIGNED);
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u64 value = get_restricted_features_unsigned(id_aa64pfr0_el1_sys_val,
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PVM_ID_AA64PFR0_ALLOW);
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if (!vcpu_has_sve(vcpu))
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set_mask &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_SVE);
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value &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_SVE);
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return (id_aa64pfr0_el1_sys_val & allow_mask) | set_mask;
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return value;
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}
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static u64 get_pvm_id_aa64pfr1(const struct kvm_vcpu *vcpu)
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{
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const struct kvm *kvm = (const struct kvm *)kern_hyp_va(vcpu->kvm);
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u64 allow_mask = PVM_ID_AA64PFR1_ALLOW;
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u64 value = get_restricted_features_unsigned(id_aa64pfr1_el1_sys_val,
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PVM_ID_AA64PFR1_ALLOW);
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if (!kvm_has_mte(kvm))
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allow_mask &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE);
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value &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE);
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return id_aa64pfr1_el1_sys_val & allow_mask;
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return value;
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}
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static u64 get_pvm_id_aa64zfr0(const struct kvm_vcpu *vcpu)
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{
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if (vcpu_has_sve(vcpu))
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return id_aa64zfr0_el1_sys_val & PVM_ID_AA64ZFR0_ALLOW;
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return get_restricted_features_unsigned(id_aa64zfr0_el1_sys_val,
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PVM_ID_AA64ZFR0_ALLOW);
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return 0;
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}
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@ -164,46 +162,46 @@ static u64 get_pvm_id_aa64isar0(const struct kvm_vcpu *vcpu)
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static u64 get_pvm_id_aa64isar1(const struct kvm_vcpu *vcpu)
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{
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u64 allow_mask = PVM_ID_AA64ISAR1_ALLOW;
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u64 value = get_restricted_features_unsigned(id_aa64isar1_el1_sys_val,
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PVM_ID_AA64ISAR1_ALLOW);
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if (!vcpu_has_ptrauth(vcpu))
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allow_mask &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) |
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ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) |
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ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) |
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ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI));
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value &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) |
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ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) |
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ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) |
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ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI));
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return id_aa64isar1_el1_sys_val & allow_mask;
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return value;
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}
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static u64 get_pvm_id_aa64isar2(const struct kvm_vcpu *vcpu)
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{
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u64 allow_mask = PVM_ID_AA64ISAR2_ALLOW;
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u64 value = get_restricted_features_unsigned(id_aa64isar2_el1_sys_val,
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PVM_ID_AA64ISAR2_ALLOW);
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if (!vcpu_has_ptrauth(vcpu))
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allow_mask &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) |
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ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3));
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value &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) |
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ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3));
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return id_aa64isar2_el1_sys_val & allow_mask;
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return id_aa64isar2_el1_sys_val & value;
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}
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static u64 get_pvm_id_aa64mmfr0(const struct kvm_vcpu *vcpu)
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{
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u64 set_mask;
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set_mask = get_restricted_features_unsigned(id_aa64mmfr0_el1_sys_val,
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PVM_ID_AA64MMFR0_RESTRICT_UNSIGNED);
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return (id_aa64mmfr0_el1_sys_val & PVM_ID_AA64MMFR0_ALLOW) | set_mask;
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return get_restricted_features_unsigned(id_aa64mmfr0_el1_sys_val,
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PVM_ID_AA64MMFR0_ALLOW);
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}
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static u64 get_pvm_id_aa64mmfr1(const struct kvm_vcpu *vcpu)
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{
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return id_aa64mmfr1_el1_sys_val & PVM_ID_AA64MMFR1_ALLOW;
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return get_restricted_features_unsigned(id_aa64mmfr1_el1_sys_val,
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PVM_ID_AA64MMFR1_ALLOW);
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}
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static u64 get_pvm_id_aa64mmfr2(const struct kvm_vcpu *vcpu)
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{
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return id_aa64mmfr2_el1_sys_val & PVM_ID_AA64MMFR2_ALLOW;
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||||
return get_restricted_features_unsigned(id_aa64mmfr2_el1_sys_val,
|
||||
PVM_ID_AA64MMFR2_ALLOW);
|
||||
}
|
||||
|
||||
/* Read a sanitized cpufeature ID register by its encoding */
|
||||
|
|
@ -278,7 +276,7 @@ static bool pvm_access_id_aarch32(struct kvm_vcpu *vcpu,
|
|||
* of AArch32 feature id registers.
|
||||
*/
|
||||
BUILD_BUG_ON(FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL1),
|
||||
PVM_ID_AA64PFR0_RESTRICT_UNSIGNED) > ID_AA64PFR0_EL1_ELx_64BIT_ONLY);
|
||||
PVM_ID_AA64PFR0_ALLOW) > ID_AA64PFR0_EL1_ELx_64BIT_ONLY);
|
||||
|
||||
return pvm_access_raz_wi(vcpu, p, r);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user