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LF-15259 drm/imx: dpu95: Fix maximum FrameGen display clock frequency

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Design team says that the frequency limitation mentioned at controller
specification is just a general guideline for the IP. The maximum frequency
depends on the process technology and SoC architecture requirement of the
SoC.  Specifically for i.MX95, the frequency of dspx_clk is signed off at
350MHz at UD/NM/OD mode.  So 350MHz is the limit of the chip, not 300MHz.

So, change maximum FrameGen display clock frequency from 300MHz to 350MHz.

Reported-by: Qiang Li <qiang.li@nxp.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
This commit is contained in:
Liu Ying 2025-05-07 16:51:56 +08:00 committed by Jason Liu
parent 3132641783
commit d6b4952355
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/imx/dpu95/dpu95.h
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@ -67,7 +67,7 @@
#define CTRL_MODE_MASK BIT(0)
#define DPU95_FRAMEGEN_MAX_FRAME_INDEX 0x3ffff
#define DPU95_FRAMEGEN_MAX_CLOCK 300000 /* in KHz */
#define DPU95_FRAMEGEN_MAX_CLOCK 350000 /* in KHz */
#define DPU95_FETCHUNIT_CAP_USE_FETCHECO BIT(0)
#define DPU95_FETCHUNIT_CAP_USE_HSCALER BIT(1)