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arm64: dts: qcom: sa8540p-ride: enable rtc

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SA8540P-ride is one of the Qualcomm platforms that does not have access
to UEFI runtime services and on which the RTC registers are read-only,
as described in:
https://lore.kernel.org/all/20230202155448.6715-1-johan+linaro@kernel.org/

Reserve four bytes in one of the PMIC registers to hold the RTC offset
the same way as it was done for sc8280xp-crd which has similar
limitations:
    commit e67b45582c ("arm64: dts: qcom: sc8280xp-crd: enable rtc")

On SA8540P-ride, the register bank SDAM6 of the first PMIC is not
writable. Following recommendations provided during the review, use
SDAM2 from the second PMIC at offset 0xa0 instead.

Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Eric Chanudet <echanude@redhat.com>
Link: https://lore.kernel.org/r/20230809203506.1833205-1-echanude@redhat.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Eric Chanudet 2023-08-09 16:32:33 -04:00 committed by Bjorn Andersson
parent 605a981e53
commit e85cbb34f3
2 changed files with 25 additions and 1 deletions
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11
arch/arm64/boot/dts/qcom/sa8540p-pmics.dtsi
View File

@ -14,7 +14,7 @@
#address-cells = <1>;
#size-cells = <0>;
rtc@6000 {
pmm8540a_rtc: rtc@6000 {
compatible = "qcom,pm8941-rtc";
reg = <0x6000>, <0x6100>;
reg-names = "rtc", "alarm";
@ -39,6 +39,15 @@
#address-cells = <1>;
#size-cells = <0>;
pmm8540c_sdam_2: nvram@b110 {
compatible = "qcom,spmi-sdam";
reg = <0xb110>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xb110 0xb0>;
status = "disabled";
};
pmm8540c_gpios: gpio@c000 {
compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio";
reg = <0xc000>;

15
arch/arm64/boot/dts/qcom/sa8540p-ride.dts
View File

@ -407,6 +407,21 @@
status = "okay";
};
&pmm8540a_rtc {
nvmem-cells = <&rtc_offset>;
nvmem-cell-names = "offset";
status = "okay";
};
&pmm8540c_sdam_2 {
status = "okay";
rtc_offset: rtc-offset@a0 {
reg = <0xa0 0x4>;
};
};
&qup0 {
status = "okay";
};