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drm/amd/display: Fix DC mode screen flickering on DCN321
[ Upstream commit ce649bd2d8
]
[Why && How]
Screen flickering saw on 4K@60 eDP with high refresh rate external
monitor when booting up in DC mode. DC Mode Capping is disabled
which caused wrong UCLK being used.
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Leo Ma <hanghong.ma@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
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@ -547,8 +547,12 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
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* since we calculate mode support based on softmax being the max UCLK
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* since we calculate mode support based on softmax being the max UCLK
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* frequency.
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* frequency.
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*/
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*/
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dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
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if (dc->debug.disable_dc_mode_overwrite) {
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dc->clk_mgr->bw_params->dc_mode_softmax_memclk);
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dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz);
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dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz);
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} else
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dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
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dc->clk_mgr->bw_params->dc_mode_softmax_memclk);
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} else {
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} else {
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dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz);
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dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz);
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}
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}
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@ -581,8 +585,13 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
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/* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */
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/* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */
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if (clk_mgr_base->clks.p_state_change_support &&
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if (clk_mgr_base->clks.p_state_change_support &&
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(update_uclk || !clk_mgr_base->clks.prev_p_state_change_support) &&
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(update_uclk || !clk_mgr_base->clks.prev_p_state_change_support) &&
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!dc->work_arounds.clock_update_disable_mask.uclk)
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!dc->work_arounds.clock_update_disable_mask.uclk) {
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if (dc->clk_mgr->dc_mode_softmax_enabled && dc->debug.disable_dc_mode_overwrite)
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dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK,
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max((int)dc->clk_mgr->bw_params->dc_mode_softmax_memclk, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)));
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dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
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dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
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}
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if (clk_mgr_base->clks.num_ways != new_clocks->num_ways &&
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if (clk_mgr_base->clks.num_ways != new_clocks->num_ways &&
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clk_mgr_base->clks.num_ways > new_clocks->num_ways) {
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clk_mgr_base->clks.num_ways > new_clocks->num_ways) {
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