[ Upstream commit ecec7c9f29 ]
head is defined in idxd->evl as a shadow of head in the EVLSTATUS register.
There are two issues related to the shadow head:
1. Mismatch between the shadow head and the state of the EVLSTATUS
register:
If Event Log is supported, upon completion of the Enable Device command,
the Event Log head in the variable idxd->evl->head should be cleared to
match the state of the EVLSTATUS register. But the variable is not reset
currently, leading mismatch between the variable and the register state.
The mismatch causes incorrect processing of Event Log entries.
2. Unnecessary shadow head definition:
The shadow head is unnecessary as head can be read directly from the
EVLSTATUS register. Reading head from the register incurs no additional
cost because event log head and tail are always read together and
tail is already read directly from the register as required by hardware.
Remove the shadow Event Log head stored in idxd->evl to address the
mentioned issues.
Fixes: 244da66cda ("dmaengine: idxd: setup event log configuration")
Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/20240215024931.1739621-1-fenghua.yu@intel.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
[ Upstream commit bbcc1c83f3 ]
The Linked list element and pointer are not stored in the same memory as
the eDMA controller register. If the doorbell register is toggled before
the full write of the linked list a race condition error will occur.
In remote setup we can only use a readl to the memory to assure the full
write has occurred.
Fixes: 7e4b8a4fbe ("dmaengine: Add Synopsys eDMA IP version 0 support")
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
Link: https://lore.kernel.org/r/20240129-b4-feature_hdma_mainline-v7-6-8e8c1acb7a46@bootlin.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
[ Upstream commit 712a92a481 ]
The Linked list element and pointer are not stored in the same memory as
the HDMA controller register. If the doorbell register is toggled before
the full write of the linked list a race condition error will occur.
In remote setup we can only use a readl to the memory to assure the full
write has occurred.
Fixes: e74c39573d ("dmaengine: dw-edma: Add support for native HDMA")
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
Link: https://lore.kernel.org/r/20240129-b4-feature_hdma_mainline-v7-5-8e8c1acb7a46@bootlin.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
[ Upstream commit e2f6a57890 ]
Only the local interruption was configured, remote interrupt was left
behind. This patch fix it by setting stop and abort remote interrupts when
the DW_EDMA_CHIP_LOCAL flag is not set.
Fixes: e74c39573d ("dmaengine: dw-edma: Add support for native HDMA")
Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20240129-b4-feature_hdma_mainline-v7-4-8e8c1acb7a46@bootlin.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
[ Upstream commit 7b52ba8616 ]
Instead of setting HDMA_V0_LOCAL_ABORT_INT_EN bit, HDMA_V0_LOCAL_STOP_INT_EN
bit got set twice, due to which the abort interrupt is not getting generated for
HDMA. Fix it by setting the correct interrupt enable bit.
Fixes: e74c39573d ("dmaengine: dw-edma: Add support for native HDMA")
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
Link: https://lore.kernel.org/r/20240129-b4-feature_hdma_mainline-v7-2-8e8c1acb7a46@bootlin.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
[ Upstream commit cd665bfc75 ]
The current check of ch_en enabled to know the maximum number of available
hardware channels is wrong as it check the number of ch_en register set
but all of them are unset at probe. This register is set at the
dw_hdma_v0_core_start function which is run lately before a DMA transfer.
The HDMA IP have no way to know the number of hardware channels available
like the eDMA IP, then let set it to maximum channels and let the platform
set the right number of channels.
Fixes: e74c39573d ("dmaengine: dw-edma: Add support for native HDMA")
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
Link: https://lore.kernel.org/r/20240129-b4-feature_hdma_mainline-v7-1-8e8c1acb7a46@bootlin.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
commit 87a39071e0 upstream.
Initialize the qDMA irqs after the registers are configured so that
interrupts that may have been pending from a primary kernel don't get
processed by the irq handler before it is ready to and cause panic with
the following trace:
Call trace:
fsl_qdma_queue_handler+0xf8/0x3e8
__handle_irq_event_percpu+0x78/0x2b0
handle_irq_event_percpu+0x1c/0x68
handle_irq_event+0x44/0x78
handle_fasteoi_irq+0xc8/0x178
generic_handle_irq+0x24/0x38
__handle_domain_irq+0x90/0x100
gic_handle_irq+0x5c/0xb8
el1_irq+0xb8/0x180
_raw_spin_unlock_irqrestore+0x14/0x40
__setup_irq+0x4bc/0x798
request_threaded_irq+0xd8/0x190
devm_request_threaded_irq+0x74/0xe8
fsl_qdma_probe+0x4d4/0xca8
platform_drv_probe+0x50/0xa0
really_probe+0xe0/0x3f8
driver_probe_device+0x64/0x130
device_driver_attach+0x6c/0x78
__driver_attach+0xbc/0x158
bus_for_each_dev+0x5c/0x98
driver_attach+0x20/0x28
bus_add_driver+0x158/0x220
driver_register+0x60/0x110
__platform_driver_register+0x44/0x50
fsl_qdma_driver_init+0x18/0x20
do_one_initcall+0x48/0x258
kernel_init_freeable+0x1a4/0x23c
kernel_init+0x10/0xf8
ret_from_fork+0x10/0x18
Cc: stable@vger.kernel.org
Fixes: b092529e0a ("dmaengine: fsl-qdma: Add qDMA controller driver for Layerscape SoCs")
Signed-off-by: Curtis Klein <curtis.klein@hpe.com>
Signed-off-by: Yi Zhao <yi.zhao@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20240201220406.440145-1-Frank.Li@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit 9ba17defd9 upstream.
The 'nbytes' should be equivalent to burst * width in audio multi-fifo
setups. Given that the FIFO width is fixed at 32 bits, adjusts the burst
size for multi-fifo configurations to match the slave maxburst in the
configuration.
Cc: stable@vger.kernel.org
Fixes: 72f5801a4e ("dmaengine: fsl-edma: integrate v3 support")
Signed-off-by: Joy Zou <joy.zou@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20240131163318.360315-1-Frank.Li@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit df2515a179 upstream.
The PTDMA driver sets DMA masks in two different places for the same
device inconsistently. First call is in pt_pci_probe(), where it uses
48bit mask. The second call is in pt_dmaengine_register(), where it
uses a 64bit mask. Using 64bit dma mask causes IO_PAGE_FAULT errors
on DMA transfers between main memory and other devices.
Without the extra call it works fine. Additionally the second call
doesn't check the return value so it can silently fail.
Remove the superfluous dma_set_mask() call and only use 48bit mask.
Cc: stable@vger.kernel.org
Fixes: b0b4a6b105 ("dmaengine: ptdma: register PTDMA controller as a DMA resource")
Reviewed-by: Basavaraj Natikar <Basavaraj.Natikar@amd.com>
Signed-off-by: Tadeusz Struk <tstruk@gigaio.com>
Link: https://lore.kernel.org/r/20240222163053.13842-1-tstruk@gigaio.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit 9d739bccf2 upstream.
There is chip (ls1028a) errata:
The SoC may hang on 16 byte unaligned read transactions by QDMA.
Unaligned read transactions initiated by QDMA may stall in the NOC
(Network On-Chip), causing a deadlock condition. Stalled transactions will
trigger completion timeouts in PCIe controller.
Workaround:
Enable prefetch by setting the source descriptor prefetchable bit
( SD[PF] = 1 ).
Implement this workaround.
Cc: stable@vger.kernel.org
Fixes: b092529e0a ("dmaengine: fsl-qdma: Add qDMA controller driver for Layerscape SoCs")
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20240201215007.439503-1-Frank.Li@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
[ Upstream commit 6e2276203a ]
devm_kasprintf() returns a pointer to dynamically allocated memory
which can be NULL upon failure. Ensure the allocation was successful
by checking the pointer validity.
Signed-off-by: Kunwu Chan <chentao@kylinos.cn>
Link: https://lore.kernel.org/r/20240118031929.192192-1-chentao@kylinos.cn
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
[ Upstream commit cb95a4fa50 ]
We seem to have hit warnings of 'output may be truncated' which is fixed
by increasing the size of 'name'
drivers/dma/dw-edma/dw-hdma-v0-debugfs.c: In function ‘dw_hdma_v0_debugfs_on’:
drivers/dma/dw-edma/dw-hdma-v0-debugfs.c:125:50: error: ‘%d’ directive output may be truncated writing between 1 and 11 bytes into a region of size 8 [-Werror=format-truncation=]
125 | snprintf(name, sizeof(name), "%s:%d", CHANNEL_STR, i);
| ^~
drivers/dma/dw-edma/dw-hdma-v0-debugfs.c: In function ‘dw_hdma_v0_debugfs_on’:
drivers/dma/dw-edma/dw-hdma-v0-debugfs.c:142:50: error: ‘%d’ directive output may be truncated writing between 1 and 11 bytes into a region of size 8 [-Werror=format-truncation=]
142 | snprintf(name, sizeof(name), "%s:%d", CHANNEL_STR, i);
| ^~
drivers/dma/dw-edma/dw-edma-v0-debugfs.c: In function ‘dw_edma_debugfs_regs_wr’:
drivers/dma/dw-edma/dw-edma-v0-debugfs.c:193:50: error: ‘%d’ directive output may be truncated writing between 1 and 11 bytes into a region of size 8 [-Werror=format-truncation=]
193 | snprintf(name, sizeof(name), "%s:%d", CHANNEL_STR, i);
| ^~
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
[ Upstream commit 6386f6c995 ]
We seem to have hit warnings of 'output may be truncated' which is fixed
by increasing the size of 'irq_name'
drivers/dma/fsl-qdma.c: In function ‘fsl_qdma_irq_init’:
drivers/dma/fsl-qdma.c:824:46: error: ‘%d’ directive writing between 1 and 11 bytes into a region of size 10 [-Werror=format-overflow=]
824 | sprintf(irq_name, "qdma-queue%d", i);
| ^~
drivers/dma/fsl-qdma.c:824:35: note: directive argument in the range [-2147483641, 2147483646]
824 | sprintf(irq_name, "qdma-queue%d", i);
| ^~~~~~~~~~~~~~
drivers/dma/fsl-qdma.c:824:17: note: ‘sprintf’ output between 12 and 22 bytes into a destination of size 20
824 | sprintf(irq_name, "qdma-queue%d", i);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
[ Upstream commit 4042902408 ]
We seem to have hit warnings of 'output may be truncated' which is fixed
by increasing the size of 'dev_id'
drivers/dma/sh/shdmac.c: In function ‘sh_dmae_probe’:
drivers/dma/sh/shdmac.c:541:34: error: ‘%d’ directive output may be truncated writing between 1 and 10 bytes into a region of size 9 [-Werror=format-truncation=]
541 | "sh-dmae%d.%d", pdev->id, id);
| ^~
In function ‘sh_dmae_chan_probe’,
inlined from ‘sh_dmae_probe’ at drivers/dma/sh/shdmac.c:845:9:
drivers/dma/sh/shdmac.c:541:26: note: directive argument in the range [0, 2147483647]
541 | "sh-dmae%d.%d", pdev->id, id);
| ^~~~~~~~~~~~~~
drivers/dma/sh/shdmac.c:541:26: note: directive argument in the range [0, 19]
drivers/dma/sh/shdmac.c:540:17: note: ‘snprintf’ output between 11 and 21 bytes into a destination of size 16
540 | snprintf(sh_chan->dev_id, sizeof(sh_chan->dev_id),
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
541 | "sh-dmae%d.%d", pdev->id, id);
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
[ Upstream commit 306f5df81f ]
For RX channels, REG_BUS_WIDTH seems to default to a value of 0xf00, and
macOS preserves the upper bits when setting the configuration in the
lower ones. If we reset the upper bits to 0, this causes framing errors
on suspend/resume (the data stream "tears" and channels get swapped
around). Keeping the upper bits untouched, like the macOS driver does,
fixes this issue.
Signed-off-by: Hector Martin <marcan@marcan.st>
Reviewed-by: Martin Povišer <povik+lin@cutebit.org>
Signed-off-by: Martin Povišer <povik+lin@cutebit.org>
Link: https://lore.kernel.org/r/20231029170704.82238-1-povik+lin@cutebit.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
[ Upstream commit 3aa58cb513 ]
This dma_alloc_coherent() is undone neither in the remove function, nor in
the error handling path of fsl_qdma_probe().
Switch to the managed version to fix both issues.
Fixes: b092529e0a ("dmaengine: fsl-qdma: Add qDMA controller driver for Layerscape SoCs")
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Link: https://lore.kernel.org/r/7f66aa14f59d32b13672dde28602b47deb294e1f.1704621515.git.christophe.jaillet@wanadoo.fr
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
[ Upstream commit 968bc1d720 ]
This dma_alloc_coherent() is undone in the remove function, but not in the
error handling path of fsl_qdma_probe().
Switch to the managed version to fix the issue in the probe and simplify
the remove function.
Fixes: b092529e0a ("dmaengine: fsl-qdma: Add qDMA controller driver for Layerscape SoCs")
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Link: https://lore.kernel.org/r/a0ef5d0f5a47381617ef339df776ddc68ce48173.1704621515.git.christophe.jaillet@wanadoo.fr
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
[ Upstream commit bc9847c9ba ]
Propagate the TR response status to the device using BCDMA
split-channels. For example CSI-RX driver should be able to check if a
frame was not transferred completely (short packet) and needs to be
discarded.
Fixes: 25dcb5dd7b ("dmaengine: ti: New driver for K3 UDMA")
Signed-off-by: Jai Luthra <j-luthra@ti.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@gmail.com>
Link: https://lore.kernel.org/r/20240103-tr_resp_err-v1-1-2fdf6d48ab92@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
[ Upstream commit b73e43dcd7 ]
In case of long format of qDMA command descriptor, there are one frame
descriptor, three entries in the frame list and two data entries. So the
size of dma_pool_create for these three fields should be the same with
the total size of entries respectively, or the contents may be overwritten
by the next allocated descriptor.
Fixes: 7fdf9b05c7 ("dmaengine: fsl-dpaa2-qdma: Add NXP dpaa2 qDMA controller driver for Layerscape SoCs")
Signed-off-by: Guanhua Gao <guanhua.gao@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20240118162917.2951450-1-Frank.Li@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
[ Upstream commit f5c24d9451 ]
__dma_async_device_channel_register() can fail. In case of failure,
chan->local is freed (with free_percpu()), and chan->local is nullified.
When dma_async_device_unregister() is called (because of managed API or
intentionally by DMA controller driver), channels are unconditionally
unregistered, leading to this NULL pointer:
[ 1.318693] Unable to handle kernel NULL pointer dereference at virtual address 00000000000000d0
[...]
[ 1.484499] Call trace:
[ 1.486930] device_del+0x40/0x394
[ 1.490314] device_unregister+0x20/0x7c
[ 1.494220] __dma_async_device_channel_unregister+0x68/0xc0
Look at dma_async_device_register() function error path, channel device
unregistration is done only if chan->local is not NULL.
Then add the same condition at the beginning of
__dma_async_device_channel_unregister() function, to avoid NULL pointer
issue whatever the API used to reach this function.
Fixes: d2fb0a0438 ("dmaengine: break out channel registration")
Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/20231213160452.2598073-1-amelie.delaunay@foss.st.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
[ Upstream commit dc51b4442d ]
The eDMAv4 channel mux has a limitation where certain requests must use
even channels, while others must use odd numbers.
Add two flags (ARGS_EVEN_CH and ARGS_ODD_CH) to reflect this limitation.
The device tree source (dts) files need to be updated accordingly.
This issue was identified by the following commit:
commit a725990557 ("arm64: dts: imx93: Fix the dmas entries order")
Reverting channel orders triggered this problem.
Fixes: 72f5801a4e ("dmaengine: fsl-edma: integrate v3 support")
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20231114154824.3617255-2-Frank.Li@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
[ Upstream commit 744f5e7b69 ]
AM62x has 3 SPI channels where each channel has 4 TX and 4 RX threads.
This also fixes the thread numbers.
Signed-off-by: Ronald Wahl <ronald.wahl@raritan.com>
Fixes: 5ac6bfb587 ("dmaengine: ti: k3-psil: Add AM62x PSIL and PDMA data")
Reviewed-by: Jai Luthra <j-luthra@ti.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@gmail.com>
Link: https://lore.kernel.org/r/20231030190113.16782-1-rwahl@gmx.de
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
commit 4ee632c82d upstream.
Allocate channel count consistently increases due to a missing source ID
(srcid) cleanup in the fsl_edma_free_chan_resources() function at imx93
eDMAv4.
Reset 'srcid' at fsl_edma_free_chan_resources().
Cc: stable@vger.kernel.org
Fixes: 72f5801a4e ("dmaengine: fsl-edma: integrate v3 support")
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20231127214325.2477247-1-Frank.Li@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit 54bed6bafa upstream.
stm32_dma_get_burst() returns a negative error for invalid input, which
gets turned into a large u32 value in stm32_dma_prep_dma_memcpy() that
in turn triggers an assertion because it does not fit into a two-bit field:
drivers/dma/stm32-dma.c: In function 'stm32_dma_prep_dma_memcpy':
include/linux/compiler_types.h:354:38: error: call to '__compiletime_assert_282' declared with attribute error: FIELD_PREP: value too large for the field
_compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
^
include/linux/compiler_types.h:335:4: note: in definition of macro '__compiletime_assert'
prefix ## suffix(); \
^~~~~~
include/linux/compiler_types.h:354:2: note: in expansion of macro '_compiletime_assert'
_compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
#define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
^~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:68:3: note: in expansion of macro 'BUILD_BUG_ON_MSG'
BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ? \
^~~~~~~~~~~~~~~~
include/linux/bitfield.h:114:3: note: in expansion of macro '__BF_FIELD_CHECK'
__BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: "); \
^~~~~~~~~~~~~~~~
drivers/dma/stm32-dma.c:1237:4: note: in expansion of macro 'FIELD_PREP'
FIELD_PREP(STM32_DMA_SCR_PBURST_MASK, dma_burst) |
^~~~~~~~~~
As an easy workaround, assume the error can happen, so try to handle this
by failing stm32_dma_prep_dma_memcpy() before the assertion. It replicates
what is done in stm32_dma_set_xfer_param() where stm32_dma_get_burst() is
also used.
Fixes: 1c32d6c37c ("dmaengine: stm32-dma: use bitfield helpers")
Fixes: a2b6103b7a ("dmaengine: stm32-dma: Improve memory burst management")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Cc: stable@vger.kernel.org
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202311060135.Q9eMnpCL-lkp@intel.com/
Link: https://lore.kernel.org/r/20231106134832.1470305-1-amelie.delaunay@foss.st.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This is the 6.6.3 stable release
* tag 'v6.6.3': (526 commits)
Linux 6.6.3
drm/amd/display: Change the DMCUB mailbox memory location from FB to inbox
drm/amd/display: Clear dpcd_sink_ext_caps if not set
...
Signed-off-by: Jason Liu <jason.hui.liu@nxp.com>
Conflicts:
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
drivers/usb/dwc3/core.c
This is the 6.6.2 stable release
* tag 'v6.6.2': (634 commits)
Linux 6.6.2
btrfs: make found_logical_ret parameter mandatory for function queue_scrub_stripe()
btrfs: use u64 for buffer sizes in the tree search ioctls
...
Signed-off-by: Jason Liu <jason.hui.liu@nxp.com>
Conflicts:
drivers/clk/imx/clk-imx8mq.c
drivers/clk/imx/clk-imx8qxp.c
drivers/media/i2c/ov5640.c
drivers/misc/pci_endpoint_test.c
commit 03f25d53b1 upstream.
In case of the prep descriptor while the channel is already running, the
CCR register value stored into the channel could already have its EN bit
set. This would lead to a bad transfer since, at start transfer time,
enabling the channel while other registers aren't yet properly set.
To avoid this, ensure to mask the CCR_EN bit when storing the ccr value
into the mdma channel structure.
Fixes: a4ffb13c89 ("dmaengine: Add STM32 MDMA driver")
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Cc: stable@vger.kernel.org
Tested-by: Alain Volmat <alain.volmat@foss.st.com>
Link: https://lore.kernel.org/r/20231009082450.452877-1-amelie.delaunay@foss.st.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* origin/dma/edma: (31 commits)
LF-10579-02: dmaengine: fsl-edma-v3: add imx95 edma support
LF-10579-01: dt-bindings: dma: fsl-edma-v3: update binding for imx95
LF-8690-2: dmaengine: fsl-edma-v3: support edma src id check if using ch_mux
LF-8690-1: dt-bindings: dma: fsl-edma-v3: optimize binding doc
dmaengine: fsl-edma-v3: set the max CITER 0x7fff instead of 0x3fff
...
[ Upstream commit 83c761f568 ]
If pxad_alloc_desc() fails on the first dma_pool_alloc() call, then
sw_desc->nb_desc is zero.
In such a case pxad_free_desc() is called and it will BUG_ON().
Remove this erroneous BUG_ON().
It is also useless, because if "sw_desc->nb_desc == 0", then, on the first
iteration of the for loop, i is -1 and the loop will not be executed.
(both i and sw_desc->nb_desc are 'int')
Fixes: a57e16cf03 ("dmaengine: pxa: add pxa dmaengine driver")
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Link: https://lore.kernel.org/r/c8fc5563c9593c914fde41f0f7d1489a21b45a9a.1696676782.git.christophe.jaillet@wanadoo.fr
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
[ Upstream commit 14f6d31791 ]
Zero is not a valid IRQ for in-kernel code and the irq_of_parse_and_map()
function returns zero on error. So this check for valid IRQs should only
accept values > 0.
Fixes: 2b6b3b7420 ("ARM/dmaengine: edma: Merge the two drivers under drivers/dma/")
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
Acked-by: Peter Ujfalusi <peter.ujfalusi@gmail.com>
Link: https://lore.kernel.org/r/f15cb6a7-8449-4f79-98b6-34072f04edbc@moroto.mountain
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
[ Upstream commit 88928addee ]
idxd sub-drivers belong to bus dsa_bus_type. Thus, dsa_bus_type must be
registered in dsa bus init before idxd drivers can be registered.
But the order is wrong when both idxd and idxd_bus are builtin drivers.
In this case, idxd driver is compiled and linked before idxd_bus driver.
Since the initcall order is determined by the link order, idxd sub-drivers
are registered in idxd initcall before dsa_bus_type is registered
in idxd_bus initcall. idxd initcall fails:
[ 21.562803] calling idxd_init_module+0x0/0x110 @ 1
[ 21.570761] Driver 'idxd' was unable to register with bus_type 'dsa' because the bus was not initialized.
[ 21.586475] initcall idxd_init_module+0x0/0x110 returned -22 after 15717 usecs
[ 21.597178] calling dsa_bus_init+0x0/0x20 @ 1
To fix the issue, compile and link idxd_bus driver before idxd driver
to ensure the right registration order.
Fixes: d9e5481fca ("dmaengine: dsa: move dsa_bus_type out of idxd driver to standalone")
Reported-by: Michael Prinke <michael.prinke@intel.com>
Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Lijun Pan <lijun.pan@intel.com>
Tested-by: Lijun Pan <lijun.pan@intel.com>
Link: https://lore.kernel.org/r/20230924162232.1409454-1-fenghua.yu@intel.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
There are three edma controller one edma-v3 and two edma-v5 on A core.
The edma-v5 is similar with edma-v4.
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Joy Zou <joy.zou@nxp.com>
Support edma src id check in order to make sure ch_mux uniqueness.
The dma_spec->args[0] passes src id. The src id is equal to the chanid,
if the sdma controller channel allocation is fixed. This case doesn't
need to check src id because repeated src id will fail when it requests
channel.
The src id isn't related to chanid if the sdma controller channel
allocation is dynamic. So need check src id, and write the srcid to the
ch_mux register.
This patch checks the src id if it's using. It can avoid setting the same
srcid in different ch_mux.
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Joy Zou <joy.zou@nxp.com>
When playback 48KHz, 16 bit, 8 channel audio, period size can’t
be set >= 1024, otherwise it will fail with “cannot set hw params:
Invalid argument”.
For the case 1024 frames period size, 8 channel, 16bit case, The
period size in byte = 1024 * 2 * 8 = 16384 bytes. The edma driver
dma_set_max_seg_size(fsl_edma3->dma_dev.dev, 0x3fff), it will limit
the period size to be 16383 bytes.
There are two purposes of adding dma_set_max_seg_size. On the one
hand, it limits the size of memcpy by software trigger. On the other
hand , it can avoids the outs of bounds of CITER register. The CITER
is equal to data_len / nbytes. The nbytes is depend on dma client
addr_width * burst, the min value of the nbytes is one. The max value
of the CITER bit0-14 is 0x7fff when the minor loop channel linking
is disable by default.
I think the driver sets 0x3fff by mistake, So we set the max CITER
0x7fff as max_seg_size. The i.MX[8ulp/8qm/93] which has eDMA3/4 all
share same settings 0x7fff. However, if your period data len exceed
0x7fff, it still fail.
Signed-off-by: Joy Zou <joy.zou@nxp.com>
Acked-by: Dong Aisheng <aisheng.dong@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
With the case that device_pause() is called, but device_terminate_all()
isn't called before device_synchronize(), the channel descriptor
is not released, which cause next instance can't device_issue_pending()
correctly.
Call the fsl_edma3_terminate_all() if the status is DMA_PAUSED in
device_synchronize() to handle this issue.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Joy Zou <joy.zou@nxp.com>
In some case, the audio may need to support more than two fifoes.
The function of multiple fifo are added by Chancel Liu submit. So
the edma driver has supported multiple fifo for audio, I find the
variable name dual fifo is not match with multiple fifo function.
This patch only optimize the variable name that change dual fifo
into multi fifo.
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Joy Zou <joy.zou@nxp.com>
Add edma-v3 AHB and edma-v4 AXI support for imx93.
The edma AHB support 31 channels. Channels and peripherals are
one-to-one corresponding. The edma AXI support 64 channels.
Channels are dynamically allocated.
Add fsl_edma3_engine struct member bus_axi in order to differentiate
edma AHB and AXI. Add fsl_edma3_engine struct member dmaclk and
fsl_edma3_drvdata struct member has_chclk due to the all channels
share edma clocks. It's different from 8ulp that each channel have
its own clock. Add fsl_edma3_engine struct member has_chmux because
the edma AHB not support Channel Multiplexor Configuration.
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Joy Zou <joy.zou@nxp.com>
The nbytes in vtcd only have 10 valid bits with MLOFF exist case,
so can't use whole 30bits for nbytes, which cause issue with micfil
case.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Chancel Liu <chancel.liu@nxp.com>
Add has_pd into drvdata to support i.mx8ulp which has no dma
power domain feature.
Add edma mp in dts since i.mx8ulp may need it, while scfw will
touch MP in scfw, but now we just map it without any touching.
There are clocks for every channel and dmamux for choosing the source id
from dts on i.mx8ulp.
Note: dma_spec->args[0] is changed to source/event id on i.mx8ulp, not
channel id on i.mx8qm/qxp since any channel could be freely configured by
dmamux to any source/event on i.mx8ulp.
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
(cherry picked from commit 87ee321a52)
Checking ACTIVE bit to ensure channel stop indeed, otherwise, there is risk
that illegal memory touch after channel not stopped with buffer freed.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
(cherry picked from commit 48cea8ae90)
S32V234 eDMA has two transmission IRQs assigned per channels 0-15 and
16-31, instead of one, like VF610/LS1028A, or 16, like i.MX 7ULP, which is
why this platform needs a custom IRQ initialization function.
Signed-off-by: Stoica Cosmin-Stefan <cosmin.stoica@nxp.com>
Signed-off-by: Stefan-Gabriel Mirea <stefan-gabriel.mirea@nxp.com>
Acked-by: Robin Gong <yibin.gong@nxp.com>
To prepare the eDMA driver for S32V234 support, the "DMA transfer complete"
interrupt lines need to be freed (and therefore stored) in a uniform way.
After this commit, fsl_edma2_irq_init() will no longer accept an arbitrary
number of interrupts in the device tree, but only a pre-established number
of 17 interrupts, as the documentation (fsl-edma.txt) requires.
Signed-off-by: Stefan-Gabriel Mirea <stefan-gabriel.mirea@nxp.com>
Acked-by: Robin Gong <yibin.gong@nxp.com>
Add suspend to save channel registers and resume to restore them back since
edmav3 may powered off in suspend.
Reviewed-by: S.j. Wang <shengjiu.wang@nxp.com>
Reviewed-by: Andy Duan <fugang.duan@nxp.com>
Acked-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
edma interrupt maybe happened during reboot or watchdog reset, meanwhile
gic never power down on i.mx8QM/QXP, thus the unexpect irq will come in
once edma driver request irq at probe phase. Unfortunately, at that time
that edma channel's power domain which power-up by customer driver such
as audio/uart driver may not be ready, so kernel panic triggered once
touch such edma registers which still not power up in interrupt handler.
This patch move request irq from probe to alloc dma channel so that edma
channel's power domain has already been powered, besides, clear meaningless
interrupt before request irq.
Acked-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Joy Zou <joy.zou@nxp.com>
There is Audio dual fifo cause that fill fifo one by one and
loop back after every minor loop:
-- fill the first 32bit width fifo
-- fill the next 32bit width fifo
-- +MLOFF signed offset after the above two FIFOs filled
-- loop back to the first step to handle the next minor loop.
edma has dual fifo mode feature for audio cyclic. Besides dual fifo,
there is also multiple fifo use case. In this patch MLOFF field of
TCD register is modified to support multiple fifo. Correspondingly,
the burst should be set to the suitable value. For example it is set
to the number of channels if there is 1 channel in per fifo.
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Chancel Liu <chancel.liu@nxp.com>
Signed-off-by: Joy Zou <joy.zou@nxp.com>
The working on the verification of upstream edma driver is still in progress.
Let's use the local version first for the rebase.
Revert "dmaengine: fsl-edma: integrate v3 support"
This reverts commit 72f5801a4e.
Revert "dmaengine: fsl-edma: move tcd into struct fsl_dma_chan"
This reverts commit 7536f8b371.
Revert "dmaengine: fsl-edma: refactor chan_name setup and safety"
This reverts commit 9b05554c5c.
Revert "dmaengine: fsl-edma: move clearing of register interrupt into setup_irq function"
This reverts commit f5b3ba52f3.
Revert "dmaengine: fsl-edma: refactor using devm_clk_get_enabled"
This reverts commit a9903de3aa.
Revert "dmaengine: fsl-edma: simply ATTR_DSIZE and ATTR_SSIZE by using ffs()"
This reverts commit ee2dda0646.
Revert "dmaengine: fsl-edma: move common IRQ handler to common.c"
This reverts commit 79434f9b97.
Revert "dmaengine: fsl-edma: Remove enum edma_version"
This reverts commit c26e611433.
Revert "dmaengine: fsl-edma: transition from bool fields to bitmask flags in drvdata"
This reverts commit 9e006b2439.
Revert "dmaengine: fsl-edma: clean up EXPORT_SYMBOL_GPL in fsl-edma-common.c"
This reverts commit 66aac8ea0a.
Fix typo introduced from the commit 9a06b8f28f ("LF-9509: dma: pxp_dma_v3:
fix dereference after null check issue") which causes pxp timeout when run
epdc test on MX8ULP EVK ('/unit_tests/Display/mxc_epdc_v2_fb_test.out').
...
[ 223.598322] pxp_dispatch_thread: task is timeout
[ 223.630619] imx_epdc_v2_fb 2db30000.epdc: PxP operation failed due to timeout
[ 223.637898] imx_epdc_v2_fb 2db30000.epdc: Unable to complete PxP update task: pre_prcoess.
Change back to non-inverted RGB565
...
Signed-off-by: Robby Cai <robby.cai@nxp.com>
Reviewed-by: G.N. Zhou <guoniu.zhou@nxp.com>
(cherry picked from commit a069b2188d)
In pxp_is_v3(), it call pxp->devdata, but it out of null check for
pxp->devdata, so maybe refer null data when lut_transform is true.
Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
(cherry picked from commit 9a06b8f28f)
When pxp read pixel data by fetch engine and output by store engine.
The performance is very low, about 50Mpixel/s when the bytes of both
read and write burst are the default value 8. While increase both
read and write burst bytes to 64, the performance will be improved
to about 125Mpixel/s.
Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
(cherry picked from commit 519de8586c)
PXP_IOC_FLUSH_PHYMEM ioctl implements support for cache coherency
of buffers previously allocated by the PXP driver using
PXP_IOC_GET_PHYMEM ioctl, hence associated to its PXP driver
handle.
This change adds the option to handle dma coherency on a dma-buf
issued by a generic exporter.
Handle associated to buffers allocated by PXP driver can not be null.
Therefore null handle is used by implementation as criteria to fall
back onto the dma-buf file descriptor passed in arguments, keeping
the backward compatibility.
Signed-off-by: Julien Vuillaumier <julien.vuillaumier@nxp.com>
Reviewed-by: G.N. Zhou <guoniu.zhou@nxp.com>
When input format of PS engine is monochrome, such as Y8 or Y4,
the low 16 bits of PS_VBUF are used as the U/V data in the data
path instead of sourcing U/V data from external buffers. In this
case it represents a fixed value for U/V data.
Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
When run g2d sample test, pxp will report timeout issue. The reason
is that BGRA32 format is used in the case and driver will select AS
engine as input source. But from PXP datasheet, As can't do a simple
copy operation since it usually need to co-work with PS engine which
mean the output pixel value will determined by both AS and PS, such
as raster operation "AS OR PS" which usually used in legacy blending
operation. So add this workaround to fix this issue.
Reproduce steps:
/opt/g2d_samples/g2d_wayland_shm_test
Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
PS engine doesn't support RGB format with alpha channel, so it will discard
alpha value in RGBA/ARGB when PXP carry data from source to destination. The
workaround enable ALPHA_A porter_duff and use source blend mode, so it will
keep the alpha component as same in source buffer.
Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
The case is that source buffer is YUYV format and need to convert it
to ABGR32 and do rotation operation. But it will fail due to the reason
as bellow:
Driver will select PS as input engine according to input format(YUYV)
and OUT engine will be used as output engine since PS can't work with
STORE engine, but OUT engine don't support ABGR32 format.
When do rotation operation, ROTATION2(iMX93 reference manual) will be
selected first, but it only can work with fetch engine due to PXP's
limitation(TKT0603343), so driver need to clean it and select ROTATION1
engine to do the rotation operation.
This patch fix this issue by adding ABGR32 format for OUT engine and
selecting ROTATION1 for PS/AS engine
Reproduce steps as bellow and run on iMX93 platform:
/opt/g2d_samples/g2d_basic_test
Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
PXP block size is selected as 16x16 pixels by default in order to request
data more efficient. So driver also need to set each module which support
block size to 16x16. This patch is used to set input fetch engine block
size to 16x16.
Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
Fill input fetch engine upper left X-coordinate(in pixels) of the active
surface of the total input memory by frame boundary size when user don't
configure them.
Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
Enable input fetch engine arbitration bit for iMX93 platform when use its
two channel simultaneously since only one AXI bus interface is connected
to PXP fetch engine channel in order to balance system performance. For
other platform which use PXP don't have this design, so set arbitration
bit as platform data and only enable it for iMX93 platform(TKT0601126).
Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
The selected modules by user case in PXP pipeline will be configured
and enabled in pxp_2d_task_config() , so don't need to enable unused
modules and re-enable the used modules in pxp_start()
Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
The offset of U/V relative to Y buffer address base in PS engine is
wrong when format is multi-plane YUV format and crop enabled. So
correct it.
Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
../drivers/dma/pxp/pxp_device.c: In function 'pxp_dmabuf_ops_map':
../drivers/dma/pxp/pxp_device.c:666:40: error: 'struct dma_buf' has no member named 'lock'
666 | struct mutex *lock = &db_attach->dmabuf->lock;
| ^~
../drivers/dma/pxp/pxp_device.c:666:15: warning: unused variable 'lock' [-Wunused-variable]
666 | struct mutex *lock = &db_attach->dmabuf->lock;
| ^~~~
Remove internal dma-buf lock as it's removed in new framework and dma-buf reservation
is guaranteed to be locked by importers during the mapping operations.
Signed-off-by: Robby Cai <robby.cai@nxp.com>
Reviewed-by: Guoniu.zhou <guoniu.zhou@nxp.com>
CSC2 engine in PXP has IC bug(TKT272216) and fixed after 7D PXP version.
Driver update new CSC coefficient provided by PXP IP owner(MLK-25625-02).
But when run e-ink case, it can't do clear operation after applying the
patch. We don't know reason until now, so add a temporary patch to fix it
and will remove after finding the root cause.
Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
Since upstream commit 7938f421816 ("dma-buf-map: Rename to iosys-map")
the dma-buf-map names need to be updated.
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Select block size to 16x16 pixel blocks for PXP primary path in order
to improve PXP performance
Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
Config block size to 16x16 for input fetch and store engine in order to
improve PXP performance
Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
Config write burst size to 64 bytes in order to improve PXP performance
Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
Correct csc2 coefficient due to PXP issue(TKT272216). It apply to PXP
version after than iMX7D
Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Tested-by: Jared Hu <jared.hu@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
In current pxp driver, U and V address are caculated by driver when input/output
format is multi-plane format, such as NV12. But for some cases, user space want
to set U and V address by themself, so expose multi address settting for the case
Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Tested-by: Jared Hu <jared.hu@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
CC drivers/dma/pxp/pxp_device.o
drivers/dma/pxp/pxp_device.c:358:8: warning: implicit conversion from enumeration type
'enum dma_data_direction' to different enumeration type 'enum dma_transfer_direction' [-Wenum-conversion]
DMA_TO_DEVICE,
To reproduce the warnings:
1) Install clang 12:
wget https://apt.llvm.org/llvm.sh
chmod +x llvm.sh
sudo ./llvm.sh 12
2) Build kernel with clang:
export PATH=/usr/lib/llvm-12/bin/:$PATH LLVM=1
make ARCH=arm64 imx_v8_defconfig
make ARCH=arm64
Signed-off-by: Robby Cai <robby.cai@nxp.com>
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
drivers/dma/pxp/pxp_dma_v3.c:7769:15: warning: equality comparison with extraneous parentheses [-Wparentheses-equality]
if ((output == enode->adjvex)) {
~~~~~~~^~~~~~~~~~~~~~~~
drivers/dma/pxp/pxp_dma_v3.c:7769:15: note: remove extraneous parentheses around the comparison to silence this warning
if ((output == enode->adjvex)) {
~ ^ ~
drivers/dma/pxp/pxp_dma_v3.c:7769:15: note: use '=' to turn this equality comparison into an assignment
if ((output == enode->adjvex)) {
To reproduce the warnings:
1) Install clang 12:
wget https://apt.llvm.org/llvm.sh
chmod +x llvm.sh
sudo ./llvm.sh 12
2) Build kernel with clang:
export PATH=/usr/lib/llvm-12/bin/:$PATH LLVM=1
make ARCH=arm64 imx_v8_defconfig
make ARCH=arm64
Signed-off-by: Robby Cai <robby.cai@nxp.com>
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Fixed together with LF-5068, just make the coverity checking system no complain.
actually there's no potential issue for out-of-bounds access.
Signed-off-by: Robby Cai <robby.cai@nxp.com>
Reviewed-by: G.N. Zhou <guoniu.zhou@nxp.com>
In linux-nxp repo, -Wimplicit-fallthrough is set to 5, so it causes
warning for /* fall through */ in switch case statement. So the patch
is used to fix it
Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
When pxp driver probe, it will do software reset and reconfigure
operation. For iMX8ULP, power domain will be turned off in runtime
suspend and the status will be missed, so need to do software reset
and reconfigure operation again. But for other platform, such as 7D,
it's not necessary.
Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
Fix segmentation fault when run pxp lib unit test on iMX8ULP platform
Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Reviewed-by : Robby.Cai <robby.cai@nxp.com>
