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c4cf17f1e6
commit f8f235e5bb upstream.
Sandybridge GTT has new cache control bits in PTE, which controls
graphics page cache in LLC or LLC/MLC, so we need to extend the mask
function to respect the new bits.
And set cache control to always LLC only by default on Gen6.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
21 lines
427 B
C
21 lines
427 B
C
/*
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* Common Intel AGPGART and GTT definitions.
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*/
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#ifndef _INTEL_GTT_H
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#define _INTEL_GTT_H
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#include <linux/agp_backend.h>
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/* This is for Intel only GTT controls.
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*
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* Sandybridge: AGP_USER_CACHED_MEMORY default to LLC only
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*/
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#define AGP_USER_CACHED_MEMORY_LLC_MLC (AGP_USER_TYPES + 2)
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#define AGP_USER_UNCACHED_MEMORY (AGP_USER_TYPES + 4)
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/* flag for GFDT type */
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#define AGP_USER_CACHED_MEMORY_GFDT (1 << 3)
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#endif
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