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https://github.com/nxp-imx/linux-imx.git
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2ea72d2ba8
SNVS HP state is read incorrectly because there is Software dependency between SECVIO and CAAM driver. Added code to read SNVS version ID register which contain non-zero constants to identify the endianness of the device. This register includes a 16-bit field called IP_ID, and seems to have one of four different values 0x003A, 0x003C, 0x003E or 0x003F. Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Reviewed-by: Pankaj Gupta <pankaj.gupta@nxp.com> Reviewed-by: Horia Geanta <horia.geanta@nxp.com>
246 lines
8.4 KiB
C
246 lines
8.4 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
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/*
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* SNVS hardware register-level view
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*
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* Copyright 2012-2015 Freescale Semiconductor, Inc.
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* Copyright 2016-2019 NXP
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*/
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#ifndef SNVSREGS_H
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#define SNVSREGS_H
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#include <linux/types.h>
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#include <linux/io.h>
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/*
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* SNVS High Power Domain
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* Includes security violations, HA counter, RTC, alarm
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*/
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struct snvs_hp {
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u32 lock; /* HPLR - HP Lock */
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u32 cmd; /* HPCOMR - HP Command */
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u32 ctl; /* HPCR - HP Control */
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u32 secvio_intcfg; /* HPSICR - Security Violation Int Config */
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u32 secvio_ctl; /* HPSVCR - Security Violation Control */
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u32 status; /* HPSR - HP Status */
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u32 secvio_status; /* HPSVSR - Security Violation Status */
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u32 ha_counteriv; /* High Assurance Counter IV */
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u32 ha_counter; /* High Assurance Counter */
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u32 rtc_msb; /* Real Time Clock/Counter MSB */
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u32 rtc_lsb; /* Real Time Counter LSB */
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u32 time_alarm_msb; /* Time Alarm MSB */
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u32 time_alarm_lsb; /* Time Alarm LSB */
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};
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#define HP_LOCK_HAC_LCK 0x00040000
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#define HP_LOCK_HPSICR_LCK 0x00020000
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#define HP_LOCK_HPSVCR_LCK 0x00010000
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#define HP_LOCK_MKEYSEL_LCK 0x00000200
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#define HP_LOCK_TAMPCFG_LCK 0x00000100
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#define HP_LOCK_TAMPFLT_LCK 0x00000080
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#define HP_LOCK_SECVIO_LCK 0x00000040
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#define HP_LOCK_GENP_LCK 0x00000020
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#define HP_LOCK_MONOCTR_LCK 0x00000010
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#define HP_LOCK_CALIB_LCK 0x00000008
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#define HP_LOCK_SRTC_LCK 0x00000004
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#define HP_LOCK_ZMK_RD_LCK 0x00000002
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#define HP_LOCK_ZMK_WT_LCK 0x00000001
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#define HP_CMD_NONPRIV_AXS 0x80000000
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#define HP_CMD_HAC_STOP 0x00080000
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#define HP_CMD_HAC_CLEAR 0x00040000
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#define HP_CMD_HAC_LOAD 0x00020000
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#define HP_CMD_HAC_CFG_EN 0x00010000
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#define HP_CMD_SNVS_MSTR_KEY 0x00002000
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#define HP_CMD_PROG_ZMK 0x00001000
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#define HP_CMD_SW_LPSV 0x00000400
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#define HP_CMD_SW_FSV 0x00000200
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#define HP_CMD_SW_SV 0x00000100
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#define HP_CMD_LP_SWR_DIS 0x00000020
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#define HP_CMD_LP_SWR 0x00000010
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#define HP_CMD_SSM_SFNS_DIS 0x00000004
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#define HP_CMD_SSM_ST_DIS 0x00000002
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#define HP_CMD_SMM_ST 0x00000001
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#define HP_CTL_TIME_SYNC 0x00010000
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#define HP_CTL_CAL_VAL_SHIFT 10
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#define HP_CTL_CAL_VAL_MASK (0x1f << HP_CTL_CALIB_SHIFT)
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#define HP_CTL_CALIB_EN 0x00000100
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#define HP_CTL_PI_FREQ_SHIFT 4
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#define HP_CTL_PI_FREQ_MASK (0xf << HP_CTL_PI_FREQ_SHIFT)
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#define HP_CTL_PI_EN 0x00000008
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#define HP_CTL_TIMEALARM_EN 0x00000002
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#define HP_CTL_RTC_EN 0x00000001
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#define HP_SECVIO_INTEN_EN 0x10000000
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#define HP_SECVIO_INTEN_SRC5 0x00000020
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#define HP_SECVIO_INTEN_SRC4 0x00000010
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#define HP_SECVIO_INTEN_SRC3 0x00000008
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#define HP_SECVIO_INTEN_SRC2 0x00000004
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#define HP_SECVIO_INTEN_SRC1 0x00000002
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#define HP_SECVIO_INTEN_SRC0 0x00000001
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#define HP_SECVIO_INTEN_ALL 0x8000003f
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#define HP_SECVIO_ICTL_CFG_SHIFT 30
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#define HP_SECVIO_ICTL_CFG_MASK (0x3 << HP_SECVIO_ICTL_CFG_SHIFT)
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#define HP_SECVIO_ICTL_CFG5_SHIFT 5
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#define HP_SECVIO_ICTL_CFG5_MASK (0x3 << HP_SECVIO_ICTL_CFG5_SHIFT)
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#define HP_SECVIO_ICTL_CFG_DISABLE 0
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#define HP_SECVIO_ICTL_CFG_NONFATAL 1
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#define HP_SECVIO_ICTL_CFG_FATAL 2
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#define HP_SECVIO_ICTL_CFG4_FATAL 0x00000010
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#define HP_SECVIO_ICTL_CFG3_FATAL 0x00000008
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#define HP_SECVIO_ICTL_CFG2_FATAL 0x00000004
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#define HP_SECVIO_ICTL_CFG1_FATAL 0x00000002
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#define HP_SECVIO_ICTL_CFG0_FATAL 0x00000001
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#define HP_STATUS_ZMK_ZERO 0x80000000
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#define HP_STATUS_OTPMK_ZERO 0x08000000
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#define HP_STATUS_OTPMK_SYN_SHIFT 16
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#define HP_STATUS_OTPMK_SYN_MASK (0x1ff << HP_STATUS_OTPMK_SYN_SHIFT)
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#define HP_STATUS_SSM_ST_SHIFT 8
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#define HP_STATUS_SSM_ST_MASK (0xf << HP_STATUS_SSM_ST_SHIFT)
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#define HP_STATUS_SSM_ST_INIT 0
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#define HP_STATUS_SSM_ST_HARDFAIL 1
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#define HP_STATUS_SSM_ST_SOFTFAIL 3
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#define HP_STATUS_SSM_ST_INITINT 8
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#define HP_STATUS_SSM_ST_CHECK 9
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#define HP_STATUS_SSM_ST_NONSECURE 11
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#define HP_STATUS_SSM_ST_TRUSTED 13
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#define HP_STATUS_SSM_ST_SECURE 15
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#define HP_SECVIOST_ZMK_ECC_FAIL 0x08000000 /* write to clear */
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#define HP_SECVIOST_ZMK_SYN_SHIFT 16
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#define HP_SECVIOST_ZMK_SYN_MASK (0x1ff << HP_SECVIOST_ZMK_SYN_SHIFT)
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#define HP_SECVIOST_SECVIO5 0x00000020
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#define HP_SECVIOST_SECVIO4 0x00000010
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#define HP_SECVIOST_SECVIO3 0x00000008
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#define HP_SECVIOST_SECVIO2 0x00000004
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#define HP_SECVIOST_SECVIO1 0x00000002
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#define HP_SECVIOST_SECVIO0 0x00000001
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#define HP_SECVIOST_SECVIOMASK 0x0000003f
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/*
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* SNVS Low Power Domain
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* Includes glitch detector, SRTC, alarm, monotonic counter, ZMK
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*/
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struct snvs_lp {
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u32 lock;
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u32 ctl;
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u32 mstr_key_ctl; /* Master Key Control */
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u32 secvio_ctl; /* Security Violation Control */
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u32 tamper_filt_cfg; /* Tamper Glitch Filters Configuration */
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u32 tamper_det_cfg; /* Tamper Detectors Configuration */
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u32 status;
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u32 srtc_msb; /* Secure Real Time Clock/Counter MSB */
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u32 srtc_lsb; /* Secure Real Time Clock/Counter LSB */
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u32 time_alarm; /* Time Alarm */
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u32 smc_msb; /* Secure Monotonic Counter MSB */
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u32 smc_lsb; /* Secure Monotonic Counter LSB */
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u32 pwr_glitch_det; /* Power Glitch Detector */
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u32 gen_purpose;
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u32 zmk[8]; /* Zeroizable Master Key */
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};
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#define LP_LOCK_MKEYSEL_LCK 0x00000200
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#define LP_LOCK_TAMPDET_LCK 0x00000100
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#define LP_LOCK_TAMPFLT_LCK 0x00000080
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#define LP_LOCK_SECVIO_LCK 0x00000040
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#define LP_LOCK_GENP_LCK 0x00000020
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#define LP_LOCK_MONOCTR_LCK 0x00000010
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#define LP_LOCK_CALIB_LCK 0x00000008
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#define LP_LOCK_SRTC_LCK 0x00000004
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#define LP_LOCK_ZMK_RD_LCK 0x00000002
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#define LP_LOCK_ZMK_WT_LCK 0x00000001
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#define LP_CTL_CAL_VAL_SHIFT 10
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#define LP_CTL_CAL_VAL_MASK (0x1f << LP_CTL_CAL_VAL_SHIFT)
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#define LP_CTL_CALIB_EN 0x00000100
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#define LP_CTL_SRTC_INVAL_EN 0x00000010
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#define LP_CTL_WAKE_INT_EN 0x00000008
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#define LP_CTL_MONOCTR_EN 0x00000004
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#define LP_CTL_TIMEALARM_EN 0x00000002
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#define LP_CTL_SRTC_EN 0x00000001
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#define LP_MKEYCTL_ZMKECC_SHIFT 8
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#define LP_MKEYCTL_ZMKECC_MASK (0xff << LP_MKEYCTL_ZMKECC_SHIFT)
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#define LP_MKEYCTL_ZMKECC_EN 0x00000010
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#define LP_MKEYCTL_ZMKECC_VAL 0x00000008
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#define LP_MKEYCTL_ZMKECC_PROG 0x00000004
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#define LP_MKEYCTL_MKSEL_SHIFT 0
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#define LP_MKEYCTL_MKSEL_MASK (3 << LP_MKEYCTL_MKSEL_SHIFT)
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#define LP_MKEYCTL_MK_OTP 0
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#define LP_MKEYCTL_MK_ZMK 2
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#define LP_MKEYCTL_MK_COMB 3
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#define LP_SECVIO_CTL_SRC5 0x20
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#define LP_SECVIO_CTL_SRC4 0x10
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#define LP_SECVIO_CTL_SRC3 0x08
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#define LP_SECVIO_CTL_SRC2 0x04
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#define LP_SECVIO_CTL_SRC1 0x02
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#define LP_SECVIO_CTL_SRC0 0x01
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#define LP_TAMPFILT_EXT2_EN 0x80000000
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#define LP_TAMPFILT_EXT2_SHIFT 24
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#define LP_TAMPFILT_EXT2_MASK (0x1f << LP_TAMPFILT_EXT2_SHIFT)
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#define LP_TAMPFILT_EXT1_EN 0x00800000
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#define LP_TAMPFILT_EXT1_SHIFT 16
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#define LP_TAMPFILT_EXT1_MASK (0x1f << LP_TAMPFILT_EXT1_SHIFT)
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#define LP_TAMPFILT_WM_EN 0x00000080
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#define LP_TAMPFILT_WM_SHIFT 0
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#define LP_TAMPFILT_WM_MASK (0x1f << LP_TAMPFILT_WM_SHIFT)
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#define LP_TAMPDET_OSC_BPS 0x10000000
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#define LP_TAMPDET_VRC_SHIFT 24
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#define LP_TAMPDET_VRC_MASK (3 << LP_TAMPFILT_VRC_SHIFT)
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#define LP_TAMPDET_HTDC_SHIFT 20
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#define LP_TAMPDET_HTDC_MASK (3 << LP_TAMPFILT_HTDC_SHIFT)
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#define LP_TAMPDET_LTDC_SHIFT 16
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#define LP_TAMPDET_LTDC_MASK (3 << LP_TAMPFILT_LTDC_SHIFT)
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#define LP_TAMPDET_POR_OBS 0x00008000
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#define LP_TAMPDET_PFD_OBS 0x00004000
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#define LP_TAMPDET_ET2_EN 0x00000400
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#define LP_TAMPDET_ET1_EN 0x00000200
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#define LP_TAMPDET_WMT2_EN 0x00000100
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#define LP_TAMPDET_WMT1_EN 0x00000080
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#define LP_TAMPDET_VT_EN 0x00000040
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#define LP_TAMPDET_TT_EN 0x00000020
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#define LP_TAMPDET_CT_EN 0x00000010
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#define LP_TAMPDET_MCR_EN 0x00000004
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#define LP_TAMPDET_SRTCR_EN 0x00000002
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#define LP_STATUS_SECURE
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#define LP_STATUS_NONSECURE
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#define LP_STATUS_SCANEXIT 0x00100000 /* all write 1 clear here on */
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#define LP_STATUS_EXT_SECVIO 0x00010000
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#define LP_STATUS_ET2 0x00000400
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#define LP_STATUS_ET1 0x00000200
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#define LP_STATUS_WMT2 0x00000100
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#define LP_STATUS_WMT1 0x00000080
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#define LP_STATUS_VTD 0x00000040
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#define LP_STATUS_TTD 0x00000020
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#define LP_STATUS_CTD 0x00000010
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#define LP_STATUS_PGD 0x00000008
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#define LP_STATUS_MCR 0x00000004
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#define LP_STATUS_SRTCR 0x00000002
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#define LP_STATUS_LPTA 0x00000001
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/* Full SNVS register page, including version/options */
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struct snvs_full {
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struct snvs_hp hp;
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struct snvs_lp lp;
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u32 rsvd[731]; /* deadspace 0x08c-0xbf7 */
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/* Version / Revision / Option ID space - end of register page */
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u32 vid; /* 0xbf8 HP Version ID (VID 1) */
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u32 opt_rev; /* 0xbfc HP Options / Revision (VID 2) */
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};
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#define SNVS_HPVIDR_BLOCK_ID 16 /* SNVS Block ID 31-16 bit */
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#define SNVS_ID1 58 /* SNVS Block ID 0x3A */
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#define SNVS_ID2 60 /* SNVS Block ID 0x3C */
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#define SNVS_ID3 62 /* SNVS Block ID 0x3E */
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#define SNVS_ID4 63 /* SNVS Block ID 0x3F */
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#endif /* SNVSREGS_H */
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