Alison Schofield 124451bbc2 cxl/region: Verify target positions using the ordered target list ... [ Upstream commit 82a3e3a235 ] When a root decoder is configured the interleave target list is read from the BIOS populated CFMWS structure. Per the CXL spec 3.1 Table 9-22 the target list is in interleave order. The CXL driver populates its decoder target list in the same order and stores it in 'struct cxl_switch_decoder' field "@target: active ordered target list in current decoder configuration" Given the promise of an ordered list, the driver can stop duplicating the work of BIOS and simply check target positions against the ordered list during region configuration. The simplified check against the ordered list is presented here. A follow-on patch will remove the unused code. For Modulo arithmetic this is not a fix, only a simplification. For XOR arithmetic this is a fix for HB IW of 3,6,12. Fixes: f9db85bfec ("cxl/acpi: Support CXL XOR Interleave Math (CXIMS)") Signed-off-by: Alison Schofield <alison.schofield@intel.com> Reviewed-by: Dan Williams <dan.j.williams@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://patch.msgid.link/35d08d3aba08fee0f9b86ab1cef0c25116ca8a55.1719980933.git.alison.schofield@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Sasha Levin <sashal@kernel.org>		2024-09-12 11:11:37 +02:00
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core.h	cxl/region: Move cxl_dpa_to_region() work to the region driver	2024-07-05 09:34:06 +02:00
hdm.c	cxl/region: check interleave capability	2024-07-05 09:34:07 +02:00
Makefile	cxl/pci: Find and register CXL PMU devices	2023-05-30 11:20:35 -07:00
mbox.c	cxl/core: Fix potential payload size confusion in cxl_mem_get_poison()	2024-05-02 16:32:35 +02:00
memdev.c	cxl/region: Move cxl_dpa_to_region() work to the region driver	2024-07-05 09:34:06 +02:00
pci.c	cxl/pci: Fix disabling memory if DVSEC CXL Range does not match a CFMWS window	2024-03-01 13:34:59 +01:00
pmem.c	cxl/memdev: Formalize endpoint port linkage	2023-06-25 14:31:33 -07:00
pmu.c	cxl/pmu: Ensure put_device on pmu devices	2024-01-10 17:16:59 +01:00
port.c	cxl/port: Fix missing target list lock	2024-01-25 15:35:55 -08:00
region.c	cxl/region: Verify target positions using the ordered target list	2024-09-12 11:11:37 +02:00
regs.c	cxl/core/regs: Fix usage of map->reg_type in cxl_decode_regblock() before assigned	2024-04-17 11:19:27 +02:00
suspend.c	PM: CXL: Disable suspend	2022-04-22 16:09:42 -07:00
trace.c	cxl/trace: Add an HPA to cxl_poison trace events	2023-04-23 11:46:13 -07:00
trace.h	cxl/trace: Correct DPA field masks for general_media & dram events	2024-06-12 11:12:42 +02:00