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https://github.com/nxp-imx/linux-imx.git
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34bbf282e3
Extend the driver to also support the GPIO controller found on the LS1046AQDS QIXIS CPLD. For usecases in which the parent device (the QIXIS CPLD) does not define a regmap for its memory area, create the driver's own regmap which will get passed to gpio-regmap trough devm_gpio_regmap_register(). In this case, the offset inside of the regmap will be zero since the regmap points directly to the desired register. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
131 lines
3.0 KiB
C
131 lines
3.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Layerscape GPIO CPLD driver
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*
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* Copyright 2023 NXP
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*/
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#include <linux/device.h>
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#include <linux/gpio/driver.h>
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#include <linux/gpio/regmap.h>
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#include <linux/kernel.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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enum qixis_cpld_gpio_type {
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LX2160ARDB_CPLD_GPIO = 0,
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LS1046AQDS_STAT_PRES2_CPLD_GPIO,
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};
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struct qixis_cpld_gpio_config {
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enum qixis_cpld_gpio_type type;
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unsigned int input_lines;
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};
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static struct qixis_cpld_gpio_config lx2160ardb_cpld_gpio_cfg = {
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.type = LX2160ARDB_CPLD_GPIO,
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.input_lines = GENMASK(7, 1),
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};
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static struct qixis_cpld_gpio_config ls1046aqds_stat_pres2_cpld_gpio_cfg = {
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.type = LS1046AQDS_STAT_PRES2_CPLD_GPIO,
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.input_lines = GENMASK(7, 0),
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};
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static int qixis_cpld_gpio_get_direction(struct gpio_regmap *gpio, unsigned int offset)
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{
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struct qixis_cpld_gpio_config *cfg = gpio_regmap_get_drvdata(gpio);
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if (cfg->input_lines & BIT(offset))
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return GPIO_LINE_DIRECTION_IN;
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else
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return GPIO_LINE_DIRECTION_OUT;
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}
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static const struct regmap_config regmap_config_8r_8v = {
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.reg_bits = 8,
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.val_bits = 8,
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};
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static int qixis_cpld_gpio_probe(struct platform_device *pdev)
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{
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const struct qixis_cpld_gpio_config *cfg;
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struct gpio_regmap_config config = {0};
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struct regmap *regmap;
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void __iomem *reg;
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u32 base;
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int ret;
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if (!pdev->dev.parent)
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return -ENODEV;
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cfg = device_get_match_data(&pdev->dev);
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if (!cfg)
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return -ENODEV;
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ret = device_property_read_u32(&pdev->dev, "reg", &base);
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if (ret)
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return ret;
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regmap = dev_get_regmap(pdev->dev.parent, NULL);
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if (!regmap) {
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/* In case there is no regmap configured by the parent device,
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* create our own.
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*/
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reg = devm_platform_ioremap_resource(pdev, 0);
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if (!reg)
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return -ENODEV;
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regmap = devm_regmap_init_mmio(&pdev->dev, reg, ®map_config_8r_8v);
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if (!regmap)
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return -ENODEV;
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/* In this case, the offset of our register is 0 inside the
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* regmap area that we just created.
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*/
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base = 0;
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}
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config.get_direction = qixis_cpld_gpio_get_direction;
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config.drvdata = (void *)cfg;
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config.regmap = regmap;
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config.parent = &pdev->dev;
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config.ngpio_per_reg = 8;
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config.ngpio = 8;
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switch (cfg->type) {
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case LX2160ARDB_CPLD_GPIO:
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case LS1046AQDS_STAT_PRES2_CPLD_GPIO:
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config.reg_dat_base = GPIO_REGMAP_ADDR(base);
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config.reg_set_base = GPIO_REGMAP_ADDR(base);
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break;
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}
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return PTR_ERR_OR_ZERO(devm_gpio_regmap_register(&pdev->dev, &config));
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}
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static const struct of_device_id qixis_cpld_gpio_of_match[] = {
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{
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.compatible = "fsl,lx2160a-rdb-qixis-cpld-gpio",
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.data = &lx2160ardb_cpld_gpio_cfg
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},
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{
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.compatible = "fsl,ls1046a-qds-qixis-stat-pres2-cpld-gpio",
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.data = &ls1046aqds_stat_pres2_cpld_gpio_cfg
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},
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{}
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};
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MODULE_DEVICE_TABLE(of, qixis_cpld_gpio_of_match);
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static struct platform_driver qixis_cpld_gpio_driver = {
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.probe = qixis_cpld_gpio_probe,
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.driver = {
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.name = "gpio-qixis-cpld",
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.of_match_table = qixis_cpld_gpio_of_match,
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},
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};
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module_platform_driver(qixis_cpld_gpio_driver);
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