mirror of
https://github.com/nxp-imx/linux-imx.git
synced 2025-09-02 18:06:13 +02:00
346d37854e
The MAX96789/MAX96791 family of serializers convert dual MIPI DSI, four-lane input port data to dual Maxim Integrated’s GMSL 1 or 2 high-speed serial link protocol. They also send and receive side-channel and peripheral control data, enabling full-duplex, single-wire, transmission of video and bidirectional data. This driver adds the core support with separate drivers adding support for video or audio. GPIO support is included in the core part as this is not a GPIO controller in the Linux sense. It performs GPIO tunneling, translating GPIO pin transitions from local side to the remote side and viceversa. Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com> Reviewed-by: Robert Chiras <robert.chiras@nxp.com>
493 lines
15 KiB
C
493 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Core MFD support for Analog Devices MAX96789 MIPI-DSI serializer
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*
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* Copyright 2023 NXP
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*/
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#include <linux/device.h>
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#include <linux/of.h>
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#include <linux/of_graph.h>
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#include <linux/mfd/core.h>
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#include <linux/module.h>
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#include <linux/regmap.h>
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#include <linux/of_gpio.h>
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#include <linux/regulator/consumer.h>
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#include <linux/mfd/maxim_serdes.h>
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#include <linux/mfd/max96789.h>
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static const struct mfd_cell max96789_mfd_cells[] = {
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{
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.name = "max96789-dsi0",
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.of_compatible = "maxim,max96789-dsi",
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.of_reg = 0,
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.use_of_reg = true,
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},
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{
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.name = "max96789-dsi1",
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.of_compatible = "maxim,max96789-dsi",
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.of_reg = 1,
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.use_of_reg = true,
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},
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};
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static bool max96789_writable_register(struct device *dev,
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unsigned int reg)
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{
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switch (reg) {
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case MAX96789_DEV_ID ... MAX96789_DEV_VIDEO_CAP:
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case MAX96789_DEV_LF_STATUS1 ... MAX96789_DEV_LF_STATUS2:
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case MAX96789_TCTRL_PWR0:
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case MAX96789_TCTRL_CTRL3:
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case MAX96789_TCTRL_INTR3:
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case MAX96789_TCTRL_INTR5:
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case MAX96789_TCTRL_INTR7:
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case MAX96789_CC_I2C_7:
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case MAX96789_CC_BITLEN_LSB:
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case MAX96789_AUD_TX_AUDIO_TX5(0):
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case MAX96789_AUD_TX_AUDIO_TX5(1):
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case MAX96789_AUD_RX_AUDIO_RX9(0):
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case MAX96789_AUD_RX_AUDIO_RX9(1):
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case MAX96789_SPI_7:
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case MAX96789_WM_5:
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case MAX96789_DUALVIEW_DV_PPL_L(0) ... MAX96789_DUALVIEW_DV2(0):
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case MAX96789_DUALVIEW_DV_PPL_L(1) ... MAX96789_DUALVIEW_DV2(1):
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case MAX96789_GMSL1_14(0):
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case MAX96789_GMSL1_14(1):
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case MAX96789_GMSL1_16(0):
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case MAX96789_GMSL1_16(1):
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case MAX96789_GMSL1_CC_I2C_RETR_CNT(0) ... MAX96789_GMSL1_CC_CRC_ERRCNT(0):
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case MAX96789_GMSL1_CC_I2C_RETR_CNT(1) ... MAX96789_GMSL1_CC_CRC_ERRCNT(1):
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case MAX96789_GMSL1_C8(0):
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case MAX96789_GMSL1_C8(1):
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case MAX96789_MISC_HS_VS_X ... MAX96789_MISC_HS_VS_U:
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case MAX96789_ASYM_DV_ASYM27:
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case MAX96789_RLMS_7(0):
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case MAX96789_RLMS_7(1):
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case MAX96789_RLMS_EYEMONERRCNTL(0) ... MAX96789_RLMS_EYEMONVALCNTH(0):
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case MAX96789_RLMS_EYEMONERRCNTL(1) ... MAX96789_RLMS_EYEMONVALCNTH(1):
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return false;
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default:
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return true;
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}
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}
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static bool max96789_volatile_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case MAX96789_TCTRL_CTRL3:
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case MAX96789_TCTRL_INTR3:
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case MAX96789_TCTRL_INTR5:
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case MAX96789_TCTRL_INTR7:
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case MAX96789_MIPI_DSI_CTRL_STATUS(DSI_PORT_A):
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case MAX96789_MIPI_DSI_CTRL_STATUS(DSI_PORT_B):
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case MAX96789_VID_TX_VIDEO_TX2(VIDEO_PIPE_X):
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case MAX96789_VID_TX_VIDEO_TX2(VIDEO_PIPE_Y):
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case MAX96789_VID_TX_VIDEO_TX2(VIDEO_PIPE_Z):
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case MAX96789_VID_TX_VIDEO_TX2(VIDEO_PIPE_U):
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case MAX96789_MISC_HS_VS_X:
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case MAX96789_MISC_HS_VS_Y:
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case MAX96789_MISC_HS_VS_Z:
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case MAX96789_MISC_HS_VS_U:
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case MAX96789_MIPI_RX_PHY0_LP_ERR:
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case MAX96789_MIPI_RX_PHY0_HS_ERR:
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case MAX96789_MIPI_RX_PHY1_LP_ERR:
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case MAX96789_MIPI_RX_PHY1_HS_ERR:
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case MAX96789_MIPI_RX_PHY2_LP_ERR:
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case MAX96789_MIPI_RX_PHY2_HS_ERR:
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case MAX96789_MIPI_RX_PHY3_LP_ERR:
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case MAX96789_MIPI_RX_PHY3_HS_ERR:
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case MAX96789_GPIO_A(0):
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case MAX96789_GPIO_A(1):
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case MAX96789_GPIO_A(2):
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case MAX96789_GPIO_A(3):
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case MAX96789_GPIO_A(4):
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case MAX96789_GPIO_A(5):
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case MAX96789_GPIO_A(6):
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case MAX96789_GPIO_A(7):
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case MAX96789_GPIO_A(8):
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case MAX96789_GPIO_A(9):
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case MAX96789_GPIO_A(10):
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case MAX96789_GPIO_A(11):
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case MAX96789_GPIO_A(12):
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case MAX96789_GPIO_A(13):
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case MAX96789_GPIO_A(14):
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case MAX96789_GPIO_A(15):
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case MAX96789_GPIO_A(16):
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case MAX96789_GPIO_A(17):
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case MAX96789_GPIO_A(18):
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case MAX96789_GPIO_A(19):
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case MAX96789_GPIO_A(20):
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return true;
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default:
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return false;
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}
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}
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const struct regmap_config max96789_regmap_cfg = {
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.name = "max96789",
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.reg_bits = 16,
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.val_bits = 8,
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.max_register = MAX96789_DPLL_AUD_SSPLL_DPLL_3(1),
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.writeable_reg = max96789_writable_register,
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.volatile_reg = max96789_volatile_reg,
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.cache_type = REGCACHE_RBTREE,
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};
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EXPORT_SYMBOL_GPL(max96789_regmap_cfg);
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static int max96789_get_dt_gmsl_links_params(struct max96789 *max96789)
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{
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struct device *dev = max96789->dev;
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unsigned int link_types[GMSL_MAX_LINKS];
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int ret;
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int val;
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ret = of_property_read_u32_array(dev->of_node, "maxim,gmsl-links-types",
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link_types, GMSL_MAX_LINKS);
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if (ret < 0) {
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dev_warn(dev, "GMSL links types not set in DT, defaulting to pin configuration\n");
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ret = regmap_read(max96789->regmap, MAX96789_DEV_LINK, &val);
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if (ret)
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return -EIO;
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max96789->gmsl_links_types[GMSL_LINK_A] = !!(val & GMSL2_A);
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max96789->gmsl_links_types[GMSL_LINK_B] = !!(val & GMSL2_B);
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} else {
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max96789->gmsl_links_types[GMSL_LINK_A] = (link_types[GMSL_LINK_A] & 0x3) - 1;
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max96789->gmsl_links_types[GMSL_LINK_B] = (link_types[GMSL_LINK_B] & 0x3) - 1;
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}
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max96789->gmsl2_dual_link = of_property_present(dev->of_node, "maxim,gmsl2-dual-link");
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if (max96789->gmsl2_dual_link &&
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(max96789->gmsl_links_types[GMSL_LINK_A] == LINK_TYPE_GMSL1 ||
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max96789->gmsl_links_types[GMSL_LINK_B] == LINK_TYPE_GMSL1)) {
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dev_warn(dev, "ignoring dual-link DT setting because at least one link is GMSL1\n");
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max96789->gmsl2_dual_link = false;
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}
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ret = of_property_read_s32(dev->of_node, "maxim,gmsl2-link-speed", &val);
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if (ret < 0) {
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dev_warn(dev, "GMSL2 link speed not set in DT, using pin configuration\n");
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ret = regmap_read(max96789->regmap, MAX96789_DEV_CH_CTRL, &val);
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if (ret)
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return -EIO;
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max96789->gmsl2_link_speed = val & TX_RATE_MASK;
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return 0;
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}
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if (!ret && val != 3 && val != 6) {
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dev_err(dev, "wrong GMSL speed set in DT\n");
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return -EINVAL;
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}
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max96789->gmsl2_link_speed = val / 3;
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return 0;
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}
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static int max96789_set_link_params(struct max96789 *max96789)
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{
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struct device *dev = max96789->dev;
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unsigned int reg_val;
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max96789->gmsl_links_need_reset = true;
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/* setting link types */
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reg_val = max96789->gmsl_links_types[GMSL_LINK_A] == LINK_TYPE_GMSL2 ? GMSL2_A : 0;
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reg_val |= max96789->gmsl_links_types[GMSL_LINK_B] == LINK_TYPE_GMSL2 ? GMSL2_B : 0;
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regmap_update_bits(max96789->regmap, MAX96789_DEV_LINK, GMSL2_A | GMSL2_B, reg_val);
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/* activating dual-link */
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if (!max96789->gmsl2_dual_link)
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return 0;
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regmap_read(max96789->regmap, MAX96789_DEV_VIDEO_CAP, ®_val);
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if (!(reg_val & DUAL_CPBL_N)) {
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dev_dbg(dev, "configuring dual-link mode\n");
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reg_val = LINK_EN_A | LINK_EN_B | GMSL2_A | GMSL2_B;
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regmap_update_bits(max96789->regmap, MAX96789_DEV_LINK, reg_val, reg_val);
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/*
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* Set link configuration but do not reset the link just yet, this will be
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* done by the remote deserializer device once it probes.
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*/
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regmap_update_bits(max96789->regmap, MAX96789_TCTRL_CTRL0,
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LINK_CFG_MASK | AUTO_LINK, LINK_CFG_DUAL_LINK);
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}
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return 0;
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}
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static void max96789_set_gpio_pull_resistor(struct max96789 *max96789, unsigned int gpio_pin,
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unsigned int pull_type, unsigned int pull_strength)
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{
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regmap_update_bits(max96789->regmap, MAX96789_GPIO_B(gpio_pin), PULL_UPDN_SEL_MASK,
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pull_type << PULL_UPDN_SEL_SHIFT);
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regmap_update_bits(max96789->regmap, MAX96789_GPIO_A(gpio_pin), RES_CFG,
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pull_strength ? RES_CFG : 0);
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}
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static void max96789_set_gpio_direction(struct max96789 *max96789, unsigned int gpio_pin,
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unsigned int direction)
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{
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regmap_update_bits(max96789->regmap, MAX96789_GPIO_A(gpio_pin), GPIO_OUT_DIS, direction);
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}
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static void max96789_set_gpio_gmsl_tx(struct max96789 *max96789, unsigned int gpio_pin, bool en)
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{
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regmap_update_bits(max96789->regmap, MAX96789_GPIO_A(gpio_pin), GPIO_TX_EN,
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en ? GPIO_TX_EN : 0);
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}
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static void max96789_set_gpio_gmsl_rx(struct max96789 *max96789, unsigned int gpio_pin, bool en)
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{
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regmap_update_bits(max96789->regmap, MAX96789_GPIO_A(gpio_pin), GPIO_RX_EN,
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en ? GPIO_RX_EN : 0);
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}
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static void max96789_set_gpio_rx_id(struct max96789 *max96789, unsigned int local_gpio_pin,
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unsigned int remote_gpio_pin)
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{
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regmap_update_bits(max96789->regmap, MAX96789_GPIO_C(local_gpio_pin), GPIO_RX_ID_MASK,
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remote_gpio_pin << GPIO_RX_ID_SHIFT);
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}
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static void max96789_config_standalone_gpio(struct max96789 *max96789, unsigned int gpio_pin,
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unsigned int *pin_configs)
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{
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struct device *dev = max96789->dev;
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dev_dbg(dev, "config standalone gpio %d: dir = %d, pull_type = %d, strength = %d\n",
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gpio_pin, pin_configs[0], pin_configs[1], pin_configs[2]);
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max96789_set_gpio_direction(max96789, gpio_pin, pin_configs[0]);
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max96789_set_gpio_pull_resistor(max96789, gpio_pin, pin_configs[1], pin_configs[2]);
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max96789_set_gpio_gmsl_tx(max96789, gpio_pin, false);
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max96789_set_gpio_gmsl_rx(max96789, gpio_pin, false);
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}
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static void max96789_config_tunneled_gpio(struct max96789 *max96789, unsigned int local_gpio_pin,
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unsigned int *pin_configs, unsigned int remote_gpio_pin)
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{
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struct device *dev = max96789->dev;
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dev_dbg(dev, "config tunneled gpio %d: dir = %d, pull_type = %d, strength = %d\n",
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local_gpio_pin, pin_configs[0], pin_configs[1], pin_configs[2]);
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max96789_set_gpio_direction(max96789, local_gpio_pin, pin_configs[0]);
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max96789_set_gpio_pull_resistor(max96789, local_gpio_pin, pin_configs[1], pin_configs[2]);
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max96789_set_gpio_gmsl_tx(max96789, local_gpio_pin, pin_configs[0] ? true : false);
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max96789_set_gpio_gmsl_rx(max96789, local_gpio_pin, pin_configs[0] ? false : true);
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if (!pin_configs[0])
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max96789_set_gpio_rx_id(max96789, local_gpio_pin, remote_gpio_pin);
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}
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static int max96789_set_gpio_pin(struct max96789 *max96789, struct device_node *gpios_node,
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struct device_node *pin_node)
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{
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struct device *dev = max96789->dev;
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unsigned int local_gpio_pin, remote_gpio_pin;
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unsigned int pin_configs[3];
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int ret;
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struct device_node *ep, *remote_pin_node;
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ret = of_property_read_u32(pin_node, "reg", &local_gpio_pin);
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if (ret)
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return ret;
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ret = of_property_read_u32_array(pin_node, "maxim,pin_config", pin_configs, 3);
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if (ret) {
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dev_err(dev, "Bad gpio pin configuration.\n");
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return ret;
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}
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ep = of_graph_get_endpoint_by_regs(gpios_node, local_gpio_pin, 0);
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if (!ep) {
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max96789_config_standalone_gpio(max96789, local_gpio_pin, pin_configs);
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return 0;
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}
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remote_pin_node = of_graph_get_remote_port(ep);
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if (!remote_pin_node) {
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dev_err(dev, "Couldn't find corresponding remote gpio pin\n");
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of_node_put(ep);
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return -ENODEV;
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}
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of_node_put(ep);
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ret = of_property_read_u32(remote_pin_node, "reg", &remote_gpio_pin);
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if (ret) {
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of_node_put(remote_pin_node);
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return ret;
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}
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of_node_put(remote_pin_node);
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max96789_config_tunneled_gpio(max96789, local_gpio_pin, pin_configs, remote_gpio_pin);
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return 0;
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}
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static int max96789_set_gpios(struct max96789 *max96789)
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{
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struct device *dev = max96789->dev;
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struct device_node *dev_node = dev->of_node;
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struct device_node *gpios_node, *child;
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int ret;
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/* look for a gpio-config node that contains gpios' pin configurations */
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gpios_node = of_get_child_by_name(dev_node, "gpio-config");
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if (!gpios_node) {
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dev_info(dev, "No gpios DT node found, using GPIOs defaults.\n");
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return 0;
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}
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for_each_child_of_node(gpios_node, child) {
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ret = max96789_set_gpio_pin(max96789, gpios_node, child);
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if (ret) {
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of_node_put(gpios_node);
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of_node_put(child);
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return ret;
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}
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}
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of_node_put(gpios_node);
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return 0;
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}
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static void max96789_finish_link_setup(void *data)
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{
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struct max96789 *max96789 = data;
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int ret;
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unsigned int reg_val;
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if (max96789->gmsl_links_types[GMSL_LINK_A] == LINK_TYPE_GMSL2 ||
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max96789->gmsl_links_types[GMSL_LINK_B] == LINK_TYPE_GMSL2)
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regmap_update_bits(max96789->regmap, MAX96789_DEV_CH_CTRL, TX_RATE_MASK,
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max96789->gmsl2_link_speed << TX_RATE_SHIFT);
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if (max96789->gmsl_links_used == 2 || max96789->gmsl2_dual_link)
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regmap_update_bits(max96789->regmap, MAX96789_DEV_LINK,
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LINK_EN_B | LINK_EN_A, LINK_EN_B | LINK_EN_A);
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if (max96789->gmsl_links_used == 2)
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regmap_update_bits(max96789->regmap, MAX96789_TCTRL_CTRL0,
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LINK_CFG_MASK | AUTO_LINK | RESET_ONESHOT,
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LINK_CFG_SPLITTER | RESET_ONESHOT);
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else if (max96789->gmsl2_dual_link)
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regmap_update_bits(max96789->regmap, MAX96789_TCTRL_CTRL0,
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LINK_CFG_MASK | AUTO_LINK | RESET_ONESHOT,
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LINK_CFG_DUAL_LINK | RESET_ONESHOT);
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ret = regmap_read_poll_timeout(max96789->regmap, MAX96789_TCTRL_INTR7, reg_val,
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reg_val & (LOCK_B | LOCK_A), 500, 300000);
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if (ret < 0) {
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dev_err(max96789->dev, "%s: GMSL links not locked, MAX96789_TCTRL_INTR7 = 0x%02x\n",
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__func__, reg_val);
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return;
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}
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max96789->link_setup_finished = true;
|
|
}
|
|
|
|
int max96789_dev_init(struct max96789 *max96789, ulong expected_dev_id)
|
|
{
|
|
struct device *dev = max96789->dev;
|
|
int ret;
|
|
unsigned int reg_val;
|
|
|
|
dev_set_drvdata(dev, max96789);
|
|
|
|
ret = devm_regulator_get_enable_optional(dev, "v12p0");
|
|
if (ret < 0 && ret != -ENODEV)
|
|
return ret;
|
|
|
|
/* power-up completes in approx 2ms, according to specifications */
|
|
usleep_range(2000, 2500);
|
|
|
|
ret = regmap_read(max96789->regmap, MAX96789_DEV_ID, &max96789->id);
|
|
if (ret) {
|
|
dev_err(dev, "Failed to read device id: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
if (max96789->id != expected_dev_id) {
|
|
dev_err(dev, "Wrong Maxim serializer detected: id 0x%x\n",
|
|
max96789->id);
|
|
return -ENODEV;
|
|
}
|
|
|
|
ret = regmap_read(max96789->regmap, MAX96789_DEV_REV, &max96789->rev);
|
|
if (ret) {
|
|
dev_err(dev, "Failed to read device revision: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
max96789->rev &= DEV_REV_MASK;
|
|
|
|
dev_info(dev, "Found Maxim serializer with id 0x%x and rev 0x%x\n",
|
|
max96789->id, max96789->rev);
|
|
|
|
/* Documentation states that:
|
|
*
|
|
* "The following register writes must be made to ensure proper
|
|
* serializer operation. Without these writes, the operation of the
|
|
* device as specified in the datasheet cannot be guaranteed."
|
|
*
|
|
* However, there's no further documentation of that register or its
|
|
* fields. So, the next command will use hard-coded values.
|
|
*/
|
|
ret = regmap_update_bits(max96789->regmap, 0x302, 0x07, 0x10);
|
|
if (ret) {
|
|
dev_err(dev, "Cannot increase voltage to clock system: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = max96789_get_dt_gmsl_links_params(max96789);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* wait for at least one GMSL link to lock with default settings*/
|
|
ret = regmap_read_poll_timeout(max96789->regmap, MAX96789_TCTRL_CTRL3, reg_val,
|
|
reg_val & LOCKED, 500, 300000);
|
|
if (ret < 0) {
|
|
dev_err(max96789->dev, "%s: no GMSL link locked, MAX96789_TCTRL_CTRL3 = 0x%02x\n",
|
|
__func__, reg_val);
|
|
return -ENODEV;
|
|
}
|
|
|
|
ret = max96789_set_link_params(max96789);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = max96789_set_gpios(max96789);
|
|
if (ret)
|
|
return ret;
|
|
|
|
maxim_serdes_chain_register_local(dev, max96789->gmsl_links_used,
|
|
max96789_finish_link_setup, max96789);
|
|
|
|
devm_mfd_add_devices(max96789->dev, PLATFORM_DEVID_AUTO, max96789_mfd_cells,
|
|
ARRAY_SIZE(max96789_mfd_cells),
|
|
NULL, 0, NULL);
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(max96789_dev_init);
|
|
|
|
MODULE_DESCRIPTION("MAX96789 core MFD driver");
|
|
MODULE_AUTHOR("Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>");
|
|
MODULE_LICENSE("GPL v2");
|