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https://github.com/nxp-imx/linux-imx.git
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1bf849437a
fix the build issue that cause by unaligned octal dtr function for macronix spi-nor chips. Signed-off-by: Han Xu <han.xu@nxp.com>
358 lines
12 KiB
C
358 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2005, Intec Automation Inc.
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* Copyright (C) 2014, Freescale Semiconductor, Inc.
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*/
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#include <linux/mtd/spi-nor.h>
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#include "core.h"
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#define SPINOR_OP_RD_CR2 0x71 /* Read configuration register 2 */
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#define SPINOR_OP_WR_CR2 0x72 /* Write configuration register 2 */
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#define SPINOR_REG_MXIC_CR2_MODE 0x00000000 /* For setting octal DTR mode */
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#define SPINOR_REG_MXIC_OPI_DTR_EN 0x2 /* Enable Octal DTR */
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#define SPINOR_REG_MXIC_SPI_EN 0x0 /* Enable SPI */
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#define SPINOR_OP_OPI_DTR_RD 0xEE /* OPI DTR first read opcode */
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static int
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mx25l25635_post_bfpt_fixups(struct spi_nor *nor,
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const struct sfdp_parameter_header *bfpt_header,
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const struct sfdp_bfpt *bfpt)
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{
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/*
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* MX25L25635F supports 4B opcodes but MX25L25635E does not.
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* Unfortunately, Macronix has re-used the same JEDEC ID for both
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* variants which prevents us from defining a new entry in the parts
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* table.
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* We need a way to differentiate MX25L25635E and MX25L25635F, and it
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* seems that the F version advertises support for Fast Read 4-4-4 in
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* its BFPT table.
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*/
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if (bfpt->dwords[SFDP_DWORD(5)] & BFPT_DWORD5_FAST_READ_4_4_4)
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nor->flags |= SNOR_F_4B_OPCODES;
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return 0;
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}
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static const struct spi_nor_fixups mx25l25635_fixups = {
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.post_bfpt = mx25l25635_post_bfpt_fixups,
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};
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/**
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* spi_nor_macronix_octal_dtr_enable() - Enable octal DTR on Macronix flashes.
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* @nor: pointer to a 'struct spi_nor'
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* @enable: whether to enable Octal DTR or switch back to SPI
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*
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* Return: 0 on success, -errno otherwise.
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*/
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static int spi_nor_macronix_set_octal_dtr(struct spi_nor *nor, bool enable)
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{
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struct spi_mem_op op;
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u8 *buf = nor->bouncebuf, i;
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int ret;
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/* Set/unset the octal and DTR enable bits. */
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ret = spi_nor_write_enable(nor);
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if (ret)
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return ret;
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if (enable) {
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buf[0] = SPINOR_REG_MXIC_OPI_DTR_EN;
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} else {
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/*
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* The register is 1-byte wide, but 1-byte transactions are not
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* allowed in 8D-8D-8D mode. Since there is no register at the
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* next location, just initialize the value to 0 and let the
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* transaction go on.
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*/
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buf[0] = SPINOR_REG_MXIC_SPI_EN;
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buf[1] = 0x0;
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}
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op = (struct spi_mem_op)
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SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_CR2, 1),
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SPI_MEM_OP_ADDR(4, SPINOR_REG_MXIC_CR2_MODE, 1),
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SPI_MEM_OP_NO_DUMMY,
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SPI_MEM_OP_DATA_OUT(enable ? 1 : 2, buf, 1));
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if (!enable)
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spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR);
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ret = spi_mem_exec_op(nor->spimem, &op);
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if (ret)
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return ret;
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/* Read flash ID to make sure the switch was successful. */
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op = (struct spi_mem_op)
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SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 1),
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SPI_MEM_OP_ADDR(enable ? 4 : 0, 0, 1),
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SPI_MEM_OP_DUMMY(enable ? 4 : 0, 1),
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SPI_MEM_OP_DATA_IN(SPI_NOR_MAX_ID_LEN, buf, 1));
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if (enable)
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spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR);
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ret = spi_mem_exec_op(nor->spimem, &op);
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if (ret)
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return ret;
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if (enable) {
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for (i = 0; i < nor->info->id_len; i++)
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if (buf[i * 2] != nor->info->id[i])
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return -EINVAL;
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} else {
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if (memcmp(buf, nor->info->id, nor->info->id_len))
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return -EINVAL;
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}
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return 0;
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}
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static void octaflash_default_init(struct spi_nor *nor)
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{
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nor->params->set_octal_dtr = spi_nor_macronix_set_octal_dtr;
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}
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static struct spi_nor_fixups octaflash_fixups = {
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.default_init = octaflash_default_init,
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};
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static int mx25uw51345g_post_sfdp_fixup(struct spi_nor *nor)
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{
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nor->params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR;
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spi_nor_set_read_settings(&nor->params->reads[SNOR_CMD_READ_8_8_8_DTR],
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0, 20, SPINOR_OP_OPI_DTR_RD,
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SNOR_PROTO_8_8_8_DTR);
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return 0;
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}
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static struct spi_nor_fixups mx25uw51345g_fixups = {
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.default_init = octaflash_default_init,
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.post_sfdp = mx25uw51345g_post_sfdp_fixup,
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};
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static const struct flash_info macronix_nor_parts[] = {
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/* Macronix */
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{ "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1)
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NO_SFDP_FLAGS(SECT_4K) },
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{ "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4)
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NO_SFDP_FLAGS(SECT_4K) },
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{ "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8)
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NO_SFDP_FLAGS(SECT_4K) },
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{ "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16) },
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{ "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32)
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NO_SFDP_FLAGS(SECT_4K) },
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{ "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64)
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NO_SFDP_FLAGS(SECT_4K) },
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{ "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64)
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NO_SFDP_FLAGS(SECT_4K) },
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{ "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128)
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NO_SFDP_FLAGS(SECT_4K) },
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{ "mx25u2033e", INFO(0xc22532, 0, 64 * 1024, 4)
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NO_SFDP_FLAGS(SECT_4K) },
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{ "mx25u3235f", INFO(0xc22536, 0, 64 * 1024, 64)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
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SPI_NOR_QUAD_READ) },
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{ "mx25u4035", INFO(0xc22533, 0, 64 * 1024, 8)
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NO_SFDP_FLAGS(SECT_4K) },
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{ "mx25u8035", INFO(0xc22534, 0, 64 * 1024, 16)
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NO_SFDP_FLAGS(SECT_4K) },
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{ "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128)
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NO_SFDP_FLAGS(SECT_4K) },
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{ "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256)
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FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP)
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NO_SFDP_FLAGS(SECT_4K) },
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{ "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256) },
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{ "mx25r1635f", INFO(0xc22815, 0, 64 * 1024, 32)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
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SPI_NOR_QUAD_READ) },
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{ "mx25r3235f", INFO(0xc22816, 0, 64 * 1024, 64)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
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SPI_NOR_QUAD_READ) },
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{ "mx25u12835f", INFO(0xc22538, 0, 64 * 1024, 256)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
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SPI_NOR_QUAD_READ) },
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{ "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512)
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NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
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.fixups = &mx25l25635_fixups },
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{ "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512)
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NO_SFDP_FLAGS(SECT_4K)
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FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
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{ "mx25u51245g", INFO(0xc2253a, 0, 64 * 1024, 1024)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
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FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
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{ "mx25uw51245g", INFOB(0xc2813a, 0, 0, 0, 4)
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PARSE_SFDP
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FLAGS(SPI_NOR_RWW) },
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{ "mx25v8035f", INFO(0xc22314, 0, 64 * 1024, 16)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
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SPI_NOR_QUAD_READ) },
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{ "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512) },
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{ "mx66l51235f", INFO(0xc2201a, 0, 64 * 1024, 1024)
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NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
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FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
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{ "mx66u51235f", INFO(0xc2253a, 0, 64 * 1024, 1024)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
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FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
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{ "mx66l1g45g", INFO(0xc2201b, 0, 64 * 1024, 2048)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
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SPI_NOR_QUAD_READ) },
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{ "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048)
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NO_SFDP_FLAGS(SPI_NOR_QUAD_READ) },
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{ "mx66u2g45g", INFO(0xc2253c, 0, 64 * 1024, 4096)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
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FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
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{ "mx66lm2g45g", INFO(0xc2853c, 0, 64 * 1024, 4096)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_DTR_READ |
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SPI_NOR_OCTAL_DTR_PP)
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FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
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.fixups = &octaflash_fixups },
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{ "mx66lm1g45g", INFO(0xc2853b, 0, 32 * 1024, 4096)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_DTR_READ |
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SPI_NOR_OCTAL_DTR_PP)
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FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
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.fixups = &octaflash_fixups },
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{ "mx66lw1g45g", INFO(0xc2863b, 0, 32 * 1024, 4096)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_DTR_READ |
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SPI_NOR_OCTAL_DTR_PP)
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FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
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.fixups = &octaflash_fixups },
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{ "mx25lm51245g", INFO(0xc2853a, 0, 16 * 1024, 4096)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_DTR_READ |
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SPI_NOR_OCTAL_DTR_PP)
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FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
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.fixups = &octaflash_fixups },
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{ "mx25lw51245g", INFO(0xc2863a, 0, 16 * 1024, 4096)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_DTR_READ |
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SPI_NOR_OCTAL_DTR_PP)
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FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
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.fixups = &octaflash_fixups },
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{ "mx25lm25645g", INFO(0xc28539, 0, 8 * 1024, 4096)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_DTR_READ |
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SPI_NOR_OCTAL_DTR_PP)
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FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
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.fixups = &octaflash_fixups },
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{ "mx25lw25645g", INFO(0xc28639, 0, 8 * 1024, 4096)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_DTR_READ |
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SPI_NOR_OCTAL_DTR_PP)
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FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
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.fixups = &octaflash_fixups },
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{ "mx66um2g45g", INFO(0xc2803c, 0, 64 * 1024, 4096)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_DTR_READ |
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SPI_NOR_OCTAL_DTR_PP)
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FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
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.fixups = &octaflash_fixups },
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{ "mx66uw2g345g", INFO(0xc2843c, 0, 64 * 1024, 4096)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_DTR_READ |
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SPI_NOR_OCTAL_DTR_PP)
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FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
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.fixups = &octaflash_fixups },
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{ "mx66uw2g345gx0", INFO(0xc2943c, 0, 64 * 1024, 4096)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_DTR_READ |
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SPI_NOR_OCTAL_DTR_PP)
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FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
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.fixups = &octaflash_fixups },
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{ "mx66um1g45g", INFO(0xc2803b, 0, 32 * 1024, 4096)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_DTR_READ |
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SPI_NOR_OCTAL_DTR_PP)
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FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
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.fixups = &octaflash_fixups },
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{ "mx66um1g45g40", INFO(0xc2808b, 0, 32 * 1024, 4096)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_DTR_READ |
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SPI_NOR_OCTAL_DTR_PP)
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FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
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.fixups = &octaflash_fixups },
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{ "mx66uw1g45g", INFO(0xc2813b, 0, 32 * 1024, 4096)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_DTR_READ |
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SPI_NOR_OCTAL_DTR_PP)
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FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
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.fixups = &octaflash_fixups },
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{ "mx25um51245g", INFO(0xc2803a, 0, 16 * 1024, 4096)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_DTR_READ |
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SPI_NOR_OCTAL_DTR_PP)
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FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
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.fixups = &octaflash_fixups },
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{ "mx25uw51245g", INFO(0xc2813a, 0, 16 * 1024, 4096)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_DTR_READ |
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SPI_NOR_OCTAL_DTR_PP)
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FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
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.fixups = &octaflash_fixups },
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{ "mx25uw51345g", INFO(0xc2843a, 0, 16 * 1024, 4096)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_DTR_READ |
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SPI_NOR_OCTAL_DTR_PP)
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FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
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.fixups = &mx25uw51345g_fixups },
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{ "mx25um25645g", INFO(0xc28039, 0, 8 * 1024, 4096)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_DTR_READ |
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SPI_NOR_OCTAL_DTR_PP)
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FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
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.fixups = &octaflash_fixups },
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{ "mx25uw25645g", INFO(0xc28139, 0, 8 * 1024, 4096)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_DTR_READ |
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SPI_NOR_OCTAL_DTR_PP)
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FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
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.fixups = &octaflash_fixups },
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{ "mx25um25345g", INFO(0xc28339, 0, 8 * 1024, 4096)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_DTR_READ |
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SPI_NOR_OCTAL_DTR_PP)
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FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
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.fixups = &octaflash_fixups },
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{ "mx25uw25345g", INFO(0xc28439, 0, 8 * 1024, 4096)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_DTR_READ |
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SPI_NOR_OCTAL_DTR_PP)
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FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
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.fixups = &octaflash_fixups },
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{ "mx25uw12845g", INFO(0xc28138, 0, 4 * 1024, 4096)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_DTR_READ |
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SPI_NOR_OCTAL_DTR_PP)
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FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
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.fixups = &octaflash_fixups },
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{ "mx25uw12a45g", INFO(0xc28938, 0, 4 * 1024, 4096)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_DTR_READ |
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SPI_NOR_OCTAL_DTR_PP)
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FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
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.fixups = &octaflash_fixups },
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{ "mx25uw12345g", INFO(0xc28438, 0, 4 * 1024, 4096)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_DTR_READ |
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SPI_NOR_OCTAL_DTR_PP)
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FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
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.fixups = &octaflash_fixups },
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{ "mx25uw6445g", INFO(0xc28137, 0, 2 * 1024, 4096)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_DTR_READ |
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SPI_NOR_OCTAL_DTR_PP)
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FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
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.fixups = &octaflash_fixups },
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{ "mx25uw6345g", INFO(0xc28437, 0, 2 * 1024, 4096)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_DTR_READ |
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SPI_NOR_OCTAL_DTR_PP)
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FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
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.fixups = &octaflash_fixups },
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};
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static void macronix_nor_default_init(struct spi_nor *nor)
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{
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nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
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}
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static int macronix_nor_late_init(struct spi_nor *nor)
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{
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if (!nor->params->set_4byte_addr_mode)
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nor->params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode_en4b_ex4b;
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return 0;
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}
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static const struct spi_nor_fixups macronix_nor_fixups = {
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.default_init = macronix_nor_default_init,
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.late_init = macronix_nor_late_init,
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};
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const struct spi_nor_manufacturer spi_nor_macronix = {
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.name = "macronix",
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.parts = macronix_nor_parts,
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.nparts = ARRAY_SIZE(macronix_nor_parts),
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.fixups = ¯onix_nor_fixups,
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};
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