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afb217dbd5
the decoding is finished only when the frame done bit is set only check the frame done interrupt on 8mp, as 8mq support some legacy format, as for the legacy format, the frame done interrupt may be missed Signed-off-by: Ming Qian <ming.qian@nxp.com>
96 lines
3.5 KiB
C
96 lines
3.5 KiB
C
/*****************************************************************************
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* The GPL License (GPL)
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*
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* Copyright (c) 2015-2017, VeriSilicon Inc.
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* Copyright (c) 2011-2014, Google Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*****************************************************************************/
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#ifndef SOFTWARE_LINUX_DWL_DWL_DEFS_H_
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#define SOFTWARE_LINUX_DWL_DWL_DEFS_H_
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#define DWL_MPEG2_E 31 /* 1 bit */
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#define DWL_VC1_E 29 /* 2 bits */
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#define DWL_JPEG_E 28 /* 1 bit */
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#define DWL_MPEG4_E 26 /* 2 bits */
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#define DWL_H264_E 24 /* 2 bits */
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#define DWL_VP6_E 23 /* 1 bit */
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#define DWL_RV_E 26 /* 2 bits */
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#define DWL_VP8_E 23 /* 1 bit */
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#define DWL_VP7_E 24 /* 1 bit */
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#define DWL_WEBP_E 19 /* 1 bit */
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#define DWL_AVS_E 22 /* 1 bit */
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#if 0
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#define DWL_PP_E 16 /* 1 bit */
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#endif
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#define DWL_PP_E 31 /* 1 bit */
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#define DWL_HEVC_E 5 /* 2 bits */
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#define DWL_VP9_E 3 /* 2 bits */
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#define DWL_HEVC_ENA 0 /* 1 bits */
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#define DWL_VP9_ENA 1 /* 1 bits */
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#define DWL_RFC_E 2 /* 1 bits */
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#define DWL_DS_E 3 /* 1 bits */
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#define DWL_HEVC_VER 8 /* 4 bits */
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#define DWL_VP9_PROFILE 12 /* 3 bits */
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#define DWL_RING_E 16 /* 1 bits */
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#define HANTRODEC_IRQ_STAT_DEC 1
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#define HANTRODEC_IRQ_STAT_DEC_OFF (HANTRODEC_IRQ_STAT_DEC * 4)
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#define HANTRODECPP_SYNTH_CFG 60
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#define HANTRODECPP_SYNTH_CFG_OFF (HANTRODECPP_SYNTH_CFG * 4)
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#define HANTRODEC_SYNTH_CFG 50
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#define HANTRODEC_SYNTH_CFG_OFF (HANTRODEC_SYNTH_CFG * 4)
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#define HANTRODEC_SYNTH_CFG_2 54
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#define HANTRODEC_SYNTH_CFG_2_OFF (HANTRODEC_SYNTH_CFG_2 * 4)
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#define HANTRODEC_SYNTH_CFG_3 56
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#define HANTRODEC_SYNTH_CFG_3_OFF (HANTRODEC_SYNTH_CFG_3 * 4)
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#define HANTRODEC_CFG_STAT 23
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#define HANTRODEC_CFG_STAT_OFF (HANTRODEC_CFG_STAT * 4)
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#define HANTRODEC_DEC_E 0x01
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#define HANTRODEC_PP_E 0x01
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#define HANTRODEC_DEC_ABORT 0x20
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#define HANTRODEC_DEC_IRQ_DISABLE 0x10
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#define HANTRODEC_DEC_IRQ 0x100
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#define HANTRODEC_DEC_DONE 0x1000
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/* Legacy from G1 */
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#define HANTRO_IRQ_STAT_DEC 1
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#define HANTRO_IRQ_STAT_DEC_OFF (HANTRO_IRQ_STAT_DEC * 4)
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#define HANTRO_IRQ_STAT_PP 60
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#define HANTRO_IRQ_STAT_PP_OFF (HANTRO_IRQ_STAT_PP * 4)
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#define HANTROPP_SYNTH_CFG 100
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#define HANTROPP_SYNTH_CFG_OFF (HANTROPP_SYNTH_CFG * 4)
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#define HANTRODEC_SYNTH_CFG 50
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#define HANTRODEC_SYNTH_CFG_OFF (HANTRODEC_SYNTH_CFG * 4)
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#define HANTRODEC_SYNTH_CFG_2 54
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#define HANTRODEC_SYNTH_CFG_2_OFF (HANTRODEC_SYNTH_CFG_2 * 4)
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#define HANTRO_DEC_E 0x01
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#define HANTRO_PP_E 0x01
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#define HANTRO_DEC_ABORT 0x20
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#define HANTRO_DEC_IRQ_DISABLE 0x10
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#define HANTRO_PP_IRQ_DISABLE 0x10
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#define HANTRO_DEC_IRQ 0x100
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#define HANTRO_PP_IRQ 0x100
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#endif /* SOFTWARE_LINUX_DWL_DWL_DEFS_H_ */
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