mirror of
https://github.com/nxp-imx/linux-imx.git
synced 2025-09-03 02:16:09 +02:00
6f33ed53f2
When enable initcall_debug together with higher debug level below.
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=9
CONFIG_CONSOLE_LOGLEVEL_QUIET=9
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
The initialization of i.MX8MP PCIe PHY might be timeout failed randomly.
To fix this issue, adjust the sequence of the resets refer to the power
up sequence listed below.
i.MX8MP PCIe PHY power up sequence:
/---------------------------------------------
1.8v supply ---------/
/---------------------------------------------------
0.8v supply ---/
---\ /--------------------------------------------------
X REFCLK Valid
Reference Clock ---/ \--------------------------------------------------
-------------------------------------------
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i_init_restn --------------
------------------------------------
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i_cmn_rstn ---------------------
-------------------------------
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o_pll_lock_done --------------------------
Logs:
imx6q-pcie 33800000.pcie: host bridge /soc@0/pcie@33800000 ranges:
imx6q-pcie 33800000.pcie: IO 0x001ff80000..0x001ff8ffff -> 0x0000000000
imx6q-pcie 33800000.pcie: MEM 0x0018000000..0x001fefffff -> 0x0018000000
probe of clk_imx8mp_audiomix.reset.0 returned 0 after 1052 usecs
probe of 30e20000.clock-controller returned 0 after 32971 usecs
phy phy-32f00000.pcie-phy.4: phy poweron failed --> -110
probe of 30e10000.dma-controller returned 0 after 10235 usecs
imx6q-pcie 33800000.pcie: waiting for PHY ready timeout!
dwhdmi-imx 32fd8000.hdmi: Detected HDMI TX controller v2.13a with HDCP (samsung_dw_hdmi_phy2)
imx6q-pcie 33800000.pcie: probe with driver imx6q-pcie failed with error -110
Fixes: dce9edff16 ("phy: freescale: imx8m-pcie: Add i.MX8MP PCIe PHY support")
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Frank Li <frank.li@nxp.com>
377 lines
12 KiB
C
377 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2021 NXP
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/mfd/syscon.h>
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#include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include <dt-bindings/phy/phy-imx8-pcie.h>
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#define IMX8MM_PCIE_PHY_CMN_REG061 0x184
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#define ANA_PLL_CLK_OUT_TO_EXT_IO_EN BIT(0)
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#define IMX8MM_PCIE_PHY_CMN_REG062 0x188
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#define ANA_PLL_CLK_OUT_TO_EXT_IO_SEL BIT(3)
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#define IMX8MM_PCIE_PHY_CMN_REG063 0x18C
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#define AUX_PLL_REFCLK_SEL_SYS_PLL GENMASK(7, 6)
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#define IMX8MM_PCIE_PHY_CMN_REG064 0x190
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#define ANA_AUX_RX_TX_SEL_TX BIT(7)
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#define ANA_AUX_RX_TERM_GND_EN BIT(3)
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#define ANA_AUX_TX_TERM BIT(2)
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#define IMX8MM_PCIE_PHY_CMN_REG065 0x194
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#define ANA_AUX_RX_TERM (BIT(7) | BIT(4))
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#define ANA_AUX_TX_LVL GENMASK(3, 0)
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#define IMX8MM_PCIE_PHY_CMN_REG075 0x1D4
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#define ANA_PLL_DONE 0x3
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#define PCIE_PHY_TRSV_REG5 0x414
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#define PCIE_PHY_TRSV_REG6 0x418
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#define IMX8MM_GPR_PCIE_REF_CLK_SEL GENMASK(25, 24)
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#define IMX8MM_GPR_PCIE_REF_CLK_PLL FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x3)
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#define IMX8MM_GPR_PCIE_REF_CLK_EXT FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x2)
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#define IMX8MM_GPR_PCIE_AUX_EN BIT(19)
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#define IMX8MM_GPR_PCIE_CMN_RST BIT(18)
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#define IMX8MM_GPR_PCIE_POWER_OFF BIT(17)
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#define IMX8MM_GPR_PCIE_SSC_EN BIT(16)
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#define IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE BIT(9)
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#define IMX8MP_PCIE_PHY_TRSV_REG001 0x404
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#define LN0_OVRD_TX_DRV_LVL_G1 0x3F
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#define IMX8MP_PCIE_PHY_TRSV_REG002 0x408
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#define LN0_OVRD_TX_DRV_LVL_G2 0x1F
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#define IMX8MP_PCIE_PHY_TRSV_REG003 0x40C
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#define LN0_OVRD_TX_DRV_LVL_G3 0x1F
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#define IMX8MP_PCIE_PHY_TRSV_REG005 0x414
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#define LN0_OVRD_TX_DRV_PST_LVL_G1 0x2B
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#define IMX8MP_PCIE_PHY_TRSV_REG006 0x418
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#define LN0_OVRD_TX_DRV_PST_LVL_G2 0xB
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#define IMX8MP_PCIE_PHY_TRSV_REG007 0x41C
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#define LN0_OVRD_TX_DRV_PST_LVL_G3 0xB
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#define IMX8MP_PCIE_PHY_TRSV_REG009 0x424
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#define LN0_OVRD_TX_DRV_PRE_LVL_G1 0x15
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#define IMX8MP_PCIE_PHY_TRSV_REG00A 0x428
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#define LN0_OVRD_TX_DRV_PRE_LVL_G23 0x55
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#define IMX8MP_PCIE_PHY_TRSV_REG059 0x4EC
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#define LN0_OVRD_RX_CTLE_RS1_G1 0x13
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#define IMX8MP_PCIE_PHY_TRSV_REG060 0x4F0
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#define LN0_OVRD_RX_CTLE_RS1_G2_G3 0x25
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#define IMX8MP_PCIE_PHY_TRSV_REG069 0x514
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#define LN0_ANA_RX_CTLE_IBLEED 0x7
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#define IMX8MP_PCIE_PHY_TRSV_REG107 0x5AC
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#define LN0_OVRD_RX_RTERM_VCM_EN 0xB8
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#define IMX8MP_PCIE_PHY_TRSV_REG109 0x5B4
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#define LN0_ANA_OVRD_RX_SQHS_DIFN_OC 0xD4
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#define IMX8MP_PCIE_PHY_TRSV_REG110 0x5B8
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#define LN0_ANA_OVRD_RX_SQHS_DIFP_OC 0x6A
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#define IMX8MP_PCIE_PHY_TRSV_REG158 0x678
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#define LN0_RX_CDR_FBB_FINE_G1_G2 0x55
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#define IMX8MP_PCIE_PHY_TRSV_REG159 0x67C
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#define LN0_RX_CDR_FBB_FINE_G3_G4 0x53
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#define IMX8MP_PCIE_PHY_TRSV_REG206 0x738
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#define LN0_TG_RX_SIGVAL_LBF_DELAY 0x4
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static int imx8_pcie_phy_tuned;
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enum imx8_pcie_phy_type {
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IMX8MM,
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IMX8MP,
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};
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struct imx8_pcie_phy_drvdata {
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const char *gpr;
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enum imx8_pcie_phy_type variant;
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};
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struct imx8_pcie_phy {
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void __iomem *base;
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struct clk *clk;
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struct phy *phy;
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struct regmap *iomuxc_gpr;
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struct reset_control *perst;
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struct reset_control *reset;
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u32 refclk_pad_mode;
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u32 tx_deemph_gen1;
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u32 tx_deemph_gen2;
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bool clkreq_unused;
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const struct imx8_pcie_phy_drvdata *drvdata;
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};
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static int imx8_pcie_phy_power_on(struct phy *phy)
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{
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int ret;
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u32 val, pad_mode;
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struct imx8_pcie_phy *imx8_phy = phy_get_drvdata(phy);
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pad_mode = imx8_phy->refclk_pad_mode;
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switch (imx8_phy->drvdata->variant) {
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case IMX8MM:
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reset_control_assert(imx8_phy->reset);
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/* Tune PHY de-emphasis setting to pass PCIe compliance. */
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if (imx8_phy->tx_deemph_gen1)
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writel(imx8_phy->tx_deemph_gen1,
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imx8_phy->base + PCIE_PHY_TRSV_REG5);
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if (imx8_phy->tx_deemph_gen2)
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writel(imx8_phy->tx_deemph_gen2,
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imx8_phy->base + PCIE_PHY_TRSV_REG6);
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break;
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case IMX8MP: /* Do nothing. */
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break;
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}
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if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ||
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pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) {
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/* Configure the pad as input */
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val = readl(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061);
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writel(val & ~ANA_PLL_CLK_OUT_TO_EXT_IO_EN,
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imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061);
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} else {
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/* Configure the PHY to output the refclock via pad */
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writel(ANA_PLL_CLK_OUT_TO_EXT_IO_EN,
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imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061);
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}
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if (pad_mode == IMX8_PCIE_REFCLK_PAD_OUTPUT ||
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pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) {
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/* Source clock from SoC internal PLL */
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writel(ANA_PLL_CLK_OUT_TO_EXT_IO_SEL,
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imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG062);
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if (imx8_phy->drvdata->variant != IMX8MM) {
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writel(AUX_PLL_REFCLK_SEL_SYS_PLL,
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imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG063);
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}
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val = ANA_AUX_RX_TX_SEL_TX | ANA_AUX_TX_TERM;
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writel(val | ANA_AUX_RX_TERM_GND_EN,
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imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG064);
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writel(ANA_AUX_RX_TERM | ANA_AUX_TX_LVL,
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imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG065);
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}
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/* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */
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regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
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IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
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imx8_phy->clkreq_unused ?
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0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
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regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
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IMX8MM_GPR_PCIE_AUX_EN,
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IMX8MM_GPR_PCIE_AUX_EN);
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regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
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IMX8MM_GPR_PCIE_POWER_OFF, 0);
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regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
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IMX8MM_GPR_PCIE_SSC_EN, 0);
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regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
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IMX8MM_GPR_PCIE_REF_CLK_SEL,
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pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?
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IMX8MM_GPR_PCIE_REF_CLK_EXT :
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IMX8MM_GPR_PCIE_REF_CLK_PLL);
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usleep_range(100, 200);
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/*
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* Fine tune the parameters of the PHY, let PCIe link up to Gen3
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* between two i.MX8MP EVK boards in the EP/RC validation system.
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*/
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if (imx8_pcie_phy_tuned && (imx8_phy->drvdata->variant == IMX8MP)) {
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writel(LN0_OVRD_TX_DRV_LVL_G1,
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imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG001);
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writel(LN0_OVRD_TX_DRV_LVL_G2,
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imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG002);
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writel(LN0_OVRD_TX_DRV_LVL_G3,
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imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG003);
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writel(LN0_OVRD_TX_DRV_PST_LVL_G1,
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imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG005);
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writel(LN0_OVRD_TX_DRV_PST_LVL_G2,
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imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG006);
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writel(LN0_OVRD_TX_DRV_PST_LVL_G3,
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imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG007);
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writel(LN0_OVRD_TX_DRV_PRE_LVL_G1,
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imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG009);
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writel(LN0_OVRD_TX_DRV_PRE_LVL_G23,
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imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG00A);
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writel(LN0_OVRD_RX_CTLE_RS1_G1,
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imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG059);
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writel(LN0_OVRD_RX_CTLE_RS1_G2_G3,
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imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG060);
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writel(LN0_ANA_RX_CTLE_IBLEED,
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imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG069);
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writel(LN0_OVRD_RX_RTERM_VCM_EN,
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imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG107);
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writel(LN0_ANA_OVRD_RX_SQHS_DIFN_OC,
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imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG109);
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writel(LN0_ANA_OVRD_RX_SQHS_DIFP_OC,
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imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG110);
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writel(LN0_RX_CDR_FBB_FINE_G1_G2,
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imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG158);
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writel(LN0_RX_CDR_FBB_FINE_G3_G4,
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imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG159);
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writel(LN0_TG_RX_SIGVAL_LBF_DELAY,
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imx8_phy->base + IMX8MP_PCIE_PHY_TRSV_REG206);
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}
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switch (imx8_phy->drvdata->variant) {
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case IMX8MP:
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reset_control_deassert(imx8_phy->perst);
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fallthrough;
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case IMX8MM:
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reset_control_deassert(imx8_phy->reset);
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usleep_range(200, 500);
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break;
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}
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/* Do the PHY common block reset */
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regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
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IMX8MM_GPR_PCIE_CMN_RST,
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IMX8MM_GPR_PCIE_CMN_RST);
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/* Polling to check the phy is ready or not. */
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ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG075,
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val, val == ANA_PLL_DONE, 10, 20000);
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return ret;
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}
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static int imx8_pcie_phy_init(struct phy *phy)
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{
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struct imx8_pcie_phy *imx8_phy = phy_get_drvdata(phy);
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return clk_prepare_enable(imx8_phy->clk);
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}
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static int imx8_pcie_phy_exit(struct phy *phy)
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{
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struct imx8_pcie_phy *imx8_phy = phy_get_drvdata(phy);
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clk_disable_unprepare(imx8_phy->clk);
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return 0;
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}
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static const struct phy_ops imx8_pcie_phy_ops = {
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.init = imx8_pcie_phy_init,
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.exit = imx8_pcie_phy_exit,
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.power_on = imx8_pcie_phy_power_on,
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.owner = THIS_MODULE,
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};
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static const struct imx8_pcie_phy_drvdata imx8mm_drvdata = {
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.gpr = "fsl,imx8mm-iomuxc-gpr",
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.variant = IMX8MM,
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};
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static const struct imx8_pcie_phy_drvdata imx8mp_drvdata = {
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.gpr = "fsl,imx8mp-iomuxc-gpr",
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.variant = IMX8MP,
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};
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static const struct of_device_id imx8_pcie_phy_of_match[] = {
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{.compatible = "fsl,imx8mm-pcie-phy", .data = &imx8mm_drvdata, },
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{.compatible = "fsl,imx8mp-pcie-phy", .data = &imx8mp_drvdata, },
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{ },
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};
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MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
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static int __init imx8_pcie_phy_fine_tune(char *str)
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{
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if (!strcmp(str, "yes")) {
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pr_info("i.MX PCIe PHY is fine tuned in EP/RC SYS.\n");
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imx8_pcie_phy_tuned = 1;
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}
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return 1;
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}
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__setup("pcie_phy_tuned=", imx8_pcie_phy_fine_tune);
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static int imx8_pcie_phy_probe(struct platform_device *pdev)
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{
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struct phy_provider *phy_provider;
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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struct imx8_pcie_phy *imx8_phy;
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imx8_phy = devm_kzalloc(dev, sizeof(*imx8_phy), GFP_KERNEL);
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if (!imx8_phy)
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return -ENOMEM;
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imx8_phy->drvdata = of_device_get_match_data(dev);
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/* get PHY refclk pad mode */
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of_property_read_u32(np, "fsl,refclk-pad-mode",
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&imx8_phy->refclk_pad_mode);
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if (of_property_read_u32(np, "fsl,tx-deemph-gen1",
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&imx8_phy->tx_deemph_gen1))
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imx8_phy->tx_deemph_gen1 = 0;
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if (of_property_read_u32(np, "fsl,tx-deemph-gen2",
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&imx8_phy->tx_deemph_gen2))
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imx8_phy->tx_deemph_gen2 = 0;
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if (of_property_read_bool(np, "fsl,clkreq-unsupported"))
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imx8_phy->clkreq_unused = true;
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else
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imx8_phy->clkreq_unused = false;
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imx8_phy->clk = devm_clk_get(dev, "ref");
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if (IS_ERR(imx8_phy->clk)) {
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dev_err(dev, "failed to get imx pcie phy clock\n");
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return PTR_ERR(imx8_phy->clk);
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}
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/* Grab GPR config register range */
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imx8_phy->iomuxc_gpr =
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syscon_regmap_lookup_by_compatible(imx8_phy->drvdata->gpr);
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if (IS_ERR(imx8_phy->iomuxc_gpr)) {
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dev_err(dev, "unable to find iomuxc registers\n");
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return PTR_ERR(imx8_phy->iomuxc_gpr);
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}
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imx8_phy->reset = devm_reset_control_get_exclusive(dev, "pciephy");
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if (IS_ERR(imx8_phy->reset)) {
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dev_err(dev, "Failed to get PCIEPHY reset control\n");
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return PTR_ERR(imx8_phy->reset);
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}
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if (imx8_phy->drvdata->variant == IMX8MP) {
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imx8_phy->perst =
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devm_reset_control_get_exclusive(dev, "perst");
|
|
if (IS_ERR(imx8_phy->perst))
|
|
return dev_err_probe(dev, PTR_ERR(imx8_phy->perst),
|
|
"Failed to get PCIE PHY PERST control\n");
|
|
}
|
|
|
|
imx8_phy->base = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(imx8_phy->base))
|
|
return PTR_ERR(imx8_phy->base);
|
|
|
|
imx8_phy->phy = devm_phy_create(dev, NULL, &imx8_pcie_phy_ops);
|
|
if (IS_ERR(imx8_phy->phy))
|
|
return PTR_ERR(imx8_phy->phy);
|
|
|
|
phy_set_drvdata(imx8_phy->phy, imx8_phy);
|
|
|
|
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
|
|
|
|
return PTR_ERR_OR_ZERO(phy_provider);
|
|
}
|
|
|
|
static struct platform_driver imx8_pcie_phy_driver = {
|
|
.probe = imx8_pcie_phy_probe,
|
|
.driver = {
|
|
.name = "imx8-pcie-phy",
|
|
.of_match_table = imx8_pcie_phy_of_match,
|
|
}
|
|
};
|
|
module_platform_driver(imx8_pcie_phy_driver);
|
|
|
|
MODULE_DESCRIPTION("FSL IMX8 PCIE PHY driver");
|
|
MODULE_LICENSE("GPL v2");
|