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cde2aed878
Provide an implementation for the new phy_configure_opts_xgkr API for the 28G Lynx SerDes from NXP LX2160A. The core logic of the algorithm is also usable with the 10G Lynx SerDes for earlier QorIQ/Layerscape SoCs, but a driver does not exist for that yet. Nonetheless, it is in progress, so structure the link training algorithm as library code, shareable by the two SerDes drivers when the time comes. Loosely based on previous work by Florinel Iordache. Co-developed-by: Florinel Iordache <florinel.iordache@nxp.com> Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
49 lines
1.1 KiB
C
49 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright 2023 NXP
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*/
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#ifndef _FSL_LYNX_XGKR_ALGORITHM_H
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#define _FSL_LYNX_XGKR_ALGORITHM_H
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#include <linux/phy/phy.h>
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#include <linux/types.h>
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struct lynx_xgkr_algorithm;
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struct phy;
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struct lynx_xgkr_tx_eq {
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u32 ratio_preq;
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u32 ratio_post1q;
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u32 adapt_eq;
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u32 amp_reduction;
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};
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enum lynx_bin_type {
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BIN_1,
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BIN_2,
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BIN_3,
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BIN_4,
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BIN_OFFSET,
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BIN_BLW,
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BIN_DATA_AVG,
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BIN_M1,
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BIN_LONG,
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};
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struct lynx_xgkr_algorithm_ops {
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void (*read_tx_eq)(struct phy *phy, struct lynx_xgkr_tx_eq *tx_eq);
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void (*tune_tx_eq)(struct phy *phy, const struct lynx_xgkr_tx_eq *tx_eq);
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int (*snapshot_rx_eq_gains)(struct phy *phy, u8 *gaink2, u8 *gaink3,
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u8 *eq_offset);
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int (*snapshot_rx_eq_bin)(struct phy *phy, enum lynx_bin_type bin_type,
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s16 *snapshot);
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};
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struct lynx_xgkr_algorithm *
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lynx_xgkr_algorithm_create(struct phy *phy,
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const struct lynx_xgkr_algorithm_ops *ops);
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void lynx_xgkr_algorithm_destroy(struct lynx_xgkr_algorithm *algorithm);
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int lynx_xgkr_algorithm_configure(struct lynx_xgkr_algorithm *algorithm,
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struct phy_configure_opts_ethernet *opts);
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#endif
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