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https://github.com/nxp-imx/linux-imx.git
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ec1db33ebe
In the last stage of deep sleep, software will trigger a Finite State Machine (FSM) to control the hardware procedure, such a board isolation, killing PLLs, removing power, and so on. When the system is waked up by an interrupt, the FSM controls the hardware to complete the early resume procedure. This patch configure the EPU FSM preparing for deep sleep. Signed-off-by: Hongbo Zhang <hongbo.zhang@freescale.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
280 lines
9.8 KiB
C
280 lines
9.8 KiB
C
/*
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* deep sleep FSM (finite-state machine) configuration
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*
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* Copyright 2018 NXP
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*
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* Author: Hongbo Zhang <hongbo.zhang@freescale.com>
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* Chenhui Zhao <chenhui.zhao@freescale.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the above-listed copyright holders nor the
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* names of any contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/types.h>
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#include "sleep_fsm.h"
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/*
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* These values are from chip's reference manual. For example,
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* the values for T1040 can be found in "8.4.3.8 Programming
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* supporting deep sleep mode" of Chapter 8 "Run Control and
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* Power Management (RCPM)".
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* The default value can be applied to T104x, LS1021.
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*/
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struct fsm_reg_vals epu_default_val[] = {
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/* EPGCR (Event Processor Global Control Register) */
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{EPGCR, 0},
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/* EPECR (Event Processor Event Control Registers) */
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{EPECR0 + EPECR_STRIDE * 0, 0},
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{EPECR0 + EPECR_STRIDE * 1, 0},
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{EPECR0 + EPECR_STRIDE * 2, 0xF0004004},
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{EPECR0 + EPECR_STRIDE * 3, 0x80000084},
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{EPECR0 + EPECR_STRIDE * 4, 0x20000084},
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{EPECR0 + EPECR_STRIDE * 5, 0x08000004},
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{EPECR0 + EPECR_STRIDE * 6, 0x80000084},
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{EPECR0 + EPECR_STRIDE * 7, 0x80000084},
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{EPECR0 + EPECR_STRIDE * 8, 0x60000084},
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{EPECR0 + EPECR_STRIDE * 9, 0x08000084},
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{EPECR0 + EPECR_STRIDE * 10, 0x42000084},
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{EPECR0 + EPECR_STRIDE * 11, 0x90000084},
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{EPECR0 + EPECR_STRIDE * 12, 0x80000084},
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{EPECR0 + EPECR_STRIDE * 13, 0x08000084},
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{EPECR0 + EPECR_STRIDE * 14, 0x02000084},
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{EPECR0 + EPECR_STRIDE * 15, 0x00000004},
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/*
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* EPEVTCR (Event Processor EVT Pin Control Registers)
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* SCU8 triger EVT2, and SCU11 triger EVT9
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*/
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{EPEVTCR0 + EPEVTCR_STRIDE * 0, 0},
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{EPEVTCR0 + EPEVTCR_STRIDE * 1, 0},
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{EPEVTCR0 + EPEVTCR_STRIDE * 2, 0x80000001},
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{EPEVTCR0 + EPEVTCR_STRIDE * 3, 0},
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{EPEVTCR0 + EPEVTCR_STRIDE * 4, 0},
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{EPEVTCR0 + EPEVTCR_STRIDE * 5, 0},
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{EPEVTCR0 + EPEVTCR_STRIDE * 6, 0},
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{EPEVTCR0 + EPEVTCR_STRIDE * 7, 0},
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{EPEVTCR0 + EPEVTCR_STRIDE * 8, 0},
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{EPEVTCR0 + EPEVTCR_STRIDE * 9, 0xB0000001},
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/* EPCMPR (Event Processor Counter Compare Registers) */
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{EPCMPR0 + EPCMPR_STRIDE * 0, 0},
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{EPCMPR0 + EPCMPR_STRIDE * 1, 0},
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{EPCMPR0 + EPCMPR_STRIDE * 2, 0x000000FF},
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{EPCMPR0 + EPCMPR_STRIDE * 3, 0},
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{EPCMPR0 + EPCMPR_STRIDE * 4, 0x000000FF},
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{EPCMPR0 + EPCMPR_STRIDE * 5, 0x00000020},
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{EPCMPR0 + EPCMPR_STRIDE * 6, 0},
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{EPCMPR0 + EPCMPR_STRIDE * 7, 0},
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{EPCMPR0 + EPCMPR_STRIDE * 8, 0x000000FF},
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{EPCMPR0 + EPCMPR_STRIDE * 9, 0x000000FF},
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{EPCMPR0 + EPCMPR_STRIDE * 10, 0x000000FF},
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{EPCMPR0 + EPCMPR_STRIDE * 11, 0x000000FF},
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{EPCMPR0 + EPCMPR_STRIDE * 12, 0x000000FF},
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{EPCMPR0 + EPCMPR_STRIDE * 13, 0},
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{EPCMPR0 + EPCMPR_STRIDE * 14, 0x000000FF},
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{EPCMPR0 + EPCMPR_STRIDE * 15, 0x000000FF},
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/* EPCCR (Event Processor Counter Control Registers) */
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{EPCCR0 + EPCCR_STRIDE * 0, 0},
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{EPCCR0 + EPCCR_STRIDE * 1, 0},
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{EPCCR0 + EPCCR_STRIDE * 2, 0x92840000},
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{EPCCR0 + EPCCR_STRIDE * 3, 0},
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{EPCCR0 + EPCCR_STRIDE * 4, 0x92840000},
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{EPCCR0 + EPCCR_STRIDE * 5, 0x92840000},
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{EPCCR0 + EPCCR_STRIDE * 6, 0},
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{EPCCR0 + EPCCR_STRIDE * 7, 0},
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{EPCCR0 + EPCCR_STRIDE * 8, 0x92840000},
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{EPCCR0 + EPCCR_STRIDE * 9, 0x92840000},
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{EPCCR0 + EPCCR_STRIDE * 10, 0x92840000},
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{EPCCR0 + EPCCR_STRIDE * 11, 0x92840000},
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{EPCCR0 + EPCCR_STRIDE * 12, 0x92840000},
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{EPCCR0 + EPCCR_STRIDE * 13, 0},
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{EPCCR0 + EPCCR_STRIDE * 14, 0x92840000},
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{EPCCR0 + EPCCR_STRIDE * 15, 0x92840000},
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/* EPSMCR (Event Processor SCU Mux Control Registers) */
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{EPSMCR0 + EPSMCR_STRIDE * 0, 0},
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{EPSMCR0 + EPSMCR_STRIDE * 1, 0},
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{EPSMCR0 + EPSMCR_STRIDE * 2, 0x6C700000},
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{EPSMCR0 + EPSMCR_STRIDE * 3, 0x2F000000},
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{EPSMCR0 + EPSMCR_STRIDE * 4, 0x002F0000},
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{EPSMCR0 + EPSMCR_STRIDE * 5, 0x00002E00},
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{EPSMCR0 + EPSMCR_STRIDE * 6, 0x7C000000},
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{EPSMCR0 + EPSMCR_STRIDE * 7, 0x30000000},
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{EPSMCR0 + EPSMCR_STRIDE * 8, 0x64300000},
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{EPSMCR0 + EPSMCR_STRIDE * 9, 0x00003000},
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{EPSMCR0 + EPSMCR_STRIDE * 10, 0x65000030},
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{EPSMCR0 + EPSMCR_STRIDE * 11, 0x31740000},
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{EPSMCR0 + EPSMCR_STRIDE * 12, 0x7F000000},
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{EPSMCR0 + EPSMCR_STRIDE * 13, 0x00003100},
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{EPSMCR0 + EPSMCR_STRIDE * 14, 0x00000031},
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{EPSMCR0 + EPSMCR_STRIDE * 15, 0x76000000},
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/* EPACR (Event Processor Action Control Registers) */
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{EPACR0 + EPACR_STRIDE * 0, 0},
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{EPACR0 + EPACR_STRIDE * 1, 0},
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{EPACR0 + EPACR_STRIDE * 2, 0},
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{EPACR0 + EPACR_STRIDE * 3, 0x00000080},
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{EPACR0 + EPACR_STRIDE * 4, 0},
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{EPACR0 + EPACR_STRIDE * 5, 0x00000040},
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{EPACR0 + EPACR_STRIDE * 6, 0},
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{EPACR0 + EPACR_STRIDE * 7, 0},
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{EPACR0 + EPACR_STRIDE * 8, 0},
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{EPACR0 + EPACR_STRIDE * 9, 0x0000001C},
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{EPACR0 + EPACR_STRIDE * 10, 0x00000020},
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{EPACR0 + EPACR_STRIDE * 11, 0},
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{EPACR0 + EPACR_STRIDE * 12, 0x00000003},
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{EPACR0 + EPACR_STRIDE * 13, 0x06000000},
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{EPACR0 + EPACR_STRIDE * 14, 0x04000000},
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{EPACR0 + EPACR_STRIDE * 15, 0x02000000},
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/* EPIMCR (Event Processor Input Mux Control Registers) */
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{EPIMCR0 + EPIMCR_STRIDE * 0, 0},
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{EPIMCR0 + EPIMCR_STRIDE * 1, 0},
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{EPIMCR0 + EPIMCR_STRIDE * 2, 0},
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{EPIMCR0 + EPIMCR_STRIDE * 3, 0},
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{EPIMCR0 + EPIMCR_STRIDE * 4, 0x44000000},
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{EPIMCR0 + EPIMCR_STRIDE * 5, 0x40000000},
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{EPIMCR0 + EPIMCR_STRIDE * 6, 0},
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{EPIMCR0 + EPIMCR_STRIDE * 7, 0},
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{EPIMCR0 + EPIMCR_STRIDE * 8, 0},
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{EPIMCR0 + EPIMCR_STRIDE * 9, 0},
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{EPIMCR0 + EPIMCR_STRIDE * 10, 0},
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{EPIMCR0 + EPIMCR_STRIDE * 11, 0},
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{EPIMCR0 + EPIMCR_STRIDE * 12, 0x44000000},
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{EPIMCR0 + EPIMCR_STRIDE * 13, 0},
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{EPIMCR0 + EPIMCR_STRIDE * 14, 0},
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{EPIMCR0 + EPIMCR_STRIDE * 15, 0},
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{EPIMCR0 + EPIMCR_STRIDE * 16, 0x6A000000},
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{EPIMCR0 + EPIMCR_STRIDE * 17, 0},
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{EPIMCR0 + EPIMCR_STRIDE * 18, 0},
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{EPIMCR0 + EPIMCR_STRIDE * 19, 0},
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{EPIMCR0 + EPIMCR_STRIDE * 20, 0x48000000},
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{EPIMCR0 + EPIMCR_STRIDE * 21, 0},
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{EPIMCR0 + EPIMCR_STRIDE * 22, 0x6C000000},
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{EPIMCR0 + EPIMCR_STRIDE * 23, 0},
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{EPIMCR0 + EPIMCR_STRIDE * 24, 0},
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{EPIMCR0 + EPIMCR_STRIDE * 25, 0},
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{EPIMCR0 + EPIMCR_STRIDE * 26, 0},
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{EPIMCR0 + EPIMCR_STRIDE * 27, 0},
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{EPIMCR0 + EPIMCR_STRIDE * 28, 0x76000000},
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{EPIMCR0 + EPIMCR_STRIDE * 29, 0},
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{EPIMCR0 + EPIMCR_STRIDE * 30, 0},
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{EPIMCR0 + EPIMCR_STRIDE * 31, 0x76000000},
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/* EPXTRIGCR (Event Processor Crosstrigger Control Register) */
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{EPXTRIGCR, 0x0000FFDF},
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/* end */
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{FSM_END_FLAG, 0},
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};
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struct fsm_reg_vals npc_default_val[] = {
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/* NPC triggered Memory-Mapped Access Registers */
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{NCR, 0x80000000},
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{MCCR1, 0},
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{MCSR1, 0},
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{MMAR1LO, 0},
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{MMAR1HI, 0},
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{MMDR1, 0},
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{MCSR2, 0},
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{MMAR2LO, 0},
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{MMAR2HI, 0},
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{MMDR2, 0},
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{MCSR3, 0x80000000},
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{MMAR3LO, 0x000E2130},
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{MMAR3HI, 0x00030000},
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{MMDR3, 0x00020000},
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/* end */
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{FSM_END_FLAG, 0},
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};
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/**
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* fsl_fsm_setup - Configure EPU's FSM registers
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* @base: the base address of registers
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* @val: Pointer to address-value pairs for FSM registers
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*/
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void fsl_fsm_setup(void __iomem *base, struct fsm_reg_vals *val)
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{
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struct fsm_reg_vals *data = val;
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WARN_ON(!base || !data);
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while (data->offset != FSM_END_FLAG) {
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iowrite32be(data->value, base + data->offset);
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data++;
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}
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}
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void fsl_epu_setup_default(void __iomem *epu_base)
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{
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fsl_fsm_setup(epu_base, epu_default_val);
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}
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void fsl_npc_setup_default(void __iomem *npc_base)
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{
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fsl_fsm_setup(npc_base, npc_default_val);
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}
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void fsl_epu_clean_default(void __iomem *epu_base)
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{
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u32 offset;
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/* follow the exact sequence to clear the registers */
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/* Clear EPACRn */
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for (offset = EPACR0; offset <= EPACR15; offset += EPACR_STRIDE)
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iowrite32be(0, epu_base + offset);
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/* Clear EPEVTCRn */
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for (offset = EPEVTCR0; offset <= EPEVTCR9; offset += EPEVTCR_STRIDE)
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iowrite32be(0, epu_base + offset);
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/* Clear EPGCR */
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iowrite32be(0, epu_base + EPGCR);
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/* Clear EPSMCRn */
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for (offset = EPSMCR0; offset <= EPSMCR15; offset += EPSMCR_STRIDE)
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iowrite32be(0, epu_base + offset);
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/* Clear EPCCRn */
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for (offset = EPCCR0; offset <= EPCCR31; offset += EPCCR_STRIDE)
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iowrite32be(0, epu_base + offset);
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/* Clear EPCMPRn */
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for (offset = EPCMPR0; offset <= EPCMPR31; offset += EPCMPR_STRIDE)
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iowrite32be(0, epu_base + offset);
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/* Clear EPCTRn */
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for (offset = EPCTR0; offset <= EPCTR31; offset += EPCTR_STRIDE)
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iowrite32be(0, epu_base + offset);
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/* Clear EPIMCRn */
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for (offset = EPIMCR0; offset <= EPIMCR31; offset += EPIMCR_STRIDE)
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iowrite32be(0, epu_base + offset);
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/* Clear EPXTRIGCRn */
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iowrite32be(0, epu_base + EPXTRIGCR);
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/* Clear EPECRn */
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for (offset = EPECR0; offset <= EPECR15; offset += EPECR_STRIDE)
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iowrite32be(0, epu_base + offset);
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}
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