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818988e575
Add binding for different usecases of i.MX8QM PCIe PHYs. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Frank Li <frank.li@nxp.com>
31 lines
990 B
C
31 lines
990 B
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* This header provides constants for i.MX8 PCIe.
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*/
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#ifndef _DT_BINDINGS_IMX8_PCIE_H
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#define _DT_BINDINGS_IMX8_PCIE_H
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/* Reference clock PAD mode */
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#define IMX8_PCIE_REFCLK_PAD_UNUSED 0
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#define IMX8_PCIE_REFCLK_PAD_INPUT 1
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#define IMX8_PCIE_REFCLK_PAD_OUTPUT 2
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/*
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* i.MX8QM HSIO(High Speed IO) module has three instances of single lane
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* SERDES PHY and an instance of two lanes PCIe GEN3 controller, an
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* instance of single lane PCIe GEN3 controller, as well as an instance
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* of SATA 3.0 controller.
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*
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* And HSIO module can be configured as the following different usecases.
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* 1 - A two lanes PCIea and a single lane SATA.
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* 2 - A single lane PCIea, a single lane PCIeb and a single lane SATA.
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* 3 - A two lanes PCIea, a single lane PCIeb.
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* Choose one mode, refer to the exact hardware board design.
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*/
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#define PCIEAX2SATA 1
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#define PCIEAX1PCIEBX1SATA 2
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#define PCIEAX2PCIEBX1 3
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#endif /* _DT_BINDINGS_IMX8_PCIE_H */
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