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9eb53327f2
The i.MX95 NETC's Timer is different from the LS1028A NETC's Timer. In addition to swapping the offsets of the upper 32-bit register and the lower 32-bit register and adding ALRAM and FIPER control registers, there are some main registers (such as the TMR_CTRL and TMR_ADD) that are used in different ways even though they have the same functionality. Yes, we can reuse the PTP driver of LS1028A and make some modifications to support i.MX95 NETC's Timer, but this will undoubtedly increase the complexity of the code and make the driver difficult to maintain. So we have added a new driver named ptp_netc to support NETC Timer of i.MX95 and future i.MX SoCs such as i.MX943, i.MX952, etc. Signed-off-by: Wei Fang <wei.fang@nxp.com> Acked-by: Clark Wang <xiaoning.wang@nxp.com>
19 lines
436 B
C
19 lines
436 B
C
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
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/* Copyright 2023 NXP
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* Copyright (c) 2023 Wei Fang <wei.fang@nxp.com>
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*/
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#ifndef _PTP_NETC_H
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#define _PTP_NETC_H
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#if IS_ENABLED(CONFIG_PTP_1588_CLOCK_NETC)
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int netc_timer_get_phc_index(int domain, unsigned int bus, unsigned int devfn);
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#else
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static inline int netc_timer_get_phc_index(int domain, unsigned int bus,
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unsigned int devfn)
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{
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return -1;
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}
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#endif
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#endif
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