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It is said that with PHY_MODE_ETHERNET, the MAC driver is in control of the SerDes lane, while with PHY_MODE_ETHERNET_LINKMODE, the internal PHY is (for backplane link modes). With the design decision to model the internal backplane PHY as phylink_pcs, integrated with the lynx pcs, now we have just the PHY_MODE_ETHERNET handling left in MAC drivers. So there needs to be some coordination between when does the MAC drive the SerDes phys, and when does the PCS drive them. If we take a step back, it becomes apparent that it is also possible to move the SerDes phy processing for PHY_MODE_ETHERNET from the MAC driver into the PCS driver, and then teach the PCS driver (in the future) to handle PHY_MODE_ETHERNET_LINKMODE for backplanes, and all of that can be transparent to the MAC. Extend lynx_pcs_create_mdiodev() and lynx_pcs_create_fwnode() with two extra arguments: "struct phy **phys, size_t num_phys" which represent the SerDes lanes (on LX2 we also support multi-lane link modes, like 40G, 50G, 100G, and each lane has a SerDes PHY). Populating phylink_config :: supported_interfaces can also be left down to the PCS, thus we also introduce lynx_pcs_set_supported_interfaces(). The SerDes phys are optional inside the lynx pcs driver. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
27 lines
727 B
C
27 lines
727 B
C
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
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/* Copyright 2020 NXP
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* Lynx PCS helpers
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*/
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#ifndef __LINUX_PCS_LYNX_H
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#define __LINUX_PCS_LYNX_H
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#include <linux/mdio.h>
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#include <linux/phy.h>
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#include <linux/phylink.h>
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struct phy;
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struct phylink_pcs *lynx_pcs_create_mdiodev(struct mii_bus *bus, int addr,
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struct phy **phys, size_t num_phys);
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struct phylink_pcs *lynx_pcs_create_fwnode(struct fwnode_handle *node,
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struct phy **phys, size_t num_phys);
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void lynx_pcs_destroy(struct phylink_pcs *pcs);
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void lynx_pcs_set_supported_interfaces(struct phylink_pcs *pcs,
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phy_interface_t default_interface,
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unsigned long *supported_interfaces);
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#endif /* __LINUX_PCS_LYNX_H */
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