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4c0e7ef18c
The LDO1 and LDO2 voltage num is wrong, so correct it. Signed-off-by: Joy Zou <joy.zou@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
177 lines
4.5 KiB
C
177 lines
4.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/* Copyright 2024 NXP. */
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#ifndef __LINUX_REG_PF9453_H__
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#define __LINUX_REG_PF9453_H__
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#include <linux/regmap.h>
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enum pf9453_chip_type {
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PF9453_TYPE_PF9453 = 0,
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PF9453_TYPE_AMOUNT,
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};
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enum {
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PF9453_BUCK1 = 0,
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PF9453_BUCK2,
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PF9453_BUCK3,
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PF9453_BUCK4,
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PF9453_LDO1,
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PF9453_LDO2,
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PF9453_LDOSNVS,
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PF9453_REGULATOR_CNT,
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};
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enum {
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PF9453_DVS_LEVEL_RUN = 0,
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PF9453_DVS_LEVEL_STANDBY,
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PF9453_DVS_LEVEL_DPSTANDBY,
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PF9453_DVS_LEVEL_MAX,
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};
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#define PF9453_BUCK1_VOLTAGE_NUM 0x80
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#define PF9453_BUCK2_VOLTAGE_NUM 0x80
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#define PF9453_BUCK3_VOLTAGE_NUM 0x80
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#define PF9453_BUCK4_VOLTAGE_NUM 0x80
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#define PF9453_LDO1_VOLTAGE_NUM 0x65
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#define PF9453_LDO2_VOLTAGE_NUM 0x3b
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#define PF9453_LDOSNVS_VOLTAGE_NUM 0x59
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enum {
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PF9453_REG_DEV_ID = 0x00,
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PF9453_REG_OTP_VER = 0x01,
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PF9453_REG_INT1 = 0x02,
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PF9453_REG_INT1_MSK = 0x03,
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PF9453_REG_INT1_STATUS = 0x04,
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PF9453_REG_VRFLT1_INT = 0x05,
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PF9453_REG_VRFLT1_MASK = 0x06,
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PF9453_REG_PWRON_STAT = 0x07,
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PF9453_REG_RESET_CTRL = 0x08,
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PF9453_REG_SW_RST = 0x09,
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PF9453_REG_PWR_CTRL = 0x0a,
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PF9453_REG_CONFIG1 = 0x0b,
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PF9453_REG_CONFIG2 = 0x0c,
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PF9453_REG_32K_CONFIG = 0x0d,
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PF9453_REG_BUCK1CTRL = 0x10,
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PF9453_REG_BUCK1OUT = 0x11,
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PF9453_REG_BUCK2CTRL = 0x14,
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PF9453_REG_BUCK2OUT = 0x15,
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PF9453_REG_BUCK2OUT_STBY = 0x1D,
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PF9453_REG_BUCK2OUT_MAX_LIMIT = 0x1F,
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PF9453_REG_BUCK2OUT_MIN_LIMIT = 0x20,
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PF9453_REG_BUCK3CTRL = 0x21,
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PF9453_REG_BUCK3OUT = 0x22,
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PF9453_REG_BUCK4CTRL = 0x2e,
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PF9453_REG_BUCK4OUT = 0x2f,
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PF9453_REG_LDO1OUT_L = 0x36,
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PF9453_REG_LDO1CFG = 0x37,
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PF9453_REG_LDO1OUT_H = 0x38,
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PF9453_REG_LDOSNVS_CFG1 = 0x39,
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PF9453_REG_LDOSNVS_CFG2 = 0x3a,
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PF9453_REG_LDO2CFG = 0x3b,
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PF9453_REG_LDO2OUT = 0x3c,
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PF9453_REG_BUCK_POK = 0x3d,
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PF9453_REG_LSW_CTRL1 = 0x40,
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PF9453_REG_LSW_CTRL2 = 0x41,
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PF9453_REG_LOCK = 0x4e,
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PF9453_MAX_REG,
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};
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#define PF9453_UNLOCK_KEY 0x5c
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#define PF9453_LOCK_KEY 0x0
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/* PF9453 BUCK ENMODE bits */
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#define BUCK_ENMODE_OFF 0x00
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#define BUCK_ENMODE_ONREQ 0x01
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#define BUCK_ENMODE_ONREQ_STBY 0x02
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#define BUCK_ENMODE_ONREQ_STBY_DPSTBY 0x03
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/* PF9453 BUCK ENMODE bits */
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#define LDO_ENMODE_OFF 0x00
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#define LDO_ENMODE_ONREQ 0x01
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#define LDO_ENMODE_ONREQ_STBY 0x02
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#define LDO_ENMODE_ONREQ_STBY_DPSTBY 0x03
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/* PF9453_REG_BUCK1_CTRL bits */
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#define BUCK1_LPMODE 0x30
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#define BUCK1_AD 0x08
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#define BUCK1_FPWM 0x04
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#define BUCK1_ENMODE_MASK 0x03
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/* PF9453_REG_BUCK2_CTRL bits */
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#define BUCK2_RAMP_MASK 0xC0
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#define BUCK2_RAMP_25MV 0x0
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#define BUCK2_RAMP_12P5MV 0x1
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#define BUCK2_RAMP_6P25MV 0x2
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#define BUCK2_RAMP_3P125MV 0x3
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#define BUCK2_LPMODE 0x30
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#define BUCK2_AD 0x08
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#define BUCK2_FPWM 0x04
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#define BUCK2_ENMODE_MASK 0x03
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/* PF9453_REG_BUCK3_CTRL bits */
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#define BUCK3_LPMODE 0x30
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#define BUCK3_AD 0x08
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#define BUCK3_FPWM 0x04
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#define BUCK3_ENMODE_MASK 0x03
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/* PF9453_REG_BUCK4_CTRL bits */
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#define BUCK4_LPMODE 0x30
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#define BUCK4_AD 0x08
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#define BUCK4_FPWM 0x04
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#define BUCK4_ENMODE_MASK 0x03
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/* PF9453_REG_BUCK123_PRESET_EN bit */
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#define BUCK123_PRESET_EN 0x80
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/* PF9453_BUCK1OUT bits */
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#define BUCK1OUT_MASK 0x7F
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/* PF9453_BUCK2OUT bits */
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#define BUCK2OUT_MASK 0x7F
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#define BUCK2OUT_STBY_MASK 0x7F
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/* PF9453_REG_BUCK3OUT bits */
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#define BUCK3OUT_MASK 0x7F
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/* PF9453_REG_BUCK4OUT bits */
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#define BUCK4OUT_MASK 0x7F
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/* PF9453_REG_LDO1_VOLT bits */
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#define LDO1_EN_MASK 0x3
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#define LDO1OUT_MASK 0x7F
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/* PF9453_REG_LDO2_VOLT bits */
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#define LDO2_EN_MASK 0x3
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#define LDO2OUT_MASK 0x7F
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/* PF9453_REG_LDOSNVS_VOLT bits */
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#define LDOSNVS_EN_MASK 0x1
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#define LDOSNVSCFG1_MASK 0x7F
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/* PF9453_REG_IRQ bits */
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#define IRQ_RSVD 0x80
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#define IRQ_RSTB 0x40
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#define IRQ_ONKEY 0x20
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#define IRQ_RESETKEY 0x10
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#define IRQ_VR_FLT1 0x08
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#define IRQ_LOWVSYS 0x04
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#define IRQ_THERM_100 0x02
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#define IRQ_THERM_80 0x01
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/* PF9453_REG_RESET_CTRL bits */
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#define WDOG_B_CFG_MASK 0xC0
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#define WDOG_B_CFG_NONE 0x00
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#define WDOG_B_CFG_WARM 0x40
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#define WDOG_B_CFG_COLD 0x80
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/* PF9453_REG_CONFIG2 bits */
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#define I2C_LT_MASK 0x03
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#define I2C_LT_FORCE_DISABLE 0x00
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#define I2C_LT_ON_STANDBY_RUN 0x01
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#define I2C_LT_ON_RUN 0x02
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#define I2C_LT_FORCE_ENABLE 0x03
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#endif /* __LINUX_REG_PF9453_H__ */
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