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0858ed035a
LIOINTC stands for "Legacy I/O Interrupts" that described in Section 11.1 of "Loongson 3A5000 Processor Reference Manual". For more information please refer Documentation/loongarch/irq-chip-model.rst. Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn> Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/1658314292-35346-11-git-send-email-lvjianmin@loongson.cn
150 lines
4.4 KiB
C
150 lines
4.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#ifndef _ASM_IRQ_H
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#define _ASM_IRQ_H
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#include <linux/irqdomain.h>
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#include <linux/irqreturn.h>
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#define IRQ_STACK_SIZE THREAD_SIZE
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#define IRQ_STACK_START (IRQ_STACK_SIZE - 16)
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DECLARE_PER_CPU(unsigned long, irq_stack);
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/*
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* The highest address on the IRQ stack contains a dummy frame which is
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* structured as follows:
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*
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* top ------------
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* | task sp | <- irq_stack[cpu] + IRQ_STACK_START
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* ------------
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* | | <- First frame of IRQ context
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* ------------
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*
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* task sp holds a copy of the task stack pointer where the struct pt_regs
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* from exception entry can be found.
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*/
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static inline bool on_irq_stack(int cpu, unsigned long sp)
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{
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unsigned long low = per_cpu(irq_stack, cpu);
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unsigned long high = low + IRQ_STACK_SIZE;
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return (low <= sp && sp <= high);
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}
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int get_ipi_irq(void);
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int get_pmc_irq(void);
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int get_timer_irq(void);
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void spurious_interrupt(void);
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#define NR_IRQS_LEGACY 16
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#define arch_trigger_cpumask_backtrace arch_trigger_cpumask_backtrace
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void arch_trigger_cpumask_backtrace(const struct cpumask *mask, bool exclude_self);
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#define MAX_IO_PICS 2
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#define NR_IRQS (64 + (256 * MAX_IO_PICS))
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struct acpi_vector_group {
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int node;
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int pci_segment;
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struct irq_domain *parent;
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};
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extern struct acpi_vector_group pch_group[MAX_IO_PICS];
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extern struct acpi_vector_group msi_group[MAX_IO_PICS];
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#define CORES_PER_EIO_NODE 4
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#define LOONGSON_CPU_UART0_VEC 10 /* CPU UART0 */
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#define LOONGSON_CPU_THSENS_VEC 14 /* CPU Thsens */
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#define LOONGSON_CPU_HT0_VEC 16 /* CPU HT0 irq vector base number */
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#define LOONGSON_CPU_HT1_VEC 24 /* CPU HT1 irq vector base number */
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/* IRQ number definitions */
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#define LOONGSON_LPC_IRQ_BASE 0
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#define LOONGSON_LPC_LAST_IRQ (LOONGSON_LPC_IRQ_BASE + 15)
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#define LOONGSON_CPU_IRQ_BASE 16
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#define LOONGSON_CPU_LAST_IRQ (LOONGSON_CPU_IRQ_BASE + 14)
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#define LOONGSON_PCH_IRQ_BASE 64
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#define LOONGSON_PCH_ACPI_IRQ (LOONGSON_PCH_IRQ_BASE + 47)
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#define LOONGSON_PCH_LAST_IRQ (LOONGSON_PCH_IRQ_BASE + 64 - 1)
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#define LOONGSON_MSI_IRQ_BASE (LOONGSON_PCH_IRQ_BASE + 64)
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#define LOONGSON_MSI_LAST_IRQ (LOONGSON_PCH_IRQ_BASE + 256 - 1)
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#define GSI_MIN_LPC_IRQ LOONGSON_LPC_IRQ_BASE
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#define GSI_MAX_LPC_IRQ (LOONGSON_LPC_IRQ_BASE + 16 - 1)
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#define GSI_MIN_CPU_IRQ LOONGSON_CPU_IRQ_BASE
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#define GSI_MAX_CPU_IRQ (LOONGSON_CPU_IRQ_BASE + 48 - 1)
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#define GSI_MIN_PCH_IRQ LOONGSON_PCH_IRQ_BASE
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#define GSI_MAX_PCH_IRQ (LOONGSON_PCH_IRQ_BASE + 256 - 1)
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extern int find_pch_pic(u32 gsi);
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extern int eiointc_get_node(int id);
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static inline void eiointc_enable(void)
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{
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uint64_t misc;
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misc = iocsr_read64(LOONGARCH_IOCSR_MISC_FUNC);
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misc |= IOCSR_MISC_FUNC_EXT_IOI_EN;
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iocsr_write64(misc, LOONGARCH_IOCSR_MISC_FUNC);
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}
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struct acpi_madt_lio_pic;
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struct acpi_madt_eio_pic;
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struct acpi_madt_ht_pic;
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struct acpi_madt_bio_pic;
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struct acpi_madt_msi_pic;
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struct acpi_madt_lpc_pic;
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struct irq_domain *loongarch_cpu_irq_init(void);
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int liointc_acpi_init(struct irq_domain *parent,
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struct acpi_madt_lio_pic *acpi_liointc);
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struct irq_domain *eiointc_acpi_init(struct irq_domain *parent,
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struct acpi_madt_eio_pic *acpi_eiointc);
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struct irq_domain *htvec_acpi_init(struct irq_domain *parent,
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struct acpi_madt_ht_pic *acpi_htvec);
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int pch_lpc_acpi_init(struct irq_domain *parent,
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struct acpi_madt_lpc_pic *acpi_pchlpc);
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#if IS_ENABLED(CONFIG_LOONGSON_PCH_MSI)
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int pch_msi_acpi_init(struct irq_domain *parent,
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struct acpi_madt_msi_pic *acpi_pchmsi);
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#else
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static inline int pch_msi_acpi_init(struct irq_domain *parent,
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struct acpi_madt_msi_pic *acpi_pchmsi)
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{
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return 0;
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}
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#endif
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int pch_pic_acpi_init(struct irq_domain *parent,
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struct acpi_madt_bio_pic *acpi_pchpic);
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int find_pch_pic(u32 gsi);
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struct fwnode_handle *get_pch_msi_handle(int pci_segment);
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extern struct acpi_madt_lio_pic *acpi_liointc;
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extern struct acpi_madt_eio_pic *acpi_eiointc[MAX_IO_PICS];
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extern struct acpi_madt_ht_pic *acpi_htintc;
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extern struct acpi_madt_lpc_pic *acpi_pchlpc;
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extern struct acpi_madt_msi_pic *acpi_pchmsi[MAX_IO_PICS];
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extern struct acpi_madt_bio_pic *acpi_pchpic[MAX_IO_PICS];
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extern struct irq_domain *cpu_domain;
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extern struct fwnode_handle *liointc_handle;
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extern struct fwnode_handle *pch_lpc_handle;
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extern struct fwnode_handle *pch_pic_handle[MAX_IO_PICS];
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extern irqreturn_t loongson3_ipi_interrupt(int irq, void *dev);
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#include <asm-generic/irq.h>
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#endif /* _ASM_IRQ_H */
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