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The RISC-V advanced interrupt architecture (AIA) specification defines advanced platform-level interrupt controller (APLIC) which has two modes of operation: 1) Direct mode and 2) MSI mode. (For more details, refer https://github.com/riscv/riscv-aia) In APLIC direct-mode, wired interrupts are forwared to CPUs (or HARTs) as a local external interrupt. Add a platform irqchip driver for the RISC-V APLIC direct-mode to support RISC-V platforms having only wired interrupts. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Björn Töpel <bjorn@rivosinc.com> Reviewed-by: Björn Töpel <bjorn@rivosinc.com> Link: https://lore.kernel.org/r/20240307140307.646078-7-apatel@ventanamicro.com
146 lines
4.5 KiB
C
146 lines
4.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2021 Western Digital Corporation or its affiliates.
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* Copyright (C) 2022 Ventana Micro Systems Inc.
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*/
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#ifndef __LINUX_IRQCHIP_RISCV_APLIC_H
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#define __LINUX_IRQCHIP_RISCV_APLIC_H
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#include <linux/bitops.h>
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#define APLIC_MAX_IDC BIT(14)
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#define APLIC_MAX_SOURCE 1024
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#define APLIC_DOMAINCFG 0x0000
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#define APLIC_DOMAINCFG_RDONLY 0x80000000
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#define APLIC_DOMAINCFG_IE BIT(8)
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#define APLIC_DOMAINCFG_DM BIT(2)
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#define APLIC_DOMAINCFG_BE BIT(0)
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#define APLIC_SOURCECFG_BASE 0x0004
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#define APLIC_SOURCECFG_D BIT(10)
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#define APLIC_SOURCECFG_CHILDIDX_MASK 0x000003ff
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#define APLIC_SOURCECFG_SM_MASK 0x00000007
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#define APLIC_SOURCECFG_SM_INACTIVE 0x0
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#define APLIC_SOURCECFG_SM_DETACH 0x1
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#define APLIC_SOURCECFG_SM_EDGE_RISE 0x4
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#define APLIC_SOURCECFG_SM_EDGE_FALL 0x5
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#define APLIC_SOURCECFG_SM_LEVEL_HIGH 0x6
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#define APLIC_SOURCECFG_SM_LEVEL_LOW 0x7
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#define APLIC_MMSICFGADDR 0x1bc0
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#define APLIC_MMSICFGADDRH 0x1bc4
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#define APLIC_SMSICFGADDR 0x1bc8
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#define APLIC_SMSICFGADDRH 0x1bcc
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#ifdef CONFIG_RISCV_M_MODE
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#define APLIC_xMSICFGADDR APLIC_MMSICFGADDR
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#define APLIC_xMSICFGADDRH APLIC_MMSICFGADDRH
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#else
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#define APLIC_xMSICFGADDR APLIC_SMSICFGADDR
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#define APLIC_xMSICFGADDRH APLIC_SMSICFGADDRH
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#endif
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#define APLIC_xMSICFGADDRH_L BIT(31)
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#define APLIC_xMSICFGADDRH_HHXS_MASK 0x1f
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#define APLIC_xMSICFGADDRH_HHXS_SHIFT 24
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#define APLIC_xMSICFGADDRH_HHXS (APLIC_xMSICFGADDRH_HHXS_MASK << \
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APLIC_xMSICFGADDRH_HHXS_SHIFT)
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#define APLIC_xMSICFGADDRH_LHXS_MASK 0x7
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#define APLIC_xMSICFGADDRH_LHXS_SHIFT 20
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#define APLIC_xMSICFGADDRH_LHXS (APLIC_xMSICFGADDRH_LHXS_MASK << \
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APLIC_xMSICFGADDRH_LHXS_SHIFT)
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#define APLIC_xMSICFGADDRH_HHXW_MASK 0x7
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#define APLIC_xMSICFGADDRH_HHXW_SHIFT 16
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#define APLIC_xMSICFGADDRH_HHXW (APLIC_xMSICFGADDRH_HHXW_MASK << \
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APLIC_xMSICFGADDRH_HHXW_SHIFT)
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#define APLIC_xMSICFGADDRH_LHXW_MASK 0xf
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#define APLIC_xMSICFGADDRH_LHXW_SHIFT 12
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#define APLIC_xMSICFGADDRH_LHXW (APLIC_xMSICFGADDRH_LHXW_MASK << \
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APLIC_xMSICFGADDRH_LHXW_SHIFT)
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#define APLIC_xMSICFGADDRH_BAPPN_MASK 0xfff
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#define APLIC_xMSICFGADDRH_BAPPN_SHIFT 0
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#define APLIC_xMSICFGADDRH_BAPPN (APLIC_xMSICFGADDRH_BAPPN_MASK << \
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APLIC_xMSICFGADDRH_BAPPN_SHIFT)
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#define APLIC_xMSICFGADDR_PPN_SHIFT 12
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#define APLIC_xMSICFGADDR_PPN_HART(__lhxs) \
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(BIT(__lhxs) - 1)
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#define APLIC_xMSICFGADDR_PPN_LHX_MASK(__lhxw) \
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(BIT(__lhxw) - 1)
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#define APLIC_xMSICFGADDR_PPN_LHX_SHIFT(__lhxs) \
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((__lhxs))
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#define APLIC_xMSICFGADDR_PPN_LHX(__lhxw, __lhxs) \
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(APLIC_xMSICFGADDR_PPN_LHX_MASK(__lhxw) << \
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APLIC_xMSICFGADDR_PPN_LHX_SHIFT(__lhxs))
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#define APLIC_xMSICFGADDR_PPN_HHX_MASK(__hhxw) \
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(BIT(__hhxw) - 1)
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#define APLIC_xMSICFGADDR_PPN_HHX_SHIFT(__hhxs) \
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((__hhxs) + APLIC_xMSICFGADDR_PPN_SHIFT)
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#define APLIC_xMSICFGADDR_PPN_HHX(__hhxw, __hhxs) \
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(APLIC_xMSICFGADDR_PPN_HHX_MASK(__hhxw) << \
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APLIC_xMSICFGADDR_PPN_HHX_SHIFT(__hhxs))
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#define APLIC_IRQBITS_PER_REG 32
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#define APLIC_SETIP_BASE 0x1c00
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#define APLIC_SETIPNUM 0x1cdc
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#define APLIC_CLRIP_BASE 0x1d00
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#define APLIC_CLRIPNUM 0x1ddc
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#define APLIC_SETIE_BASE 0x1e00
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#define APLIC_SETIENUM 0x1edc
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#define APLIC_CLRIE_BASE 0x1f00
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#define APLIC_CLRIENUM 0x1fdc
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#define APLIC_SETIPNUM_LE 0x2000
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#define APLIC_SETIPNUM_BE 0x2004
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#define APLIC_GENMSI 0x3000
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#define APLIC_TARGET_BASE 0x3004
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#define APLIC_TARGET_HART_IDX_SHIFT 18
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#define APLIC_TARGET_HART_IDX_MASK 0x3fff
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#define APLIC_TARGET_HART_IDX (APLIC_TARGET_HART_IDX_MASK << \
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APLIC_TARGET_HART_IDX_SHIFT)
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#define APLIC_TARGET_GUEST_IDX_SHIFT 12
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#define APLIC_TARGET_GUEST_IDX_MASK 0x3f
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#define APLIC_TARGET_GUEST_IDX (APLIC_TARGET_GUEST_IDX_MASK << \
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APLIC_TARGET_GUEST_IDX_SHIFT)
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#define APLIC_TARGET_IPRIO_SHIFT 0
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#define APLIC_TARGET_IPRIO_MASK 0xff
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#define APLIC_TARGET_IPRIO (APLIC_TARGET_IPRIO_MASK << \
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APLIC_TARGET_IPRIO_SHIFT)
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#define APLIC_TARGET_EIID_SHIFT 0
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#define APLIC_TARGET_EIID_MASK 0x7ff
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#define APLIC_TARGET_EIID (APLIC_TARGET_EIID_MASK << \
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APLIC_TARGET_EIID_SHIFT)
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#define APLIC_IDC_BASE 0x4000
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#define APLIC_IDC_SIZE 32
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#define APLIC_IDC_IDELIVERY 0x00
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#define APLIC_IDC_IFORCE 0x04
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#define APLIC_IDC_ITHRESHOLD 0x08
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#define APLIC_IDC_TOPI 0x18
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#define APLIC_IDC_TOPI_ID_SHIFT 16
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#define APLIC_IDC_TOPI_ID_MASK 0x3ff
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#define APLIC_IDC_TOPI_ID (APLIC_IDC_TOPI_ID_MASK << \
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APLIC_IDC_TOPI_ID_SHIFT)
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#define APLIC_IDC_TOPI_PRIO_SHIFT 0
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#define APLIC_IDC_TOPI_PRIO_MASK 0xff
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#define APLIC_IDC_TOPI_PRIO (APLIC_IDC_TOPI_PRIO_MASK << \
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APLIC_IDC_TOPI_PRIO_SHIFT)
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#define APLIC_IDC_CLAIMI 0x1c
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#endif
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