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b2adbc9cea
Introduce a new PLL reset mode flag which controls whether or not to reset a PLL after adjusting its rate. The mode can be configured through platform data or device tree. Since commit6dc669a22c("clk: si5351: Add PLL soft reset"), the driver unconditionally resets a PLL whenever its rate is adjusted. The rationale was that a PLL reset was required to get three outputs working at the same time. Before this change, the driver never reset the PLLs. Commitb26ff127c5("clk: si5351: Apply PLL soft reset before enabling the outputs") subsequently introduced an option to reset the PLL when enabling a clock output that sourced it. Here, the rationale was that this is required to get a deterministic phase relationship between multiple output clocks. This clearly shows that it is useful to reset the PLLs in applications where multiple clock outputs are used. However, the Si5351 also allows for glitch-free rate adjustment of its PLLs if one avoids resetting the PLL. In our audio application where a single Si5351 clock output is used to supply a runtime adjustable bit clock, this unconditional PLL reset behaviour introduces unwanted glitches in the clock output. It would appear that the problem being solved in the former commit may be solved by using the optional device tree property introduced in the latter commit, obviating the need for an unconditional PLL reset after rate adjustment. But it's not OK to break the default behaviour of the driver, and it cannot be assumed that all device trees are using the property introduced in the latter commit. Hence, the new behaviour is made opt-in. Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: Rabeeh Khoury <rabeeh@solid-run.com> Cc: Jacob Siverskog <jacob@teenage.engineering> Cc: Sergej Sawazki <sergej@taudac.com> Signed-off-by: Alvin Šipraga <alsi@bang-olufsen.dk> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Link: https://lore.kernel.org/r/20231124-alvin-clk-si5351-no-pll-reset-v6-3-69b82311cb90@bang-olufsen.dk Signed-off-by: Stephen Boyd <sboyd@kernel.org>
118 lines
3.6 KiB
C
118 lines
3.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Si5351A/B/C programmable clock generator platform_data.
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*/
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#ifndef __LINUX_PLATFORM_DATA_SI5351_H__
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#define __LINUX_PLATFORM_DATA_SI5351_H__
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/**
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* enum si5351_pll_src - Si5351 pll clock source
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* @SI5351_PLL_SRC_DEFAULT: default, do not change eeprom config
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* @SI5351_PLL_SRC_XTAL: pll source clock is XTAL input
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* @SI5351_PLL_SRC_CLKIN: pll source clock is CLKIN input (Si5351C only)
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*/
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enum si5351_pll_src {
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SI5351_PLL_SRC_DEFAULT = 0,
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SI5351_PLL_SRC_XTAL = 1,
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SI5351_PLL_SRC_CLKIN = 2,
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};
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/**
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* enum si5351_multisynth_src - Si5351 multisynth clock source
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* @SI5351_MULTISYNTH_SRC_DEFAULT: default, do not change eeprom config
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* @SI5351_MULTISYNTH_SRC_VCO0: multisynth source clock is VCO0
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* @SI5351_MULTISYNTH_SRC_VCO1: multisynth source clock is VCO1/VXCO
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*/
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enum si5351_multisynth_src {
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SI5351_MULTISYNTH_SRC_DEFAULT = 0,
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SI5351_MULTISYNTH_SRC_VCO0 = 1,
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SI5351_MULTISYNTH_SRC_VCO1 = 2,
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};
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/**
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* enum si5351_clkout_src - Si5351 clock output clock source
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* @SI5351_CLKOUT_SRC_DEFAULT: default, do not change eeprom config
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* @SI5351_CLKOUT_SRC_MSYNTH_N: clkout N source clock is multisynth N
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* @SI5351_CLKOUT_SRC_MSYNTH_0_4: clkout N source clock is multisynth 0 (N<4)
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* or 4 (N>=4)
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* @SI5351_CLKOUT_SRC_XTAL: clkout N source clock is XTAL
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* @SI5351_CLKOUT_SRC_CLKIN: clkout N source clock is CLKIN (Si5351C only)
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*/
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enum si5351_clkout_src {
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SI5351_CLKOUT_SRC_DEFAULT = 0,
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SI5351_CLKOUT_SRC_MSYNTH_N = 1,
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SI5351_CLKOUT_SRC_MSYNTH_0_4 = 2,
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SI5351_CLKOUT_SRC_XTAL = 3,
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SI5351_CLKOUT_SRC_CLKIN = 4,
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};
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/**
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* enum si5351_drive_strength - Si5351 clock output drive strength
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* @SI5351_DRIVE_DEFAULT: default, do not change eeprom config
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* @SI5351_DRIVE_2MA: 2mA clock output drive strength
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* @SI5351_DRIVE_4MA: 4mA clock output drive strength
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* @SI5351_DRIVE_6MA: 6mA clock output drive strength
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* @SI5351_DRIVE_8MA: 8mA clock output drive strength
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*/
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enum si5351_drive_strength {
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SI5351_DRIVE_DEFAULT = 0,
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SI5351_DRIVE_2MA = 2,
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SI5351_DRIVE_4MA = 4,
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SI5351_DRIVE_6MA = 6,
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SI5351_DRIVE_8MA = 8,
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};
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/**
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* enum si5351_disable_state - Si5351 clock output disable state
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* @SI5351_DISABLE_DEFAULT: default, do not change eeprom config
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* @SI5351_DISABLE_LOW: CLKx is set to a LOW state when disabled
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* @SI5351_DISABLE_HIGH: CLKx is set to a HIGH state when disabled
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* @SI5351_DISABLE_FLOATING: CLKx is set to a FLOATING state when
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* disabled
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* @SI5351_DISABLE_NEVER: CLKx is NEVER disabled
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*/
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enum si5351_disable_state {
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SI5351_DISABLE_DEFAULT = 0,
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SI5351_DISABLE_LOW,
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SI5351_DISABLE_HIGH,
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SI5351_DISABLE_FLOATING,
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SI5351_DISABLE_NEVER,
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};
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/**
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* struct si5351_clkout_config - Si5351 clock output configuration
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* @clkout: clkout number
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* @multisynth_src: multisynth source clock
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* @clkout_src: clkout source clock
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* @pll_master: if true, clkout can also change pll rate
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* @pll_reset: if true, clkout can reset its pll
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* @drive: output drive strength
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* @rate: initial clkout rate, or default if 0
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*/
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struct si5351_clkout_config {
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enum si5351_multisynth_src multisynth_src;
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enum si5351_clkout_src clkout_src;
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enum si5351_drive_strength drive;
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enum si5351_disable_state disable_state;
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bool pll_master;
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bool pll_reset;
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unsigned long rate;
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};
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/**
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* struct si5351_platform_data - Platform data for the Si5351 clock driver
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* @clk_xtal: xtal input clock
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* @clk_clkin: clkin input clock
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* @pll_src: array of pll source clock setting
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* @pll_reset: array indicating if plls should be reset after setting the rate
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* @clkout: array of clkout configuration
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*/
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struct si5351_platform_data {
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enum si5351_pll_src pll_src[2];
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bool pll_reset[2];
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struct si5351_clkout_config clkout[8];
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};
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#endif
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