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drm/panel: himax-hx8394: Add Support for Microchip AC40T08A MIPI Display Panel
Add support for the Microchip AC40T08A MIPI Display panel. This panel uses a Himax HX8394 display controller and requires a vendor provided init sequence. The display resolution is 720x1280@60Hz with width and height of 76mm and 132mm respectively. Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240701085837.50855-4-manikandan.m@microchip.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20240701085837.50855-4-manikandan.m@microchip.com
This commit is contained in:
Manikandan Muralidharan
Neil Armstrong
parent
1dcfca093b
commit
014e597d35
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@ -339,6 +339,156 @@ static const struct hx8394_panel_desc powkiddy_x55_desc = {
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.init_sequence = powkiddy_x55_init_sequence,
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};
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static int mchp_ac40t08a_init_sequence(struct hx8394 *ctx)
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{
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struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
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/* DCS commands do not seem to be sent correclty without this delay */
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msleep(20);
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/* 5.19.8 SETEXTC: Set extension command (B9h) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETEXTC,
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0xff, 0x83, 0x94);
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/* 5.19.9 SETMIPI: Set MIPI control (BAh) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETMIPI,
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0x63, 0x03, 0x68, 0x6b, 0xb2, 0xc0);
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/* 5.19.2 SETPOWER: Set power (B1h) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETPOWER,
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0x48, 0x12, 0x72, 0x09, 0x32, 0x54,
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0x71, 0x71, 0x57, 0x47);
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/* 5.19.3 SETDISP: Set display related register (B2h) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETDISP,
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0x00, 0x80, 0x64, 0x0c, 0x0d, 0x2f);
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/* 5.19.4 SETCYC: Set display waveform cycles (B4h) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETCYC,
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0x73, 0x74, 0x73, 0x74, 0x73, 0x74,
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0x01, 0x0c, 0x86, 0x75, 0x00, 0x3f,
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0x73, 0x74, 0x73, 0x74, 0x73, 0x74,
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0x01, 0x0c, 0x86);
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/* 5.19.5 SETVCOM: Set VCOM voltage (B6h) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETVCOM,
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0x6e, 0x6e);
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/* 5.19.19 SETGIP0: Set GIP Option0 (D3h) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP0,
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0x00, 0x00, 0x07, 0x07, 0x40, 0x07,
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0x0c, 0x00, 0x08, 0x10, 0x08, 0x00,
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0x08, 0x54, 0x15, 0x0a, 0x05, 0x0a,
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0x02, 0x15, 0x06, 0x05, 0x06, 0x47,
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0x44, 0x0a, 0x0a, 0x4b, 0x10, 0x07,
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0x07, 0x0c, 0x40);
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/* 5.19.20 Set GIP Option1 (D5h) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP1,
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0x1c, 0x1c, 0x1d, 0x1d, 0x00, 0x01,
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0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
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0x08, 0x09, 0x0a, 0x0b, 0x24, 0x25,
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0x18, 0x18, 0x26, 0x27, 0x18, 0x18,
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0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
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0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
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0x18, 0x18, 0x20, 0x21, 0x18, 0x18,
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0x18, 0x18);
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/* 5.19.21 Set GIP Option2 (D6h) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP2,
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0x1c, 0x1c, 0x1d, 0x1d, 0x07, 0x06,
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0x05, 0x04, 0x03, 0x02, 0x01, 0x00,
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0x0b, 0x0a, 0x09, 0x08, 0x21, 0x20,
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0x18, 0x18, 0x27, 0x26, 0x18, 0x18,
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0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
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0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
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0x18, 0x18, 0x25, 0x24, 0x18, 0x18,
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0x18, 0x18);
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/* 5.19.25 SETGAMMA: Set gamma curve related setting (E0h) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGAMMA,
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0x00, 0x0a, 0x15, 0x1b, 0x1e, 0x21,
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0x24, 0x22, 0x47, 0x56, 0x65, 0x66,
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0x6e, 0x82, 0x88, 0x8b, 0x9a, 0x9d,
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0x98, 0xa8, 0xb9, 0x5d, 0x5c, 0x61,
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0x66, 0x6a, 0x6f, 0x7f, 0x7f, 0x00,
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0x0a, 0x15, 0x1b, 0x1e, 0x21, 0x24,
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0x22, 0x47, 0x56, 0x65, 0x65, 0x6e,
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0x81, 0x87, 0x8b, 0x98, 0x9d, 0x99,
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0xa8, 0xba, 0x5d, 0x5d, 0x62, 0x67,
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0x6b, 0x72, 0x7f, 0x7f);
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/* Unknown command, not listed in the HX8394-F datasheet (C0H) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN1,
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0x1f, 0x73);
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/* Set CABC control (C9h)*/
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETCABC,
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0x76, 0x00, 0x30);
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/* 5.19.17 SETPANEL (CCh) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETPANEL,
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0x0b);
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/* Unknown command, not listed in the HX8394-F datasheet (D4h) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN3,
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0x02);
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/* 5.19.11 Set register bank (BDh) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETREGBANK,
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0x02);
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/* 5.19.11 Set register bank (D8h) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN4,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
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/* 5.19.11 Set register bank (BDh) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETREGBANK,
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0x00);
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/* 5.19.11 Set register bank (BDh) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETREGBANK,
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0x01);
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/* 5.19.2 SETPOWER: Set power (B1h) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETPOWER,
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0x00);
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/* 5.19.11 Set register bank (BDh) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETREGBANK,
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0x00);
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/* Unknown command, not listed in the HX8394-F datasheet (C6h) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN2,
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0xed);
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return 0;
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}
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static const struct drm_display_mode mchp_ac40t08a_mode = {
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.hdisplay = 720,
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.hsync_start = 720 + 12,
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.hsync_end = 720 + 12 + 24,
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.htotal = 720 + 12 + 12 + 24,
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.vdisplay = 1280,
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.vsync_start = 1280 + 13,
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.vsync_end = 1280 + 14,
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.vtotal = 1280 + 14 + 13,
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.clock = 60226,
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.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
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.width_mm = 76,
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.height_mm = 132,
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};
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static const struct hx8394_panel_desc mchp_ac40t08a_desc = {
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.mode = &mchp_ac40t08a_mode,
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.lanes = 4,
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.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST,
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.format = MIPI_DSI_FMT_RGB888,
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.init_sequence = mchp_ac40t08a_init_sequence,
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};
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static int hx8394_enable(struct drm_panel *panel)
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{
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struct hx8394 *ctx = panel_to_hx8394(panel);
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@ -555,6 +705,7 @@ static void hx8394_remove(struct mipi_dsi_device *dsi)
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static const struct of_device_id hx8394_of_match[] = {
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{ .compatible = "hannstar,hsd060bhw4", .data = &hsd060bhw4_desc },
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{ .compatible = "powkiddy,x55-panel", .data = &powkiddy_x55_desc },
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{ .compatible = "microchip,ac40t08a-mipi-panel", .data = &mchp_ac40t08a_desc },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, hx8394_of_match);
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