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clk: renesas: div6: Implement range checking

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Consider the minimum and maximum clock rates imposed by clock users when
calculating the most appropriate clock rate in the .determine_rate()
callback.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/35ceb262c71f1b2e9864a39bde9dafd78b2981f4.1617281699.git.geert+renesas@glider.be
This commit is contained in:
Geert Uytterhoeven 2021-04-01 15:01:38 +02:00
parent 1c924fc679
commit 02c69593e6
1 changed files with 7 additions and 1 deletions
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8
drivers/clk/renesas/clk-div6.c
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@ -106,8 +106,8 @@ static int cpg_div6_clock_determine_rate(struct clk_hw *hw,
unsigned long prate, calc_rate, diff, best_rate, best_prate; unsigned long prate, calc_rate, diff, best_rate, best_prate;
unsigned int num_parents = clk_hw_get_num_parents(hw); unsigned int num_parents = clk_hw_get_num_parents(hw);
struct clk_hw *parent, *best_parent = NULL; struct clk_hw *parent, *best_parent = NULL;
unsigned int i, min_div, max_div, div;
unsigned long min_diff = ULONG_MAX; unsigned long min_diff = ULONG_MAX;
unsigned int i, div;
for (i = 0; i < num_parents; i++) { for (i = 0; i < num_parents; i++) {
parent = clk_hw_get_parent_by_index(hw, i); parent = clk_hw_get_parent_by_index(hw, i);
@ -118,7 +118,13 @@ static int cpg_div6_clock_determine_rate(struct clk_hw *hw,
if (!prate) if (!prate)
continue; continue;
min_div = max(DIV_ROUND_UP(prate, req->max_rate), 1UL);
max_div = req->min_rate ? min(prate / req->min_rate, 64UL) : 64;
if (max_div < min_div)
continue;
div = cpg_div6_clock_calc_div(req->rate, prate); div = cpg_div6_clock_calc_div(req->rate, prate);
div = clamp(div, min_div, max_div);
calc_rate = prate / div; calc_rate = prate / div;
diff = calc_rate > req->rate ? calc_rate - req->rate diff = calc_rate > req->rate ? calc_rate - req->rate
: req->rate - calc_rate; : req->rate - calc_rate;