mirror of
git://git.yoctoproject.org/linux-yocto.git
synced 2025-10-23 07:23:12 +02:00
Merge branches 'acpi-processor' and 'acpi-cppc'
Merge ACPI processor driver updates and ACPI CPPC library updates for 6.16-rc1: - Clean up the initialization of CPU data structures in the ACPI processor driver (Zhang Rui). - Remove an obsolete comment regarding the C-states handling in the ACPI processor driver (Giovanni Gherdovich). - Simplify PCC shared memory region handling (Sudeep Holla). - Rework and extend functions for reading CPPC register values and for updating CPPC registers (Lifeng Zheng). - Add three functions related to autonomous CPU performance state selection to the CPPC library (Lifeng Zheng). * acpi-processor: ACPI: processor: idle: Remove redundant pr->power.count assignment ACPI: processor: idle: Set pr->flags.power unconditionally ACPI: processor: idle: Remove obsolete comment * acpi-cppc: ACPI: CPPC: Add three functions related to autonomous selection ACPI: CPPC: Modify cppc_get_auto_sel_caps() to cppc_get_auto_sel() ACPI: CPPC: Refactor register value get and set ABIs ACPI: CPPC: Add cppc_set_reg_val() ACPI: CPPC: Extract cppc_get_reg_val_in_pcc() ACPI: CPPC: Rename cppc_get_perf() to cppc_get_reg_val() ACPI: CPPC: Optimize cppc_get_perf() ACPI: CPPC: Add IS_OPTIONAL_CPC_REG macro to judge if a cpc_reg is optional ACPI: CPPC: Simplify PCC shared memory region handling ACPI: PCC: Simplify PCC shared memory region handling
This commit is contained in:
Rafael J. Wysocki
commit
0a17adc6be
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@ -31,7 +31,6 @@
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struct pcc_data {
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struct pcc_mbox_chan *pcc_chan;
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void __iomem *pcc_comm_addr;
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struct completion done;
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struct mbox_client cl;
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struct acpi_pcc_info ctx;
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@ -81,14 +80,6 @@ acpi_pcc_address_space_setup(acpi_handle region_handle, u32 function,
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ret = AE_SUPPORT;
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goto err_free_channel;
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}
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data->pcc_comm_addr = acpi_os_ioremap(pcc_chan->shmem_base_addr,
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pcc_chan->shmem_size);
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if (!data->pcc_comm_addr) {
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pr_err("Failed to ioremap PCC comm region mem for %d\n",
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ctx->subspace_id);
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ret = AE_NO_MEMORY;
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goto err_free_channel;
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}
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*region_context = data;
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return AE_OK;
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@ -113,7 +104,7 @@ acpi_pcc_address_space_handler(u32 function, acpi_physical_address addr,
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reinit_completion(&data->done);
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/* Write to Shared Memory */
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memcpy_toio(data->pcc_comm_addr, (void *)value, data->ctx.length);
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memcpy_toio(data->pcc_chan->shmem, (void *)value, data->ctx.length);
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ret = mbox_send_message(data->pcc_chan->mchan, NULL);
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if (ret < 0)
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@ -134,7 +125,7 @@ acpi_pcc_address_space_handler(u32 function, acpi_physical_address addr,
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mbox_chan_txdone(data->pcc_chan->mchan, ret);
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memcpy_fromio(value, data->pcc_comm_addr, data->ctx.length);
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memcpy_fromio(value, data->pcc_chan->shmem, data->ctx.length);
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return AE_OK;
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}
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@ -47,7 +47,6 @@
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struct cppc_pcc_data {
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struct pcc_mbox_chan *pcc_channel;
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void __iomem *pcc_comm_addr;
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bool pcc_channel_acquired;
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unsigned int deadline_us;
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unsigned int pcc_mpar, pcc_mrtt, pcc_nominal;
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@ -95,7 +94,7 @@ static DEFINE_PER_CPU(int, cpu_pcc_subspace_idx);
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static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);
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/* pcc mapped address + header size + offset within PCC subspace */
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#define GET_PCC_VADDR(offs, pcc_ss_id) (pcc_data[pcc_ss_id]->pcc_comm_addr + \
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#define GET_PCC_VADDR(offs, pcc_ss_id) (pcc_data[pcc_ss_id]->pcc_channel->shmem + \
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0x8 + (offs))
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/* Check if a CPC register is in PCC */
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@ -129,6 +128,20 @@ static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);
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#define CPC_SUPPORTED(cpc) ((cpc)->type == ACPI_TYPE_INTEGER ? \
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!!(cpc)->cpc_entry.int_value : \
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!IS_NULL_REG(&(cpc)->cpc_entry.reg))
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/*
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* Each bit indicates the optionality of the register in per-cpu
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* cpc_regs[] with the corresponding index. 0 means mandatory and 1
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* means optional.
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*/
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#define REG_OPTIONAL (0x1FC7D0)
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/*
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* Use the index of the register in per-cpu cpc_regs[] to check if
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* it's an optional one.
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*/
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#define IS_OPTIONAL_CPC_REG(reg_idx) (REG_OPTIONAL & (1U << (reg_idx)))
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/*
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* Arbitrary Retries in case the remote processor is slow to respond
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* to PCC commands. Keeping it high enough to cover emulators where
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@ -223,7 +236,7 @@ static int check_pcc_chan(int pcc_ss_id, bool chk_err_bit)
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int ret, status;
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struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];
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struct acpi_pcct_shared_memory __iomem *generic_comm_base =
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pcc_ss_data->pcc_comm_addr;
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pcc_ss_data->pcc_channel->shmem;
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if (!pcc_ss_data->platform_owns_pcc)
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return 0;
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@ -258,7 +271,7 @@ static int send_pcc_cmd(int pcc_ss_id, u16 cmd)
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int ret = -EIO, i;
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struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];
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struct acpi_pcct_shared_memory __iomem *generic_comm_base =
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pcc_ss_data->pcc_comm_addr;
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pcc_ss_data->pcc_channel->shmem;
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unsigned int time_delta;
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/*
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@ -571,15 +584,6 @@ static int register_pcc_channel(int pcc_ss_idx)
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pcc_data[pcc_ss_idx]->pcc_mpar = pcc_chan->max_access_rate;
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pcc_data[pcc_ss_idx]->pcc_nominal = pcc_chan->latency;
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pcc_data[pcc_ss_idx]->pcc_comm_addr =
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acpi_os_ioremap(pcc_chan->shmem_base_addr,
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pcc_chan->shmem_size);
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if (!pcc_data[pcc_ss_idx]->pcc_comm_addr) {
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pr_err("Failed to ioremap PCC comm region mem for %d\n",
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pcc_ss_idx);
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return -ENOMEM;
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}
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/* Set flag so that we don't come here for each CPU. */
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pcc_data[pcc_ss_idx]->pcc_channel_acquired = true;
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}
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@ -1175,43 +1179,106 @@ static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val)
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return ret_val;
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}
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static int cppc_get_perf(int cpunum, enum cppc_regs reg_idx, u64 *perf)
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static int cppc_get_reg_val_in_pcc(int cpu, struct cpc_register_resource *reg, u64 *val)
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{
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struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
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int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
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struct cppc_pcc_data *pcc_ss_data = NULL;
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int ret;
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if (pcc_ss_id < 0) {
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pr_debug("Invalid pcc_ss_id\n");
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return -ENODEV;
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}
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pcc_ss_data = pcc_data[pcc_ss_id];
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down_write(&pcc_ss_data->pcc_lock);
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if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0)
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ret = cpc_read(cpu, reg, val);
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else
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ret = -EIO;
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up_write(&pcc_ss_data->pcc_lock);
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return ret;
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}
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static int cppc_get_reg_val(int cpu, enum cppc_regs reg_idx, u64 *val)
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{
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struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
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struct cpc_register_resource *reg;
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if (val == NULL)
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return -EINVAL;
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if (!cpc_desc) {
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pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
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pr_debug("No CPC descriptor for CPU:%d\n", cpu);
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return -ENODEV;
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}
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reg = &cpc_desc->cpc_regs[reg_idx];
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if (CPC_IN_PCC(reg)) {
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int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
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struct cppc_pcc_data *pcc_ss_data = NULL;
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int ret = 0;
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if (pcc_ss_id < 0)
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return -EIO;
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pcc_ss_data = pcc_data[pcc_ss_id];
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down_write(&pcc_ss_data->pcc_lock);
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if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0)
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cpc_read(cpunum, reg, perf);
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else
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ret = -EIO;
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up_write(&pcc_ss_data->pcc_lock);
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return ret;
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if ((reg->type == ACPI_TYPE_INTEGER && IS_OPTIONAL_CPC_REG(reg_idx) &&
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!reg->cpc_entry.int_value) || (reg->type != ACPI_TYPE_INTEGER &&
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IS_NULL_REG(®->cpc_entry.reg))) {
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pr_debug("CPC register is not supported\n");
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return -EOPNOTSUPP;
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}
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cpc_read(cpunum, reg, perf);
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if (CPC_IN_PCC(reg))
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return cppc_get_reg_val_in_pcc(cpu, reg, val);
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return 0;
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return cpc_read(cpu, reg, val);
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}
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static int cppc_set_reg_val_in_pcc(int cpu, struct cpc_register_resource *reg, u64 val)
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{
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int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
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struct cppc_pcc_data *pcc_ss_data = NULL;
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int ret;
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if (pcc_ss_id < 0) {
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pr_debug("Invalid pcc_ss_id\n");
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return -ENODEV;
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}
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ret = cpc_write(cpu, reg, val);
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if (ret)
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return ret;
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pcc_ss_data = pcc_data[pcc_ss_id];
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down_write(&pcc_ss_data->pcc_lock);
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/* after writing CPC, transfer the ownership of PCC to platform */
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ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
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up_write(&pcc_ss_data->pcc_lock);
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return ret;
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}
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static int cppc_set_reg_val(int cpu, enum cppc_regs reg_idx, u64 val)
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{
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struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
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struct cpc_register_resource *reg;
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if (!cpc_desc) {
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pr_debug("No CPC descriptor for CPU:%d\n", cpu);
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return -ENODEV;
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}
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reg = &cpc_desc->cpc_regs[reg_idx];
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/* if a register is writeable, it must be a buffer and not null */
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if ((reg->type != ACPI_TYPE_BUFFER) || IS_NULL_REG(®->cpc_entry.reg)) {
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pr_debug("CPC register is not supported\n");
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return -EOPNOTSUPP;
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}
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if (CPC_IN_PCC(reg))
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return cppc_set_reg_val_in_pcc(cpu, reg, val);
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return cpc_write(cpu, reg, val);
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}
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/**
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@ -1223,7 +1290,7 @@ static int cppc_get_perf(int cpunum, enum cppc_regs reg_idx, u64 *perf)
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*/
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int cppc_get_desired_perf(int cpunum, u64 *desired_perf)
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{
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return cppc_get_perf(cpunum, DESIRED_PERF, desired_perf);
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return cppc_get_reg_val(cpunum, DESIRED_PERF, desired_perf);
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}
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EXPORT_SYMBOL_GPL(cppc_get_desired_perf);
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@ -1236,7 +1303,7 @@ EXPORT_SYMBOL_GPL(cppc_get_desired_perf);
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*/
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int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf)
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{
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return cppc_get_perf(cpunum, NOMINAL_PERF, nominal_perf);
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return cppc_get_reg_val(cpunum, NOMINAL_PERF, nominal_perf);
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}
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/**
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@ -1248,7 +1315,7 @@ int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf)
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*/
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int cppc_get_highest_perf(int cpunum, u64 *highest_perf)
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{
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return cppc_get_perf(cpunum, HIGHEST_PERF, highest_perf);
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return cppc_get_reg_val(cpunum, HIGHEST_PERF, highest_perf);
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}
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EXPORT_SYMBOL_GPL(cppc_get_highest_perf);
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@ -1261,7 +1328,7 @@ EXPORT_SYMBOL_GPL(cppc_get_highest_perf);
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*/
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int cppc_get_epp_perf(int cpunum, u64 *epp_perf)
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{
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return cppc_get_perf(cpunum, ENERGY_PERF, epp_perf);
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return cppc_get_reg_val(cpunum, ENERGY_PERF, epp_perf);
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}
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EXPORT_SYMBOL_GPL(cppc_get_epp_perf);
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|
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@ -1535,53 +1602,110 @@ int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, bool enable)
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EXPORT_SYMBOL_GPL(cppc_set_epp_perf);
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|
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/**
|
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* cppc_get_auto_sel_caps - Read autonomous selection register.
|
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* @cpunum : CPU from which to read register.
|
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* @perf_caps : struct where autonomous selection register value is updated.
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* cppc_set_epp() - Write the EPP register.
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* @cpu: CPU on which to write register.
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* @epp_val: Value to write to the EPP register.
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*/
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int cppc_get_auto_sel_caps(int cpunum, struct cppc_perf_caps *perf_caps)
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int cppc_set_epp(int cpu, u64 epp_val)
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{
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struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
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struct cpc_register_resource *auto_sel_reg;
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u64 auto_sel;
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if (epp_val > CPPC_ENERGY_PERF_MAX)
|
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return -EINVAL;
|
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|
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if (!cpc_desc) {
|
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pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
|
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return -ENODEV;
|
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}
|
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return cppc_set_reg_val(cpu, ENERGY_PERF, epp_val);
|
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}
|
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EXPORT_SYMBOL_GPL(cppc_set_epp);
|
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|
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auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE];
|
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/**
|
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* cppc_get_auto_act_window() - Read autonomous activity window register.
|
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* @cpu: CPU from which to read register.
|
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* @auto_act_window: Return address.
|
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*
|
||||
* According to ACPI 6.5, s8.4.6.1.6, the value read from the autonomous
|
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* activity window register consists of two parts: a 7 bits value indicate
|
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* significand and a 3 bits value indicate exponent.
|
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*/
|
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int cppc_get_auto_act_window(int cpu, u64 *auto_act_window)
|
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{
|
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unsigned int exp;
|
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u64 val, sig;
|
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int ret;
|
||||
|
||||
if (!CPC_SUPPORTED(auto_sel_reg))
|
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pr_warn_once("Autonomous mode is not unsupported!\n");
|
||||
|
||||
if (CPC_IN_PCC(auto_sel_reg)) {
|
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int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
|
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struct cppc_pcc_data *pcc_ss_data = NULL;
|
||||
int ret = 0;
|
||||
|
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if (pcc_ss_id < 0)
|
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return -ENODEV;
|
||||
|
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pcc_ss_data = pcc_data[pcc_ss_id];
|
||||
|
||||
down_write(&pcc_ss_data->pcc_lock);
|
||||
|
||||
if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0) {
|
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cpc_read(cpunum, auto_sel_reg, &auto_sel);
|
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perf_caps->auto_sel = (bool)auto_sel;
|
||||
} else {
|
||||
ret = -EIO;
|
||||
}
|
||||
|
||||
up_write(&pcc_ss_data->pcc_lock);
|
||||
if (auto_act_window == NULL)
|
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return -EINVAL;
|
||||
|
||||
ret = cppc_get_reg_val(cpu, AUTO_ACT_WINDOW, &val);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
sig = val & CPPC_AUTO_ACT_WINDOW_MAX_SIG;
|
||||
exp = (val >> CPPC_AUTO_ACT_WINDOW_SIG_BIT_SIZE) & CPPC_AUTO_ACT_WINDOW_MAX_EXP;
|
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*auto_act_window = sig * int_pow(10, exp);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(cppc_get_auto_sel_caps);
|
||||
EXPORT_SYMBOL_GPL(cppc_get_auto_act_window);
|
||||
|
||||
/**
|
||||
* cppc_set_auto_act_window() - Write autonomous activity window register.
|
||||
* @cpu: CPU on which to write register.
|
||||
* @auto_act_window: usec value to write to the autonomous activity window register.
|
||||
*
|
||||
* According to ACPI 6.5, s8.4.6.1.6, the value to write to the autonomous
|
||||
* activity window register consists of two parts: a 7 bits value indicate
|
||||
* significand and a 3 bits value indicate exponent.
|
||||
*/
|
||||
int cppc_set_auto_act_window(int cpu, u64 auto_act_window)
|
||||
{
|
||||
/* The max value to store is 1270000000 */
|
||||
u64 max_val = CPPC_AUTO_ACT_WINDOW_MAX_SIG * int_pow(10, CPPC_AUTO_ACT_WINDOW_MAX_EXP);
|
||||
int exp = 0;
|
||||
u64 val;
|
||||
|
||||
if (auto_act_window > max_val)
|
||||
return -EINVAL;
|
||||
|
||||
/*
|
||||
* The max significand is 127, when auto_act_window is larger than
|
||||
* 129, discard the precision of the last digit and increase the
|
||||
* exponent by 1.
|
||||
*/
|
||||
while (auto_act_window > CPPC_AUTO_ACT_WINDOW_SIG_CARRY_THRESH) {
|
||||
auto_act_window /= 10;
|
||||
exp += 1;
|
||||
}
|
||||
|
||||
/* For 128 and 129, cut it to 127. */
|
||||
if (auto_act_window > CPPC_AUTO_ACT_WINDOW_MAX_SIG)
|
||||
auto_act_window = CPPC_AUTO_ACT_WINDOW_MAX_SIG;
|
||||
|
||||
val = (exp << CPPC_AUTO_ACT_WINDOW_SIG_BIT_SIZE) + auto_act_window;
|
||||
|
||||
return cppc_set_reg_val(cpu, AUTO_ACT_WINDOW, val);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(cppc_set_auto_act_window);
|
||||
|
||||
/**
|
||||
* cppc_get_auto_sel() - Read autonomous selection register.
|
||||
* @cpu: CPU from which to read register.
|
||||
* @enable: Return address.
|
||||
*/
|
||||
int cppc_get_auto_sel(int cpu, bool *enable)
|
||||
{
|
||||
u64 auto_sel;
|
||||
int ret;
|
||||
|
||||
if (enable == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
ret = cppc_get_reg_val(cpu, AUTO_SEL_ENABLE, &auto_sel);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
*enable = (bool)auto_sel;
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(cppc_get_auto_sel);
|
||||
|
||||
/**
|
||||
* cppc_set_auto_sel - Write autonomous selection register.
|
||||
|
|
@ -1590,43 +1714,7 @@ EXPORT_SYMBOL_GPL(cppc_get_auto_sel_caps);
|
|||
*/
|
||||
int cppc_set_auto_sel(int cpu, bool enable)
|
||||
{
|
||||
int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
|
||||
struct cpc_register_resource *auto_sel_reg;
|
||||
struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
|
||||
struct cppc_pcc_data *pcc_ss_data = NULL;
|
||||
int ret = -EINVAL;
|
||||
|
||||
if (!cpc_desc) {
|
||||
pr_debug("No CPC descriptor for CPU:%d\n", cpu);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE];
|
||||
|
||||
if (CPC_IN_PCC(auto_sel_reg)) {
|
||||
if (pcc_ss_id < 0) {
|
||||
pr_debug("Invalid pcc_ss_id\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
if (CPC_SUPPORTED(auto_sel_reg)) {
|
||||
ret = cpc_write(cpu, auto_sel_reg, enable);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
pcc_ss_data = pcc_data[pcc_ss_id];
|
||||
|
||||
down_write(&pcc_ss_data->pcc_lock);
|
||||
/* after writing CPC, transfer the ownership of PCC to platform */
|
||||
ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
|
||||
up_write(&pcc_ss_data->pcc_lock);
|
||||
} else {
|
||||
ret = -ENOTSUPP;
|
||||
pr_debug("_CPC in PCC is not supported\n");
|
||||
}
|
||||
|
||||
return ret;
|
||||
return cppc_set_reg_val(cpu, AUTO_SEL_ENABLE, enable);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(cppc_set_auto_sel);
|
||||
|
||||
|
|
@ -1640,38 +1728,7 @@ EXPORT_SYMBOL_GPL(cppc_set_auto_sel);
|
|||
*/
|
||||
int cppc_set_enable(int cpu, bool enable)
|
||||
{
|
||||
int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
|
||||
struct cpc_register_resource *enable_reg;
|
||||
struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
|
||||
struct cppc_pcc_data *pcc_ss_data = NULL;
|
||||
int ret = -EINVAL;
|
||||
|
||||
if (!cpc_desc) {
|
||||
pr_debug("No CPC descriptor for CPU:%d\n", cpu);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
enable_reg = &cpc_desc->cpc_regs[ENABLE];
|
||||
|
||||
if (CPC_IN_PCC(enable_reg)) {
|
||||
|
||||
if (pcc_ss_id < 0)
|
||||
return -EIO;
|
||||
|
||||
ret = cpc_write(cpu, enable_reg, enable);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
pcc_ss_data = pcc_data[pcc_ss_id];
|
||||
|
||||
down_write(&pcc_ss_data->pcc_lock);
|
||||
/* after writing CPC, transfer the ownership of PCC to platfrom */
|
||||
ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
|
||||
up_write(&pcc_ss_data->pcc_lock);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return cpc_write(cpu, enable_reg, enable);
|
||||
return cppc_set_reg_val(cpu, ENABLE, enable);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(cppc_set_enable);
|
||||
|
||||
|
|
|
|||
|
|
@ -461,10 +461,8 @@ static int acpi_processor_power_verify(struct acpi_processor *pr)
|
|||
|
||||
static int acpi_processor_get_cstate_info(struct acpi_processor *pr)
|
||||
{
|
||||
unsigned int i;
|
||||
int result;
|
||||
|
||||
|
||||
/* NOTE: the idle thread may not be running while calling
|
||||
* this function */
|
||||
|
||||
|
|
@ -481,17 +479,7 @@ static int acpi_processor_get_cstate_info(struct acpi_processor *pr)
|
|||
acpi_processor_get_power_info_default(pr);
|
||||
|
||||
pr->power.count = acpi_processor_power_verify(pr);
|
||||
|
||||
/*
|
||||
* if one state of type C2 or C3 is available, mark this
|
||||
* CPU as being "idle manageable"
|
||||
*/
|
||||
for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) {
|
||||
if (pr->power.states[i].valid) {
|
||||
pr->power.count = i;
|
||||
pr->flags.power = 1;
|
||||
}
|
||||
}
|
||||
pr->flags.power = 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -417,6 +417,7 @@ static int shmem_init_perf(struct amd_cpudata *cpudata)
|
|||
struct cppc_perf_caps cppc_perf;
|
||||
union perf_cached perf = READ_ONCE(cpudata->perf);
|
||||
u64 numerator;
|
||||
bool auto_sel;
|
||||
|
||||
int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf);
|
||||
if (ret)
|
||||
|
|
@ -438,7 +439,7 @@ static int shmem_init_perf(struct amd_cpudata *cpudata)
|
|||
if (cppc_state == AMD_PSTATE_ACTIVE)
|
||||
return 0;
|
||||
|
||||
ret = cppc_get_auto_sel_caps(cpudata->cpu, &cppc_perf);
|
||||
ret = cppc_get_auto_sel(cpudata->cpu, &auto_sel);
|
||||
if (ret) {
|
||||
pr_warn("failed to get auto_sel, ret: %d\n", ret);
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -32,6 +32,15 @@
|
|||
#define CMD_READ 0
|
||||
#define CMD_WRITE 1
|
||||
|
||||
#define CPPC_AUTO_ACT_WINDOW_SIG_BIT_SIZE (7)
|
||||
#define CPPC_AUTO_ACT_WINDOW_EXP_BIT_SIZE (3)
|
||||
#define CPPC_AUTO_ACT_WINDOW_MAX_SIG ((1 << CPPC_AUTO_ACT_WINDOW_SIG_BIT_SIZE) - 1)
|
||||
#define CPPC_AUTO_ACT_WINDOW_MAX_EXP ((1 << CPPC_AUTO_ACT_WINDOW_EXP_BIT_SIZE) - 1)
|
||||
/* CPPC_AUTO_ACT_WINDOW_MAX_SIG is 127, so 128 and 129 will decay to 127 when writing */
|
||||
#define CPPC_AUTO_ACT_WINDOW_SIG_CARRY_THRESH 129
|
||||
|
||||
#define CPPC_ENERGY_PERF_MAX (0xFF)
|
||||
|
||||
/* Each register has the folowing format. */
|
||||
struct cpc_reg {
|
||||
u8 descriptor;
|
||||
|
|
@ -159,7 +168,10 @@ extern int cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val);
|
|||
extern int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val);
|
||||
extern int cppc_get_epp_perf(int cpunum, u64 *epp_perf);
|
||||
extern int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, bool enable);
|
||||
extern int cppc_get_auto_sel_caps(int cpunum, struct cppc_perf_caps *perf_caps);
|
||||
extern int cppc_set_epp(int cpu, u64 epp_val);
|
||||
extern int cppc_get_auto_act_window(int cpu, u64 *auto_act_window);
|
||||
extern int cppc_set_auto_act_window(int cpu, u64 auto_act_window);
|
||||
extern int cppc_get_auto_sel(int cpu, bool *enable);
|
||||
extern int cppc_set_auto_sel(int cpu, bool enable);
|
||||
extern int amd_get_highest_perf(unsigned int cpu, u32 *highest_perf);
|
||||
extern int amd_get_boost_ratio_numerator(unsigned int cpu, u64 *numerator);
|
||||
|
|
@ -229,11 +241,23 @@ static inline int cppc_get_epp_perf(int cpunum, u64 *epp_perf)
|
|||
{
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
static inline int cppc_set_auto_sel(int cpu, bool enable)
|
||||
static inline int cppc_set_epp(int cpu, u64 epp_val)
|
||||
{
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
static inline int cppc_get_auto_sel_caps(int cpunum, struct cppc_perf_caps *perf_caps)
|
||||
static inline int cppc_get_auto_act_window(int cpu, u64 *auto_act_window)
|
||||
{
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
static inline int cppc_set_auto_act_window(int cpu, u64 auto_act_window)
|
||||
{
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
static inline int cppc_get_auto_sel(int cpu, bool *enable)
|
||||
{
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
static inline int cppc_set_auto_sel(int cpu, bool enable)
|
||||
{
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user