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Merge branch 'v6.6/standard/base' into v6.6/standard/fsl-mpc8315e-rdb

Browse Source
This commit is contained in:
Bruce Ashfield 2025-12-09 09:57:26 -05:00
commit 1338f63360
196 changed files with 913 additions and 28086 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
MAINTAINERS
View File

@ -20403,12 +20403,6 @@ S: Maintained
W: http://wiki.laptop.org/go/DCON
F: drivers/staging/olpc_dcon/
STAGING - REALTEK RTL8712U DRIVERS
M: Larry Finger <Larry.Finger@lwfinger.net>
M: Florian Schilhabel <florian.c.schilhabel@googlemail.com>.
S: Odd Fixes
F: drivers/staging/rtl8712/
STAGING - SEPS525 LCD CONTROLLER DRIVERS
M: Michael Hennerich <michael.hennerich@analog.com>
L: linux-fbdev@vger.kernel.org

2
Makefile
View File

@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
VERSION = 6
PATCHLEVEL = 6
SUBLEVEL = 118
SUBLEVEL = 119
EXTRAVERSION =
NAME = Pinguïn Aangedreven

2
arch/arm/boot/dts/nxp/imx/imx6ul.dtsi
View File

@ -333,7 +333,7 @@
#sound-dai-cells = <0>;
compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
reg = <0x02030000 0x4000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
<&clks IMX6UL_CLK_SAI3>,
<&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;

118
arch/mips/mm/tlb-r4k.c
View File

@ -12,9 +12,11 @@
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/smp.h>
#include <linux/memblock.h>
#include <linux/mm.h>
#include <linux/hugetlb.h>
#include <linux/export.h>
#include <linux/sort.h>
#include <asm/cpu.h>
#include <asm/cpu-type.h>
@ -506,58 +508,95 @@ static int __init set_ntlb(char *str)
__setup("ntlb=", set_ntlb);
/* Initialise all TLB entries with unique values */
static void r4k_tlb_uniquify(void)
/* Comparison function for EntryHi VPN fields. */
static int r4k_vpn_cmp(const void *a, const void *b)
{
int entry = num_wired_entries();
long v = *(unsigned long *)a - *(unsigned long *)b;
int s = sizeof(long) > sizeof(int) ? sizeof(long) * 8 - 1: 0;
return s ? (v != 0) | v >> s : v;
}
/*
* Initialise all TLB entries with unique values that do not clash with
* what we have been handed over and what we'll be using ourselves.
*/
static void __ref r4k_tlb_uniquify(void)
{
int tlbsize = current_cpu_data.tlbsize;
bool use_slab = slab_is_available();
int start = num_wired_entries();
phys_addr_t tlb_vpn_size;
unsigned long *tlb_vpns;
unsigned long vpn_mask;
int cnt, ent, idx, i;
vpn_mask = GENMASK(cpu_vmbits - 1, 13);
vpn_mask |= IS_ENABLED(CONFIG_64BIT) ? 3ULL << 62 : 1 << 31;
tlb_vpn_size = tlbsize * sizeof(*tlb_vpns);
tlb_vpns = (use_slab ?
kmalloc(tlb_vpn_size, GFP_KERNEL) :
memblock_alloc_raw(tlb_vpn_size, sizeof(*tlb_vpns)));
if (WARN_ON(!tlb_vpns))
return; /* Pray local_flush_tlb_all() is good enough. */
htw_stop();
for (i = start, cnt = 0; i < tlbsize; i++, cnt++) {
unsigned long vpn;
write_c0_index(i);
mtc0_tlbr_hazard();
tlb_read();
tlb_read_hazard();
vpn = read_c0_entryhi();
vpn &= vpn_mask & PAGE_MASK;
tlb_vpns[cnt] = vpn;
/* Prevent any large pages from overlapping regular ones. */
write_c0_pagemask(read_c0_pagemask() & PM_DEFAULT_MASK);
mtc0_tlbw_hazard();
tlb_write_indexed();
tlbw_use_hazard();
}
sort(tlb_vpns, cnt, sizeof(tlb_vpns[0]), r4k_vpn_cmp, NULL);
write_c0_pagemask(PM_DEFAULT_MASK);
write_c0_entrylo0(0);
write_c0_entrylo1(0);
while (entry < current_cpu_data.tlbsize) {
unsigned long asid_mask = cpu_asid_mask(&current_cpu_data);
unsigned long asid = 0;
int idx;
idx = 0;
ent = tlbsize;
for (i = start; i < tlbsize; i++)
while (1) {
unsigned long entryhi, vpn;
/* Skip wired MMID to make ginvt_mmid work */
if (cpu_has_mmid)
asid = MMID_KERNEL_WIRED + 1;
entryhi = UNIQUE_ENTRYHI(ent);
vpn = entryhi & vpn_mask & PAGE_MASK;
/* Check for match before using UNIQUE_ENTRYHI */
do {
if (cpu_has_mmid) {
write_c0_memorymapid(asid);
write_c0_entryhi(UNIQUE_ENTRYHI(entry));
} else {
write_c0_entryhi(UNIQUE_ENTRYHI(entry) | asid);
}
mtc0_tlbw_hazard();
tlb_probe();
tlb_probe_hazard();
idx = read_c0_index();
/* No match or match is on current entry */
if (idx < 0 || idx == entry)
if (idx >= cnt || vpn < tlb_vpns[idx]) {
write_c0_entryhi(entryhi);
write_c0_index(i);
mtc0_tlbw_hazard();
tlb_write_indexed();
ent++;
break;
/*
* If we hit a match, we need to try again with
* a different ASID.
*/
asid++;
} while (asid < asid_mask);
if (idx >= 0 && idx != entry)
panic("Unable to uniquify TLB entry %d", idx);
write_c0_index(entry);
mtc0_tlbw_hazard();
tlb_write_indexed();
entry++;
}
} else if (vpn == tlb_vpns[idx]) {
ent++;
} else {
idx++;
}
}
tlbw_use_hazard();
htw_start();
flush_micro_tlb();
if (use_slab)
kfree(tlb_vpns);
else
memblock_free(tlb_vpns, tlb_vpn_size);
}
/*
@ -600,6 +639,7 @@ static void r4k_tlb_configure(void)
/* From this point on the ARC firmware is dead. */
r4k_tlb_uniquify();
local_flush_tlb_all();
/* Did I tell you that ARC SUCKS? */
}

10
arch/x86/events/core.c
View File

@ -2769,13 +2769,13 @@ perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *re
return;
}
if (perf_callchain_store(entry, regs->ip))
return;
if (perf_hw_regs(regs))
if (perf_hw_regs(regs)) {
if (perf_callchain_store(entry, regs->ip))
return;
unwind_start(&state, current, regs, NULL);
else
} else {
unwind_start(&state, current, NULL, (void *)regs->sp);
}
for (; !unwind_done(&state); unwind_next_frame(&state)) {
addr = unwind_get_return_address(&state);

2
drivers/atm/fore200e.c
View File

@ -1377,7 +1377,9 @@ fore200e_open(struct atm_vcc *vcc)
vcc->dev_data = NULL;
mutex_lock(&fore200e->rate_mtx);
fore200e->available_cell_rate += vcc->qos.txtp.max_pcr;
mutex_unlock(&fore200e->rate_mtx);
kfree(fore200e_vcc);
return -EINVAL;

7
drivers/firmware/stratix10-svc.c
View File

@ -134,6 +134,7 @@ struct stratix10_svc_data {
* @complete_status: state for completion
* @svc_fifo_lock: protect access to service message data queue
* @invoke_fn: function to issue secure monitor call or hypervisor call
* @svc: manages the list of client svc drivers
*
* This struct is used to create communication channels for service clients, to
* handle secure monitor or hypervisor call.
@ -150,6 +151,7 @@ struct stratix10_svc_controller {
struct completion complete_status;
spinlock_t svc_fifo_lock;
svc_invoke_fn *invoke_fn;
struct stratix10_svc *svc;
};
/**
@ -1209,6 +1211,7 @@ static int stratix10_svc_drv_probe(struct platform_device *pdev)
ret = -ENOMEM;
goto err_free_kfifo;
}
controller->svc = svc;
svc->stratix10_svc_rsu = platform_device_alloc(STRATIX10_RSU, 0);
if (!svc->stratix10_svc_rsu) {
@ -1236,8 +1239,6 @@ static int stratix10_svc_drv_probe(struct platform_device *pdev)
goto err_unregister_dev;
}
dev_set_drvdata(dev, svc);
pr_info("Intel Service Layer Driver Initialized\n");
return 0;
@ -1253,8 +1254,8 @@ err_destroy_pool:
static int stratix10_svc_drv_remove(struct platform_device *pdev)
{
struct stratix10_svc *svc = dev_get_drvdata(&pdev->dev);
struct stratix10_svc_controller *ctrl = platform_get_drvdata(pdev);
struct stratix10_svc *svc = ctrl->svc;
platform_device_unregister(svc->intel_svc_fcs);
platform_device_unregister(svc->stratix10_svc_rsu);

2
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
View File

@ -1941,6 +1941,8 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
chip_name = "navi12";
break;
case CHIP_CYAN_SKILLFISH:
if (adev->mman.discovery_bin)
return 0;
chip_name = "cyan_skillfish";
break;
}

11
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
View File

@ -634,9 +634,14 @@ bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,
{
uint8_t i;
bool ret = false;
struct dc *dc = stream->ctx->dc;
struct resource_context *res_ctx =
&dc->current_state->res_ctx;
struct dc *dc;
struct resource_context *res_ctx;
if (!stream->ctx)
return false;
dc = stream->ctx->dc;
res_ctx = &dc->current_state->res_ctx;
for (i = 0; i < MAX_PIPES; i++) {
struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg;

7
drivers/gpu/drm/sti/sti_vtg.c
View File

@ -143,12 +143,17 @@ struct sti_vtg {
struct sti_vtg *of_vtg_find(struct device_node *np)
{
struct platform_device *pdev;
struct sti_vtg *vtg;
pdev = of_find_device_by_node(np);
if (!pdev)
return NULL;
return (struct sti_vtg *)platform_get_drvdata(pdev);
vtg = platform_get_drvdata(pdev);
put_device(&pdev->dev);
return vtg;
}
static void vtg_reset(struct sti_vtg *vtg)

7
drivers/hid/hid-core.c
View File

@ -1351,7 +1351,12 @@ EXPORT_SYMBOL_GPL(hid_snto32);
static u32 s32ton(__s32 value, unsigned n)
{
s32 a = value >> (n - 1);
s32 a;
if (!value || !n)
return 0;
a = value >> (n - 1);
if (a && a != -1)
return value < 0 ? 1 << (n - 1) : (1 << (n - 1)) - 1;
return value & ((1 << n) - 1);

44
drivers/iio/accel/adxl355_core.c
View File

@ -56,6 +56,8 @@
#define ADXL355_POWER_CTL_DRDY_MSK BIT(2)
#define ADXL355_SELF_TEST_REG 0x2E
#define ADXL355_RESET_REG 0x2F
#define ADXL355_BASE_ADDR_SHADOW_REG 0x50
#define ADXL355_SHADOW_REG_COUNT 5
#define ADXL355_DEVID_AD_VAL 0xAD
#define ADXL355_DEVID_MST_VAL 0x1D
@ -294,7 +296,12 @@ static void adxl355_fill_3db_frequency_table(struct adxl355_data *data)
static int adxl355_setup(struct adxl355_data *data)
{
unsigned int regval;
int retries = 5; /* the number is chosen based on empirical reasons */
int ret;
u8 *shadow_regs __free(kfree) = kzalloc(ADXL355_SHADOW_REG_COUNT, GFP_KERNEL);
if (!shadow_regs)
return -ENOMEM;
ret = regmap_read(data->regmap, ADXL355_DEVID_AD_REG, &regval);
if (ret)
@ -321,14 +328,41 @@ static int adxl355_setup(struct adxl355_data *data)
if (regval != ADXL355_PARTID_VAL)
dev_warn(data->dev, "Invalid DEV ID 0x%02x\n", regval);
/*
* Perform a software reset to make sure the device is in a consistent
* state after start-up.
*/
ret = regmap_write(data->regmap, ADXL355_RESET_REG, ADXL355_RESET_CODE);
/* Read shadow registers to be compared after reset */
ret = regmap_bulk_read(data->regmap,
ADXL355_BASE_ADDR_SHADOW_REG,
shadow_regs, ADXL355_SHADOW_REG_COUNT);
if (ret)
return ret;
do {
if (--retries == 0) {
dev_err(data->dev, "Shadow registers mismatch\n");
return -EIO;
}
/*
* Perform a software reset to make sure the device is in a consistent
* state after start-up.
*/
ret = regmap_write(data->regmap, ADXL355_RESET_REG,
ADXL355_RESET_CODE);
if (ret)
return ret;
/* Wait at least 5ms after software reset */
usleep_range(5000, 10000);
/* Read shadow registers for comparison */
ret = regmap_bulk_read(data->regmap,
ADXL355_BASE_ADDR_SHADOW_REG,
data->buffer.buf,
ADXL355_SHADOW_REG_COUNT);
if (ret)
return ret;
} while (memcmp(shadow_regs, data->buffer.buf,
ADXL355_SHADOW_REG_COUNT));
ret = regmap_update_bits(data->regmap, ADXL355_POWER_CTL_REG,
ADXL355_POWER_CTL_DRDY_MSK,
FIELD_PREP(ADXL355_POWER_CTL_DRDY_MSK, 1));

5
drivers/iio/accel/bmc150-accel-core.c
View File

@ -569,6 +569,10 @@ static int bmc150_accel_set_interrupt(struct bmc150_accel_data *data, int i,
const struct bmc150_accel_interrupt_info *info = intr->info;
int ret;
/* We do not always have an IRQ */
if (data->irq <= 0)
return 0;
if (state) {
if (atomic_inc_return(&intr->users) > 1)
return 0;
@ -1743,6 +1747,7 @@ int bmc150_accel_core_probe(struct device *dev, struct regmap *regmap, int irq,
}
if (irq > 0) {
data->irq = irq;
ret = devm_request_threaded_irq(dev, irq,
bmc150_accel_irq_handler,
bmc150_accel_irq_thread_handler,

1
drivers/iio/accel/bmc150-accel.h
View File

@ -57,6 +57,7 @@ enum bmc150_accel_trigger_id {
struct bmc150_accel_data {
struct regmap *regmap;
int irq;
struct regulator_bulk_data regulators[2];
struct bmc150_accel_interrupt interrupts[BMC150_ACCEL_INTERRUPTS];
struct bmc150_accel_trigger triggers[BMC150_ACCEL_TRIGGERS];

2
drivers/iio/adc/ad7280a.c
View File

@ -540,7 +540,7 @@ static ssize_t ad7280_store_balance_timer(struct iio_dev *indio_dev,
int val, val2;
int ret;
ret = iio_str_to_fixpoint(buf, 1000, &val, &val2);
ret = iio_str_to_fixpoint(buf, 100, &val, &val2);
if (ret)
return ret;

2
drivers/iio/adc/rtq6056.c
View File

@ -171,7 +171,7 @@ static int rtq6056_adc_read_channel(struct rtq6056_priv *priv,
if (addr == RTQ6056_REG_BUSVOLT || addr == RTQ6056_REG_POWER)
*val = regval;
else
*val = sign_extend32(regval, 16);
*val = sign_extend32(regval, 15);
return IIO_VAL_INT;
}

4
drivers/iio/common/ssp_sensors/ssp_dev.c
View File

@ -503,7 +503,7 @@ static int ssp_probe(struct spi_device *spi)
ret = spi_setup(spi);
if (ret < 0) {
dev_err(&spi->dev, "Failed to setup spi\n");
return ret;
goto err_setup_spi;
}
data->fw_dl_state = SSP_FW_DL_STATE_NONE;
@ -568,6 +568,8 @@ err_read_reg:
err_setup_irq:
mutex_destroy(&data->pending_lock);
mutex_destroy(&data->comm_lock);
err_setup_spi:
mfd_remove_devices(&spi->dev);
dev_err(&spi->dev, "Probe failed!\n");

40
drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h
View File

@ -190,6 +190,22 @@ struct st_lsm6dsx_fifo_ops {
* @fifo_en: Hw timer FIFO enable register info (addr + mask).
* @decimator: Hw timer FIFO decimator register info (addr + mask).
* @freq_fine: Difference in % of ODR with respect to the typical.
* @ts_sensitivity: Nominal timestamp sensitivity.
* @ts_trim_coeff: Coefficient for calculating the calibrated timestamp gain.
* This coefficient comes into play when linearizing the formula
* used to calculate the calibrated timestamp (please see the
* relevant formula in the AN for the specific IMU).
* For example, in the case of LSM6DSO we have:
*
* 1 / (1 + x) ~= 1 - x (Taylor’s Series)
* ttrim[s] = 1 / (40000 * (1 + 0.0015 * val)) (from AN5192)
* ttrim[ns] ~= 25000 - 37.5 * val
* ttrim[ns] ~= 25000 - (37500 * val) / 1000
*
* so, replacing ts_sensitivity = 25000 and
* ts_trim_coeff = 37500
*
* ttrim[ns] ~= ts_sensitivity - (ts_trim_coeff * val) / 1000
*/
struct st_lsm6dsx_hw_ts_settings {
struct st_lsm6dsx_reg timer_en;
@ -197,6 +213,8 @@ struct st_lsm6dsx_hw_ts_settings {
struct st_lsm6dsx_reg fifo_en;
struct st_lsm6dsx_reg decimator;
u8 freq_fine;
u16 ts_sensitivity;
u16 ts_trim_coeff;
};
/**
@ -250,6 +268,15 @@ struct st_lsm6dsx_event_settings {
u8 wakeup_src_x_mask;
};
enum st_lsm6dsx_sensor_id {
ST_LSM6DSX_ID_GYRO,
ST_LSM6DSX_ID_ACC,
ST_LSM6DSX_ID_EXT0,
ST_LSM6DSX_ID_EXT1,
ST_LSM6DSX_ID_EXT2,
ST_LSM6DSX_ID_MAX
};
enum st_lsm6dsx_ext_sensor_id {
ST_LSM6DSX_ID_MAGN,
};
@ -335,23 +362,14 @@ struct st_lsm6dsx_settings {
struct st_lsm6dsx_odr_table_entry odr_table[2];
struct st_lsm6dsx_samples_to_discard samples_to_discard[2];
struct st_lsm6dsx_fs_table_entry fs_table[2];
struct st_lsm6dsx_reg decimator[ST_LSM6DSX_MAX_ID];
struct st_lsm6dsx_reg batch[ST_LSM6DSX_MAX_ID];
struct st_lsm6dsx_reg decimator[ST_LSM6DSX_ID_MAX];
struct st_lsm6dsx_reg batch[2];
struct st_lsm6dsx_fifo_ops fifo_ops;
struct st_lsm6dsx_hw_ts_settings ts_settings;
struct st_lsm6dsx_shub_settings shub_settings;
struct st_lsm6dsx_event_settings event_settings;
};
enum st_lsm6dsx_sensor_id {
ST_LSM6DSX_ID_GYRO,
ST_LSM6DSX_ID_ACC,
ST_LSM6DSX_ID_EXT0,
ST_LSM6DSX_ID_EXT1,
ST_LSM6DSX_ID_EXT2,
ST_LSM6DSX_ID_MAX,
};
enum st_lsm6dsx_fifo_mode {
ST_LSM6DSX_FIFO_BYPASS = 0x0,
ST_LSM6DSX_FIFO_CONT = 0x6,

19
drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c
View File

@ -77,8 +77,6 @@
#define ST_LSM6DSX_REG_WHOAMI_ADDR 0x0f
#define ST_LSM6DSX_TS_SENSITIVITY 25000UL /* 25us */
static const struct iio_chan_spec st_lsm6dsx_acc_channels[] = {
ST_LSM6DSX_CHANNEL_ACC(IIO_ACCEL, 0x28, IIO_MOD_X, 0),
ST_LSM6DSX_CHANNEL_ACC(IIO_ACCEL, 0x2a, IIO_MOD_Y, 1),
@ -962,6 +960,8 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
.mask = GENMASK(7, 6),
},
.freq_fine = 0x63,
.ts_sensitivity = 25000,
.ts_trim_coeff = 37500,
},
.shub_settings = {
.page_mux = {
@ -1175,6 +1175,8 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
.mask = GENMASK(7, 6),
},
.freq_fine = 0x63,
.ts_sensitivity = 25000,
.ts_trim_coeff = 37500,
},
.event_settings = {
.enable_reg = {
@ -1350,6 +1352,8 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
.mask = GENMASK(7, 6),
},
.freq_fine = 0x4f,
.ts_sensitivity = 21701,
.ts_trim_coeff = 28212,
},
.shub_settings = {
.page_mux = {
@ -2243,20 +2247,13 @@ static int st_lsm6dsx_init_hw_timer(struct st_lsm6dsx_hw *hw)
}
/* calibrate timestamp sensitivity */
hw->ts_gain = ST_LSM6DSX_TS_SENSITIVITY;
hw->ts_gain = ts_settings->ts_sensitivity;
if (ts_settings->freq_fine) {
err = regmap_read(hw->regmap, ts_settings->freq_fine, &val);
if (err < 0)
return err;
/*
* linearize the AN5192 formula:
* 1 / (1 + x) ~= 1 - x (Taylor’s Series)
* ttrim[s] = 1 / (40000 * (1 + 0.0015 * val))
* ttrim[ns] ~= 25000 - 37.5 * val
* ttrim[ns] ~= 25000 - (37500 * val) / 1000
*/
hw->ts_gain -= ((s8)val * 37500) / 1000;
hw->ts_gain -= ((s8)val * ts_settings->ts_trim_coeff) / 1000;
}
return 0;

2
drivers/mailbox/mailbox-test.c
View File

@ -268,7 +268,7 @@ static int mbox_test_add_debugfs(struct platform_device *pdev,
return 0;
tdev->root_debugfs_dir = debugfs_create_dir(dev_name(&pdev->dev), NULL);
if (!tdev->root_debugfs_dir) {
if (IS_ERR(tdev->root_debugfs_dir)) {
dev_err(&pdev->dev, "Failed to create Mailbox debugfs\n");
return -EINVAL;
}

32
drivers/mailbox/pcc.c
View File

@ -269,6 +269,24 @@ static bool pcc_mbox_cmd_complete_check(struct pcc_chan_info *pchan)
return !!val;
}
static int pcc_mbox_error_check_and_clear(struct pcc_chan_info *pchan)
{
u64 val;
int ret;
ret = pcc_chan_reg_read(&pchan->error, &val);
if (ret)
return ret;
if (val & pchan->error.status_mask) {
val &= pchan->error.preserve_mask;
pcc_chan_reg_write(&pchan->error, val);
return -EIO;
}
return 0;
}
static void check_and_ack(struct pcc_chan_info *pchan, struct mbox_chan *chan)
{
struct acpi_pcct_ext_pcc_shared_memory pcc_hdr;
@ -309,8 +327,6 @@ static irqreturn_t pcc_mbox_irq(int irq, void *p)
{
struct pcc_chan_info *pchan;
struct mbox_chan *chan = p;
u64 val;
int ret;
pchan = chan->con_priv;
@ -324,15 +340,8 @@ static irqreturn_t pcc_mbox_irq(int irq, void *p)
if (!pcc_mbox_cmd_complete_check(pchan))
return IRQ_NONE;
ret = pcc_chan_reg_read(&pchan->error, &val);
if (ret)
if (pcc_mbox_error_check_and_clear(pchan))
return IRQ_NONE;
val &= pchan->error.status_mask;
if (val) {
val &= ~pchan->error.status_mask;
pcc_chan_reg_write(&pchan->error, val);
return IRQ_NONE;
}
/*
* Clear this flag after updating interrupt ack register and just
@ -663,7 +672,8 @@ static int pcc_parse_subspace_db_reg(struct pcc_chan_info *pchan,
ret = pcc_chan_reg_init(&pchan->error,
&pcct_ext->error_status_register,
0, 0, pcct_ext->error_status_mask,
~pcct_ext->error_status_mask, 0,
pcct_ext->error_status_mask,
"Error Status");
}
return ret;

6
drivers/md/dm-verity-fec.c
View File

@ -330,11 +330,7 @@ static int fec_alloc_bufs(struct dm_verity *v, struct dm_verity_fec_io *fio)
if (fio->bufs[n])
continue;
fio->bufs[n] = mempool_alloc(&v->fec->prealloc_pool, GFP_NOWAIT);
if (unlikely(!fio->bufs[n])) {
DMERR("failed to allocate FEC buffer");
return -ENOMEM;
}
fio->bufs[n] = mempool_alloc(&v->fec->prealloc_pool, GFP_NOIO);
}
/* try to allocate the maximum number of buffers */

14
drivers/most/most_usb.c
View File

@ -1058,7 +1058,7 @@ hdm_probe(struct usb_interface *interface, const struct usb_device_id *id)
ret = most_register_interface(&mdev->iface);
if (ret)
goto err_free_busy_urbs;
return ret;
mutex_lock(&mdev->io_mutex);
if (le16_to_cpu(usb_dev->descriptor.idProduct) == USB_DEV_ID_OS81118 ||
@ -1068,8 +1068,7 @@ hdm_probe(struct usb_interface *interface, const struct usb_device_id *id)
if (!mdev->dci) {
mutex_unlock(&mdev->io_mutex);
most_deregister_interface(&mdev->iface);
ret = -ENOMEM;
goto err_free_busy_urbs;
return -ENOMEM;
}
mdev->dci->dev.init_name = "dci";
@ -1078,18 +1077,15 @@ hdm_probe(struct usb_interface *interface, const struct usb_device_id *id)
mdev->dci->dev.release = release_dci;
if (device_register(&mdev->dci->dev)) {
mutex_unlock(&mdev->io_mutex);
put_device(&mdev->dci->dev);
most_deregister_interface(&mdev->iface);
ret = -ENOMEM;
goto err_free_dci;
return -ENOMEM;
}
mdev->dci->usb_device = mdev->usb_device;
}
mutex_unlock(&mdev->io_mutex);
return 0;
err_free_dci:
put_device(&mdev->dci->dev);
err_free_busy_urbs:
kfree(mdev->busy_urbs);
err_free_ep_address:
kfree(mdev->ep_address);
err_free_cap:

2
drivers/mtd/nand/spi/core.c
View File

@ -1044,6 +1044,8 @@ spinand_select_op_variant(struct spinand_device *spinand,
if (ret)
break;
spi_mem_adjust_op_freq(spinand->spimem, &op);
if (!spi_mem_supports_op(spinand->spimem, &op))
break;

11
drivers/net/bonding/bond_main.c
View File

@ -322,9 +322,9 @@ static bool bond_sk_check(struct bonding *bond)
}
}
static bool bond_xdp_check(struct bonding *bond)
bool bond_xdp_check(struct bonding *bond, int mode)
{
switch (BOND_MODE(bond)) {
switch (mode) {
case BOND_MODE_ROUNDROBIN:
case BOND_MODE_ACTIVEBACKUP:
return true;
@ -1855,7 +1855,7 @@ void bond_xdp_set_features(struct net_device *bond_dev)
ASSERT_RTNL();
if (!bond_xdp_check(bond) || !bond_has_slaves(bond)) {
if (!bond_xdp_check(bond, BOND_MODE(bond)) || !bond_has_slaves(bond)) {
xdp_clear_features_flag(bond_dev);
return;
}
@ -5622,8 +5622,11 @@ static int bond_xdp_set(struct net_device *dev, struct bpf_prog *prog,
ASSERT_RTNL();
if (!bond_xdp_check(bond))
if (!bond_xdp_check(bond, BOND_MODE(bond))) {
BOND_NL_ERR(dev, extack,
"No native XDP support for the current bonding mode");
return -EOPNOTSUPP;
}
old_prog = bond->xdp_prog;
bond->xdp_prog = prog;

3
drivers/net/bonding/bond_options.c
View File

@ -868,6 +868,9 @@ static bool bond_set_xfrm_features(struct bonding *bond)
static int bond_option_mode_set(struct bonding *bond,
const struct bond_opt_value *newval)
{
if (bond->xdp_prog && !bond_xdp_check(bond, newval->value))
return -EOPNOTSUPP;
if (!bond_mode_uses_arp(newval->value)) {
if (bond->params.arp_interval) {
netdev_dbg(bond->dev, "%s mode is incompatible with arp monitoring, start mii monitoring\n",

53
drivers/net/can/rcar/rcar_canfd.c
View File

@ -687,26 +687,6 @@ static void rcar_canfd_tx_failure_cleanup(struct net_device *ndev)
can_free_echo_skb(ndev, i, NULL);
}
static void rcar_canfd_set_mode(struct rcar_canfd_global *gpriv)
{
if (is_gen4(gpriv)) {
u32 ch, val = gpriv->fdmode ? RCANFD_GEN4_FDCFG_FDOE
: RCANFD_GEN4_FDCFG_CLOE;
for_each_set_bit(ch, &gpriv->channels_mask,
gpriv->info->max_channels)
rcar_canfd_set_bit(gpriv->base, RCANFD_GEN4_FDCFG(ch),
val);
} else {
if (gpriv->fdmode)
rcar_canfd_set_bit(gpriv->base, RCANFD_GRMCFG,
RCANFD_GRMCFG_RCMC);
else
rcar_canfd_clear_bit(gpriv->base, RCANFD_GRMCFG,
RCANFD_GRMCFG_RCMC);
}
}
static int rcar_canfd_reset_controller(struct rcar_canfd_global *gpriv)
{
u32 sts, ch;
@ -738,6 +718,16 @@ static int rcar_canfd_reset_controller(struct rcar_canfd_global *gpriv)
/* Reset Global error flags */
rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0x0);
/* Set the controller into appropriate mode */
if (!is_gen4(gpriv)) {
if (gpriv->fdmode)
rcar_canfd_set_bit(gpriv->base, RCANFD_GRMCFG,
RCANFD_GRMCFG_RCMC);
else
rcar_canfd_clear_bit(gpriv->base, RCANFD_GRMCFG,
RCANFD_GRMCFG_RCMC);
}
/* Transition all Channels to reset mode */
for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
rcar_canfd_clear_bit(gpriv->base,
@ -756,10 +746,27 @@ static int rcar_canfd_reset_controller(struct rcar_canfd_global *gpriv)
"channel %u reset failed\n", ch);
return err;
}
}
/* Set the controller into appropriate mode */
rcar_canfd_set_mode(gpriv);
/* Set the controller into appropriate mode */
if (is_gen4(gpriv)) {
/* Do not set CLOE and FDOE simultaneously */
if (!gpriv->fdmode) {
rcar_canfd_clear_bit(gpriv->base,
RCANFD_GEN4_FDCFG(ch),
RCANFD_GEN4_FDCFG_FDOE);
rcar_canfd_set_bit(gpriv->base,
RCANFD_GEN4_FDCFG(ch),
RCANFD_GEN4_FDCFG_CLOE);
} else {
rcar_canfd_clear_bit(gpriv->base,
RCANFD_GEN4_FDCFG(ch),
RCANFD_GEN4_FDCFG_FDOE);
rcar_canfd_clear_bit(gpriv->base,
RCANFD_GEN4_FDCFG(ch),
RCANFD_GEN4_FDCFG_CLOE);
}
}
}
return 0;
}

4
drivers/net/can/sja1000/sja1000.c
View File

@ -548,8 +548,8 @@ irqreturn_t sja1000_interrupt(int irq, void *dev_id)
if (priv->read_reg(priv, SJA1000_IER) == IRQ_OFF)
goto out;
while ((isrc = priv->read_reg(priv, SJA1000_IR)) &&
(n < SJA1000_MAX_IRQ)) {
while ((n < SJA1000_MAX_IRQ) &&
(isrc = priv->read_reg(priv, SJA1000_IR))) {
status = priv->read_reg(priv, SJA1000_SR);
/* check for absent controller due to hw unplug */

4
drivers/net/can/sun4i_can.c
View File

@ -657,8 +657,8 @@ static irqreturn_t sun4i_can_interrupt(int irq, void *dev_id)
u8 isrc, status;
int n = 0;
while ((isrc = readl(priv->base + SUN4I_REG_INT_ADDR)) &&
(n < SUN4I_CAN_MAX_IRQ)) {
while ((n < SUN4I_CAN_MAX_IRQ) &&
(isrc = readl(priv->base + SUN4I_REG_INT_ADDR))) {
n++;
status = readl(priv->base + SUN4I_REG_STA_ADDR);

102
drivers/net/can/usb/gs_usb.c
View File

@ -258,14 +258,21 @@ struct canfd_quirk {
u8 quirk;
} __packed;
struct gs_host_frame {
u32 echo_id;
__le32 can_id;
/* struct gs_host_frame::echo_id == GS_HOST_FRAME_ECHO_ID_RX indicates
* a regular RX'ed CAN frame
*/
#define GS_HOST_FRAME_ECHO_ID_RX 0xffffffff
u8 can_dlc;
u8 channel;
u8 flags;
u8 reserved;
struct gs_host_frame {
struct_group(header,
u32 echo_id;
__le32 can_id;
u8 can_dlc;
u8 channel;
u8 flags;
u8 reserved;
);
union {
DECLARE_FLEX_ARRAY(struct classic_can, classic_can);
@ -565,6 +572,37 @@ gs_usb_get_echo_skb(struct gs_can *dev, struct sk_buff *skb,
return len;
}
static unsigned int
gs_usb_get_minimum_rx_length(const struct gs_can *dev, const struct gs_host_frame *hf,
unsigned int *data_length_p)
{
unsigned int minimum_length, data_length = 0;
if (hf->flags & GS_CAN_FLAG_FD) {
if (hf->echo_id == GS_HOST_FRAME_ECHO_ID_RX)
data_length = can_fd_dlc2len(hf->can_dlc);
if (dev->feature & GS_CAN_FEATURE_HW_TIMESTAMP)
/* timestamp follows data field of max size */
minimum_length = struct_size(hf, canfd_ts, 1);
else
minimum_length = sizeof(hf->header) + data_length;
} else {
if (hf->echo_id == GS_HOST_FRAME_ECHO_ID_RX &&
!(hf->can_id & cpu_to_le32(CAN_RTR_FLAG)))
data_length = can_cc_dlc2len(hf->can_dlc);
if (dev->feature & GS_CAN_FEATURE_HW_TIMESTAMP)
/* timestamp follows data field of max size */
minimum_length = struct_size(hf, classic_can_ts, 1);
else
minimum_length = sizeof(hf->header) + data_length;
}
*data_length_p = data_length;
return minimum_length;
}
static void gs_usb_receive_bulk_callback(struct urb *urb)
{
struct gs_usb *parent = urb->context;
@ -573,6 +611,7 @@ static void gs_usb_receive_bulk_callback(struct urb *urb)
int rc;
struct net_device_stats *stats;
struct gs_host_frame *hf = urb->transfer_buffer;
unsigned int minimum_length, data_length;
struct gs_tx_context *txc;
struct can_frame *cf;
struct canfd_frame *cfd;
@ -591,6 +630,15 @@ static void gs_usb_receive_bulk_callback(struct urb *urb)
return;
}
minimum_length = sizeof(hf->header);
if (urb->actual_length < minimum_length) {
dev_err_ratelimited(&parent->udev->dev,
"short read (actual_length=%u, minimum_length=%u)\n",
urb->actual_length, minimum_length);
goto resubmit_urb;
}
/* device reports out of range channel id */
if (hf->channel >= parent->channel_cnt)
goto device_detach;
@ -606,20 +654,33 @@ static void gs_usb_receive_bulk_callback(struct urb *urb)
if (!netif_running(netdev))
goto resubmit_urb;
if (hf->echo_id == -1) { /* normal rx */
minimum_length = gs_usb_get_minimum_rx_length(dev, hf, &data_length);
if (urb->actual_length < minimum_length) {
stats->rx_errors++;
stats->rx_length_errors++;
if (net_ratelimit())
netdev_err(netdev,
"short read (actual_length=%u, minimum_length=%u)\n",
urb->actual_length, minimum_length);
goto resubmit_urb;
}
if (hf->echo_id == GS_HOST_FRAME_ECHO_ID_RX) { /* normal rx */
if (hf->flags & GS_CAN_FLAG_FD) {
skb = alloc_canfd_skb(netdev, &cfd);
if (!skb)
return;
cfd->can_id = le32_to_cpu(hf->can_id);
cfd->len = can_fd_dlc2len(hf->can_dlc);
cfd->len = data_length;
if (hf->flags & GS_CAN_FLAG_BRS)
cfd->flags |= CANFD_BRS;
if (hf->flags & GS_CAN_FLAG_ESI)
cfd->flags |= CANFD_ESI;
memcpy(cfd->data, hf->canfd->data, cfd->len);
memcpy(cfd->data, hf->canfd->data, data_length);
} else {
skb = alloc_can_skb(netdev, &cf);
if (!skb)
@ -628,7 +689,7 @@ static void gs_usb_receive_bulk_callback(struct urb *urb)
cf->can_id = le32_to_cpu(hf->can_id);
can_frame_set_cc_len(cf, hf->can_dlc, dev->can.ctrlmode);
memcpy(cf->data, hf->classic_can->data, 8);
memcpy(cf->data, hf->classic_can->data, data_length);
/* ERROR frames tell us information about the controller */
if (le32_to_cpu(hf->can_id) & CAN_ERR_FLAG)
@ -684,7 +745,7 @@ static void gs_usb_receive_bulk_callback(struct urb *urb)
resubmit_urb:
usb_fill_bulk_urb(urb, parent->udev,
parent->pipe_in,
hf, dev->parent->hf_size_rx,
hf, parent->hf_size_rx,
gs_usb_receive_bulk_callback, parent);
rc = usb_submit_urb(urb, GFP_ATOMIC);
@ -747,8 +808,21 @@ static void gs_usb_xmit_callback(struct urb *urb)
struct gs_can *dev = txc->dev;
struct net_device *netdev = dev->netdev;
if (urb->status)
netdev_info(netdev, "usb xmit fail %u\n", txc->echo_id);
if (!urb->status)
return;
if (urb->status != -ESHUTDOWN && net_ratelimit())
netdev_info(netdev, "failed to xmit URB %u: %pe\n",
txc->echo_id, ERR_PTR(urb->status));
netdev->stats.tx_dropped++;
netdev->stats.tx_errors++;
can_free_echo_skb(netdev, txc->echo_id, NULL);
gs_free_tx_context(txc);
atomic_dec(&dev->active_tx_urbs);
netif_wake_queue(netdev);
}
static netdev_tx_t gs_can_start_xmit(struct sk_buff *skb,

4
drivers/net/can/usb/kvaser_usb/kvaser_usb_leaf.c
View File

@ -611,7 +611,7 @@ static int kvaser_usb_leaf_wait_cmd(const struct kvaser_usb *dev, u8 id,
* for further details.
*/
if (tmp->len == 0) {
pos = round_up(pos,
pos = round_up(pos + 1,
le16_to_cpu
(dev->bulk_in->wMaxPacketSize));
continue;
@ -1590,7 +1590,7 @@ static void kvaser_usb_leaf_read_bulk_callback(struct kvaser_usb *dev,
* number of events in case of a heavy rx load on the bus.
*/
if (cmd->len == 0) {
pos = round_up(pos, le16_to_cpu
pos = round_up(pos + 1, le16_to_cpu
(dev->bulk_in->wMaxPacketSize));
continue;
}

30
drivers/net/dsa/microchip/ksz_common.c
View File

@ -1870,8 +1870,8 @@ static int ksz_irq_phy_setup(struct ksz_device *dev)
if (BIT(phy) & ds->phys_mii_mask) {
irq = irq_find_mapping(dev->ports[phy].pirq.domain,
PORT_SRC_PHY_INT);
if (irq < 0) {
ret = irq;
if (!irq) {
ret = -EINVAL;
goto out;
}
ds->slave_mii_bus->irq[phy] = irq;
@ -2095,8 +2095,8 @@ static int ksz_pirq_setup(struct ksz_device *dev, u8 p)
snprintf(pirq->name, sizeof(pirq->name), "port_irq-%d", p);
pirq->irq_num = irq_find_mapping(dev->girq.domain, p);
if (pirq->irq_num < 0)
return pirq->irq_num;
if (!pirq->irq_num)
return -EINVAL;
return ksz_irq_common_setup(dev, pirq);
}
@ -2163,18 +2163,18 @@ static int ksz_setup(struct dsa_switch *ds)
dsa_switch_for_each_user_port(dp, dev->ds) {
ret = ksz_pirq_setup(dev, dp->index);
if (ret)
goto out_girq;
goto port_release;
ret = ksz_ptp_irq_setup(ds, dp->index);
if (ret)
goto out_pirq;
goto pirq_release;
}
}
ret = ksz_ptp_clock_register(ds);
if (ret) {
dev_err(dev->dev, "Failed to register PTP clock: %d\n", ret);
goto out_ptpirq;
goto port_release;
}
ret = ksz_mdio_register(dev);
@ -2191,17 +2191,17 @@ static int ksz_setup(struct dsa_switch *ds)
out_ptp_clock_unregister:
ksz_ptp_clock_unregister(ds);
out_ptpirq:
if (dev->irq > 0)
dsa_switch_for_each_user_port(dp, dev->ds)
port_release:
if (dev->irq > 0) {
dsa_switch_for_each_port_continue_reverse(dp, dev->ds) {
if (!dsa_port_is_user(dp))
continue;
ksz_ptp_irq_free(ds, dp->index);
out_pirq:
if (dev->irq > 0)
dsa_switch_for_each_user_port(dp, dev->ds)
pirq_release:
ksz_irq_free(&dev->ports[dp->index].pirq);
out_girq:
if (dev->irq > 0)
}
ksz_irq_free(&dev->girq);
}
return ret;
}

22
drivers/net/dsa/microchip/ksz_ptp.c
View File

@ -1099,19 +1099,19 @@ static int ksz_ptp_msg_irq_setup(struct ksz_port *port, u8 n)
static const char * const name[] = {"pdresp-msg", "xdreq-msg",
"sync-msg"};
const struct ksz_dev_ops *ops = port->ksz_dev->dev_ops;
struct ksz_irq *ptpirq = &port->ptpirq;
struct ksz_ptp_irq *ptpmsg_irq;
ptpmsg_irq = &port->ptpmsg_irq[n];
ptpmsg_irq->num = irq_create_mapping(ptpirq->domain, n);
if (!ptpmsg_irq->num)
return -EINVAL;
ptpmsg_irq->port = port;
ptpmsg_irq->ts_reg = ops->get_port_addr(port->num, ts_reg[n]);
snprintf(ptpmsg_irq->name, sizeof(ptpmsg_irq->name), name[n]);
ptpmsg_irq->num = irq_find_mapping(port->ptpirq.domain, n);
if (ptpmsg_irq->num < 0)
return ptpmsg_irq->num;
return request_threaded_irq(ptpmsg_irq->num, NULL,
ksz_ptp_msg_thread_fn, IRQF_ONESHOT,
ptpmsg_irq->name, ptpmsg_irq);
@ -1141,12 +1141,9 @@ int ksz_ptp_irq_setup(struct dsa_switch *ds, u8 p)
if (!ptpirq->domain)
return -ENOMEM;
for (irq = 0; irq < ptpirq->nirqs; irq++)
irq_create_mapping(ptpirq->domain, irq);
ptpirq->irq_num = irq_find_mapping(port->pirq.domain, PORT_SRC_PTP_INT);
if (ptpirq->irq_num < 0) {
ret = ptpirq->irq_num;
if (!ptpirq->irq_num) {
ret = -EINVAL;
goto out;
}
@ -1165,12 +1162,11 @@ int ksz_ptp_irq_setup(struct dsa_switch *ds, u8 p)
out_ptp_msg:
free_irq(ptpirq->irq_num, ptpirq);
while (irq--)
while (irq--) {
free_irq(port->ptpmsg_irq[irq].num, &port->ptpmsg_irq[irq]);
out:
for (irq = 0; irq < ptpirq->nirqs; irq++)
irq_dispose_mapping(port->ptpmsg_irq[irq].num);
}
out:
irq_domain_remove(ptpirq->domain);
return ret;

66
drivers/net/dsa/sja1105/sja1105_main.c
View File

@ -1261,29 +1261,11 @@ static int sja1105_parse_dt(struct sja1105_private *priv)
return rc;
}
/* Convert link speed from SJA1105 to ethtool encoding */
static int sja1105_port_speed_to_ethtool(struct sja1105_private *priv,
u64 speed)
{
if (speed == priv->info->port_speed[SJA1105_SPEED_10MBPS])
return SPEED_10;
if (speed == priv->info->port_speed[SJA1105_SPEED_100MBPS])
return SPEED_100;
if (speed == priv->info->port_speed[SJA1105_SPEED_1000MBPS])
return SPEED_1000;
if (speed == priv->info->port_speed[SJA1105_SPEED_2500MBPS])
return SPEED_2500;
return SPEED_UNKNOWN;
}
/* Set link speed in the MAC configuration for a specific port. */
static int sja1105_adjust_port_config(struct sja1105_private *priv, int port,
int speed_mbps)
static int sja1105_set_port_speed(struct sja1105_private *priv, int port,
int speed_mbps)
{
struct sja1105_mac_config_entry *mac;
struct device *dev = priv->ds->dev;
u64 speed;
int rc;
/* On P/Q/R/S, one can read from the device via the MAC reconfiguration
* tables. On E/T, MAC reconfig tables are not readable, only writable.
@ -1317,7 +1299,7 @@ static int sja1105_adjust_port_config(struct sja1105_private *priv, int port,
speed = priv->info->port_speed[SJA1105_SPEED_2500MBPS];
break;
default:
dev_err(dev, "Invalid speed %iMbps\n", speed_mbps);
dev_err(priv->ds->dev, "Invalid speed %iMbps\n", speed_mbps);
return -EINVAL;
}
@ -1325,15 +1307,28 @@ static int sja1105_adjust_port_config(struct sja1105_private *priv, int port,
* table, since this will be used for the clocking setup, and we no
* longer need to store it in the static config (already told hardware
* we want auto during upload phase).
* Actually for the SGMII port, the MAC is fixed at 1 Gbps and
* we need to configure the PCS only (if even that).
*/
if (priv->phy_mode[port] == PHY_INTERFACE_MODE_SGMII)
mac[port].speed = priv->info->port_speed[SJA1105_SPEED_1000MBPS];
else if (priv->phy_mode[port] == PHY_INTERFACE_MODE_2500BASEX)
mac[port].speed = priv->info->port_speed[SJA1105_SPEED_2500MBPS];
else
mac[port].speed = speed;
mac[port].speed = speed;
return 0;
}
/* Write the MAC Configuration Table entry and, if necessary, the CGU settings,
* after a link speedchange for this port.
*/
static int sja1105_set_port_config(struct sja1105_private *priv, int port)
{
struct sja1105_mac_config_entry *mac;
struct device *dev = priv->ds->dev;
int rc;
/* On P/Q/R/S, one can read from the device via the MAC reconfiguration
* tables. On E/T, MAC reconfig tables are not readable, only writable.
* We have to *know* what the MAC looks like. For the sake of keeping
* the code common, we'll use the static configuration tables as a
* reasonable approximation for both E/T and P/Q/R/S.
*/
mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
/* Write to the dynamic reconfiguration tables */
rc = sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
@ -1383,7 +1378,8 @@ static void sja1105_mac_link_up(struct dsa_switch *ds, int port,
{
struct sja1105_private *priv = ds->priv;
sja1105_adjust_port_config(priv, port, speed);
if (!sja1105_set_port_speed(priv, port, speed))
sja1105_set_port_config(priv, port);
sja1105_inhibit_tx(priv, BIT(port), false);
}
@ -2284,8 +2280,8 @@ int sja1105_static_config_reload(struct sja1105_private *priv,
{
struct ptp_system_timestamp ptp_sts_before;
struct ptp_system_timestamp ptp_sts_after;
int speed_mbps[SJA1105_MAX_NUM_PORTS];
u16 bmcr[SJA1105_MAX_NUM_PORTS] = {0};
u64 mac_speed[SJA1105_MAX_NUM_PORTS];
struct sja1105_mac_config_entry *mac;
struct dsa_switch *ds = priv->ds;
s64 t1, t2, t3, t4;
@ -2298,14 +2294,13 @@ int sja1105_static_config_reload(struct sja1105_private *priv,
mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
/* Back up the dynamic link speed changed by sja1105_adjust_port_config
/* Back up the dynamic link speed changed by sja1105_set_port_speed()
* in order to temporarily restore it to SJA1105_SPEED_AUTO - which the
* switch wants to see in the static config in order to allow us to
* change it through the dynamic interface later.
*/
for (i = 0; i < ds->num_ports; i++) {
speed_mbps[i] = sja1105_port_speed_to_ethtool(priv,
mac[i].speed);
mac_speed[i] = mac[i].speed;
mac[i].speed = priv->info->port_speed[SJA1105_SPEED_AUTO];
if (priv->xpcs[i])
@ -2368,7 +2363,8 @@ int sja1105_static_config_reload(struct sja1105_private *priv,
struct dw_xpcs *xpcs = priv->xpcs[i];
unsigned int neg_mode;
rc = sja1105_adjust_port_config(priv, i, speed_mbps[i]);
mac[i].speed = mac_speed[i];
rc = sja1105_set_port_config(priv, i);
if (rc < 0)
goto out;

22
drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.c
View File

@ -15,6 +15,7 @@
#include "aq_hw.h"
#include "aq_nic.h"
#include "hw_atl/hw_atl_llh.h"
void aq_hw_write_reg_bit(struct aq_hw_s *aq_hw, u32 addr, u32 msk,
u32 shift, u32 val)
@ -81,6 +82,27 @@ void aq_hw_write_reg64(struct aq_hw_s *hw, u32 reg, u64 value)
lo_hi_writeq(value, hw->mmio + reg);
}
int aq_hw_invalidate_descriptor_cache(struct aq_hw_s *hw)
{
int err;
u32 val;
/* Invalidate Descriptor Cache to prevent writing to the cached
* descriptors and to the data pointer of those descriptors
*/
hw_atl_rdm_rx_dma_desc_cache_init_tgl(hw);
err = aq_hw_err_from_flags(hw);
if (err)
goto err_exit;
readx_poll_timeout_atomic(hw_atl_rdm_rx_dma_desc_cache_init_done_get,
hw, val, val == 1, 1000U, 10000U);
err_exit:
return err;
}
int aq_hw_err_from_flags(struct aq_hw_s *hw)
{
int err = 0;

1
drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.h
View File

@ -35,6 +35,7 @@ u32 aq_hw_read_reg(struct aq_hw_s *hw, u32 reg);
void aq_hw_write_reg(struct aq_hw_s *hw, u32 reg, u32 value);
u64 aq_hw_read_reg64(struct aq_hw_s *hw, u32 reg);
void aq_hw_write_reg64(struct aq_hw_s *hw, u32 reg, u64 value);
int aq_hw_invalidate_descriptor_cache(struct aq_hw_s *hw);
int aq_hw_err_from_flags(struct aq_hw_s *hw);
int aq_hw_num_tcs(struct aq_hw_s *hw);
int aq_hw_q_per_tc(struct aq_hw_s *hw);

5
drivers/net/ethernet/aquantia/atlantic/aq_ring.c
View File

@ -547,6 +547,11 @@ static int __aq_ring_rx_clean(struct aq_ring_s *self, struct napi_struct *napi,
if (!buff->is_eop) {
unsigned int frag_cnt = 0U;
/* There will be an extra fragment */
if (buff->len > AQ_CFG_RX_HDR_SIZE)
frag_cnt++;
buff_ = buff;
do {
bool is_rsc_completed = true;

19
drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c
View File

@ -1198,26 +1198,9 @@ static int hw_atl_b0_hw_interrupt_moderation_set(struct aq_hw_s *self)
static int hw_atl_b0_hw_stop(struct aq_hw_s *self)
{
int err;
u32 val;
hw_atl_b0_hw_irq_disable(self, HW_ATL_B0_INT_MASK);
/* Invalidate Descriptor Cache to prevent writing to the cached
* descriptors and to the data pointer of those descriptors
*/
hw_atl_rdm_rx_dma_desc_cache_init_tgl(self);
err = aq_hw_err_from_flags(self);
if (err)
goto err_exit;
readx_poll_timeout_atomic(hw_atl_rdm_rx_dma_desc_cache_init_done_get,
self, val, val == 1, 1000U, 10000U);
err_exit:
return err;
return aq_hw_invalidate_descriptor_cache(self);
}
int hw_atl_b0_hw_ring_tx_stop(struct aq_hw_s *self, struct aq_ring_s *ring)

2
drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2.c
View File

@ -759,7 +759,7 @@ static int hw_atl2_hw_stop(struct aq_hw_s *self)
{
hw_atl_b0_hw_irq_disable(self, HW_ATL2_INT_MASK);
return 0;
return aq_hw_invalidate_descriptor_cache(self);
}
static struct aq_stats_s *hw_atl2_utils_get_hw_stats(struct aq_hw_s *self)

2
drivers/net/ethernet/cadence/macb_main.c
View File

@ -5182,11 +5182,11 @@ static int macb_remove(struct platform_device *pdev)
if (dev) {
bp = netdev_priv(dev);
unregister_netdev(dev);
phy_exit(bp->sgmii_phy);
mdiobus_unregister(bp->mii_bus);
mdiobus_free(bp->mii_bus);
unregister_netdev(dev);
tasklet_kill(&bp->hresp_err_tasklet);
pm_runtime_disable(&pdev->dev);
pm_runtime_dont_use_autosuspend(&pdev->dev);

1
drivers/net/ethernet/freescale/fec.h
View File

@ -683,6 +683,7 @@ struct fec_enet_private {
unsigned int reload_period;
int pps_enable;
unsigned int next_counter;
bool perout_enable;
struct hrtimer perout_timer;
u64 perout_stime;

64
drivers/net/ethernet/freescale/fec_ptp.c
View File

@ -129,6 +129,12 @@ static int fec_ptp_enable_pps(struct fec_enet_private *fep, uint enable)
spin_lock_irqsave(&fep->tmreg_lock, flags);
if (fep->perout_enable) {
spin_unlock_irqrestore(&fep->tmreg_lock, flags);
dev_err(&fep->pdev->dev, "PEROUT is running");
return -EBUSY;
}
if (fep->pps_enable == enable) {
spin_unlock_irqrestore(&fep->tmreg_lock, flags);
return 0;
@ -244,6 +250,7 @@ static int fec_ptp_pps_perout(struct fec_enet_private *fep)
* the FEC_TCCR register in time and missed the start time.
*/
if (fep->perout_stime < curr_time + 100 * NSEC_PER_MSEC) {
fep->perout_enable = false;
dev_err(&fep->pdev->dev, "Current time is too close to the start time!\n");
spin_unlock_irqrestore(&fep->tmreg_lock, flags);
return -1;
@ -498,7 +505,10 @@ static int fec_ptp_pps_disable(struct fec_enet_private *fep, uint channel)
{
unsigned long flags;
hrtimer_cancel(&fep->perout_timer);
spin_lock_irqsave(&fep->tmreg_lock, flags);
fep->perout_enable = false;
writel(0, fep->hwp + FEC_TCSR(channel));
spin_unlock_irqrestore(&fep->tmreg_lock, flags);
@ -530,6 +540,8 @@ static int fec_ptp_enable(struct ptp_clock_info *ptp,
return ret;
} else if (rq->type == PTP_CLK_REQ_PEROUT) {
u32 reload_period;
/* Reject requests with unsupported flags */
if (rq->perout.flags)
return -EOPNOTSUPP;
@ -549,12 +561,14 @@ static int fec_ptp_enable(struct ptp_clock_info *ptp,
return -EOPNOTSUPP;
}
fep->reload_period = div_u64(period_ns, 2);
if (on && fep->reload_period) {
reload_period = div_u64(period_ns, 2);
if (on && reload_period) {
u64 perout_stime;
/* Convert 1588 timestamp to ns*/
start_time.tv_sec = rq->perout.start.sec;
start_time.tv_nsec = rq->perout.start.nsec;
fep->perout_stime = timespec64_to_ns(&start_time);
perout_stime = timespec64_to_ns(&start_time);
mutex_lock(&fep->ptp_clk_mutex);
if (!fep->ptp_clk_on) {
@ -563,18 +577,41 @@ static int fec_ptp_enable(struct ptp_clock_info *ptp,
return -EOPNOTSUPP;
}
spin_lock_irqsave(&fep->tmreg_lock, flags);
if (fep->pps_enable) {
dev_err(&fep->pdev->dev, "PPS is running");
ret = -EBUSY;
goto unlock;
}
if (fep->perout_enable) {
dev_err(&fep->pdev->dev,
"PEROUT has been enabled\n");
ret = -EBUSY;
goto unlock;
}
/* Read current timestamp */
curr_time = timecounter_read(&fep->tc);
if (perout_stime <= curr_time) {
dev_err(&fep->pdev->dev,
"Start time must be greater than current time\n");
ret = -EINVAL;
goto unlock;
}
/* Calculate time difference */
delta = perout_stime - curr_time;
fep->reload_period = reload_period;
fep->perout_stime = perout_stime;
fep->perout_enable = true;
unlock:
spin_unlock_irqrestore(&fep->tmreg_lock, flags);
mutex_unlock(&fep->ptp_clk_mutex);
/* Calculate time difference */
delta = fep->perout_stime - curr_time;
if (fep->perout_stime <= curr_time) {
dev_err(&fep->pdev->dev, "Start time must larger than current time!\n");
return -EINVAL;
}
if (ret)
return ret;
/* Because the timer counter of FEC only has 31-bits, correspondingly,
* the time comparison register FEC_TCCR also only low 31 bits can be
@ -682,8 +719,11 @@ static irqreturn_t fec_pps_interrupt(int irq, void *dev_id)
fep->next_counter = (fep->next_counter + fep->reload_period) &
fep->cc.mask;
event.type = PTP_CLOCK_PPS;
ptp_clock_event(fep->ptp_clock, &event);
if (fep->pps_enable) {
event.type = PTP_CLOCK_PPS;
ptp_clock_event(fep->ptp_clock, &event);
}
return IRQ_HANDLED;
}

2
drivers/net/ethernet/mellanox/mlx5/core/en_dcbnl.c
View File

@ -619,7 +619,7 @@ static int mlx5e_dcbnl_ieee_setmaxrate(struct net_device *netdev,
MLX5E_100MB);
max_bw_value[i] = max_bw_value[i] ? max_bw_value[i] : 1;
max_bw_unit[i] = MLX5_100_MBPS_UNIT;
} else if (max_bw_value[i] <= upper_limit_gbps) {
} else if (maxrate->tc_maxrate[i] <= upper_limit_gbps) {
max_bw_value[i] = div_u64(maxrate->tc_maxrate[i],
MLX5E_1GB);
max_bw_unit[i] = MLX5_GBPS_UNIT;

5
drivers/net/ethernet/microchip/lan966x/lan966x_ptp.c
View File

@ -1,11 +1,14 @@
// SPDX-License-Identifier: GPL-2.0+
#include <linux/ptp_classify.h>
#include <linux/units.h>
#include "lan966x_main.h"
#include "vcap_api.h"
#include "vcap_api_client.h"
#define LAN9X66_CLOCK_RATE 165617754
#define LAN966X_MAX_PTP_ID 512
/* Represents 1ppm adjustment in 2^59 format with 6.037735849ns as reference
@ -1132,5 +1135,5 @@ void lan966x_ptp_rxtstamp(struct lan966x *lan966x, struct sk_buff *skb,
u32 lan966x_ptp_get_period_ps(void)
{
/* This represents the system clock period in picoseconds */
return 15125;
return PICO / LAN9X66_CLOCK_RATE;
}

4
drivers/net/ethernet/samsung/sxgbe/sxgbe_main.c
View File

@ -1521,8 +1521,10 @@ static int sxgbe_rx(struct sxgbe_priv_data *priv, int limit)
skb = priv->rxq[qnum]->rx_skbuff[entry];
if (unlikely(!skb))
if (unlikely(!skb)) {
netdev_err(priv->dev, "rx descriptor is not consistent\n");
break;
}
prefetch(skb->data - NET_IP_ALIGN);
priv->rxq[qnum]->rx_skbuff[entry] = NULL;

2
drivers/net/phy/mxl-gpy.c
View File

@ -515,7 +515,7 @@ static int gpy_update_interface(struct phy_device *phydev)
/* Interface mode is fixed for USXGMII and integrated PHY */
if (phydev->interface == PHY_INTERFACE_MODE_USXGMII ||
phydev->interface == PHY_INTERFACE_MODE_INTERNAL)
return -EINVAL;
return 0;
/* Automatically switch SERDES interface between SGMII and 2500-BaseX
* according to speed. Disable ANEG in 2500-BaseX mode.

2
drivers/platform/x86/intel/punit_ipc.c
View File

@ -283,7 +283,7 @@ static int intel_punit_ipc_probe(struct platform_device *pdev)
} else {
ret = devm_request_irq(&pdev->dev, irq, intel_punit_ioc,
IRQF_NO_SUSPEND, "intel_punit_ipc",
&punit_ipcdev);
punit_ipcdev);
if (ret) {
dev_err(&pdev->dev, "Failed to request irq: %d\n", irq);
return ret;

1
drivers/slimbus/qcom-ngd-ctrl.c
View File

@ -1239,6 +1239,7 @@ static void qcom_slim_ngd_notify_slaves(struct qcom_slim_ngd_ctrl *ctrl)
if (slim_get_logical_addr(sbdev))
dev_err(ctrl->dev, "Failed to get logical address\n");
put_device(&sbdev->dev);
}
}

4
drivers/spi/Kconfig
View File

@ -1059,10 +1059,10 @@ config SPI_TEGRA210_QUAD
config SPI_TEGRA114
tristate "NVIDIA Tegra114 SPI Controller"
depends on (ARCH_TEGRA && TEGRA20_APB_DMA) || COMPILE_TEST
depends on ARCH_TEGRA || COMPILE_TEST
depends on RESET_CONTROLLER
help
SPI driver for NVIDIA Tegra114 SPI Controller interface. This controller
SPI controller driver for NVIDIA Tegra114 and later SoCs. This controller
is different than the older SoCs SPI controller and also register interface
get changed with this controller.

4
drivers/spi/spi-amlogic-spifc-a1.c
View File

@ -349,7 +349,9 @@ static int amlogic_spifc_a1_probe(struct platform_device *pdev)
pm_runtime_set_autosuspend_delay(spifc->dev, 500);
pm_runtime_use_autosuspend(spifc->dev);
devm_pm_runtime_enable(spifc->dev);
ret = devm_pm_runtime_enable(spifc->dev);
if (ret)
return ret;
ctrl->num_chipselect = 1;
ctrl->dev.of_node = pdev->dev.of_node;

14
drivers/spi/spi-bcm63xx.c
View File

@ -247,6 +247,20 @@ static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first,
if (t->rx_buf) {
do_rx = true;
/*
* In certain hardware implementations, there appears to be a
* hidden accumulator that tracks the number of bytes written into
* the hardware FIFO, and this accumulator overrides the length in
* the SPI_MSG_CTL register.
*
* Therefore, for read-only transfers, we need to write some dummy
* value into the FIFO to keep the accumulator tracking the correct
* length.
*/
if (!t->tx_buf)
memset_io(bs->tx_io + len, 0xFF, t->len);
/* prepend is half-duplex write only */
if (t == first)
prepend_len = 0;

37
drivers/spi/spi-mem.c
View File

@ -172,6 +172,9 @@ bool spi_mem_default_supports_op(struct spi_mem *mem,
if (!spi_mem_controller_is_capable(ctlr, dtr))
return false;
if (op->data.swap16 && !spi_mem_controller_is_capable(ctlr, swap16))
return false;
if (op->cmd.nbytes != 2)
return false;
} else {
@ -184,6 +187,16 @@ bool spi_mem_default_supports_op(struct spi_mem *mem,
return false;
}
if (op->max_freq && mem->spi->controller->min_speed_hz &&
op->max_freq < mem->spi->controller->min_speed_hz)
return false;
if (op->max_freq &&
op->max_freq < mem->spi->max_speed_hz) {
if (!spi_mem_controller_is_capable(ctlr, per_op_freq))
return false;
}
return spi_mem_check_buswidth(mem, op);
}
EXPORT_SYMBOL_GPL(spi_mem_default_supports_op);
@ -318,6 +331,9 @@ int spi_mem_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
u8 *tmpbuf;
int ret;
/* Make sure the operation frequency is correct before going futher */
spi_mem_adjust_op_freq(mem, (struct spi_mem_op *)op);
ret = spi_mem_check_op(op);
if (ret)
return ret;
@ -360,6 +376,7 @@ int spi_mem_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
xfers[xferpos].tx_buf = tmpbuf;
xfers[xferpos].len = op->cmd.nbytes;
xfers[xferpos].tx_nbits = op->cmd.buswidth;
xfers[xferpos].speed_hz = op->max_freq;
spi_message_add_tail(&xfers[xferpos], &msg);
xferpos++;
totalxferlen++;
@ -374,6 +391,7 @@ int spi_mem_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
xfers[xferpos].tx_buf = tmpbuf + 1;
xfers[xferpos].len = op->addr.nbytes;
xfers[xferpos].tx_nbits = op->addr.buswidth;
xfers[xferpos].speed_hz = op->max_freq;
spi_message_add_tail(&xfers[xferpos], &msg);
xferpos++;
totalxferlen += op->addr.nbytes;
@ -385,6 +403,7 @@ int spi_mem_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
xfers[xferpos].len = op->dummy.nbytes;
xfers[xferpos].tx_nbits = op->dummy.buswidth;
xfers[xferpos].dummy_data = 1;
xfers[xferpos].speed_hz = op->max_freq;
spi_message_add_tail(&xfers[xferpos], &msg);
xferpos++;
totalxferlen += op->dummy.nbytes;
@ -400,6 +419,7 @@ int spi_mem_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
}
xfers[xferpos].len = op->data.nbytes;
xfers[xferpos].speed_hz = op->max_freq;
spi_message_add_tail(&xfers[xferpos], &msg);
xferpos++;
totalxferlen += op->data.nbytes;
@ -478,6 +498,23 @@ int spi_mem_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
}
EXPORT_SYMBOL_GPL(spi_mem_adjust_op_size);
/**
* spi_mem_adjust_op_freq() - Adjust the frequency of a SPI mem operation to
* match controller, PCB and chip limitations
* @mem: the SPI memory
* @op: the operation to adjust
*
* Some chips have per-op frequency limitations and must adapt the maximum
* speed. This function allows SPI mem drivers to set @op->max_freq to the
* maximum supported value.
*/
void spi_mem_adjust_op_freq(struct spi_mem *mem, struct spi_mem_op *op)
{
if (!op->max_freq || op->max_freq > mem->spi->max_speed_hz)
op->max_freq = mem->spi->max_speed_hz;
}
EXPORT_SYMBOL_GPL(spi_mem_adjust_op_freq);
static ssize_t spi_mem_no_dirmap_read(struct spi_mem_dirmap_desc *desc,
u64 offs, size_t len, void *buf)
{

22
drivers/spi/spi-nxp-fspi.c
View File

@ -711,9 +711,10 @@ static void nxp_fspi_dll_calibration(struct nxp_fspi *f)
* Value for rest of the CS FLSHxxCR0 register would be zero.
*
*/
static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi)
static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi,
const struct spi_mem_op *op)
{
unsigned long rate = spi->max_speed_hz;
unsigned long rate = op->max_freq;
int ret;
uint64_t size_kb;
@ -938,7 +939,7 @@ static int nxp_fspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
FSPI_STS0_ARB_IDLE, 1, POLL_TOUT, true);
WARN_ON(err);
nxp_fspi_select_mem(f, mem->spi);
nxp_fspi_select_mem(f, mem->spi, op);
nxp_fspi_prepare_lut(f, op);
/*
@ -1156,11 +1157,15 @@ static const struct spi_controller_mem_ops nxp_fspi_mem_ops = {
.get_name = nxp_fspi_get_name,
};
static const struct spi_controller_mem_caps nxp_fspi_mem_caps = {
.per_op_freq = true,
};
static int nxp_fspi_probe(struct platform_device *pdev)
{
struct spi_controller *ctlr;
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
struct fwnode_handle *fwnode = dev_fwnode(dev);
struct resource *res;
struct nxp_fspi *f;
int ret;
@ -1184,7 +1189,7 @@ static int nxp_fspi_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, f);
/* find the resources - configuration register address space */
if (is_acpi_node(dev_fwnode(f->dev)))
if (is_acpi_node(fwnode))
f->iobase = devm_platform_ioremap_resource(pdev, 0);
else
f->iobase = devm_platform_ioremap_resource_byname(pdev, "fspi_base");
@ -1195,7 +1200,7 @@ static int nxp_fspi_probe(struct platform_device *pdev)
}
/* find the resources - controller memory mapped space */
if (is_acpi_node(dev_fwnode(f->dev)))
if (is_acpi_node(fwnode))
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
else
res = platform_get_resource_byname(pdev,
@ -1211,7 +1216,7 @@ static int nxp_fspi_probe(struct platform_device *pdev)
f->memmap_phy_size = resource_size(res);
/* find the clocks */
if (dev_of_node(&pdev->dev)) {
if (is_of_node(fwnode)) {
f->clk_en = devm_clk_get(dev, "fspi_en");
if (IS_ERR(f->clk_en)) {
ret = PTR_ERR(f->clk_en);
@ -1253,10 +1258,11 @@ static int nxp_fspi_probe(struct platform_device *pdev)
ctlr->bus_num = -1;
ctlr->num_chipselect = NXP_FSPI_MAX_CHIPSELECT;
ctlr->mem_ops = &nxp_fspi_mem_ops;
ctlr->mem_caps = &nxp_fspi_mem_caps;
nxp_fspi_default_setup(f);
ctlr->dev.of_node = np;
device_set_node(&ctlr->dev, fwnode);
ret = devm_spi_register_controller(&pdev->dev, ctlr);
if (ret)

2
drivers/staging/Kconfig
View File

@ -34,8 +34,6 @@ source "drivers/staging/rtl8192e/Kconfig"
source "drivers/staging/rtl8723bs/Kconfig"
source "drivers/staging/rtl8712/Kconfig"
source "drivers/staging/rts5208/Kconfig"
source "drivers/staging/octeon/Kconfig"

1
drivers/staging/Makefile
View File

@ -7,7 +7,6 @@ obj-$(CONFIG_FB_OLPC_DCON) += olpc_dcon/
obj-$(CONFIG_RTL8192U) += rtl8192u/
obj-$(CONFIG_RTL8192E) += rtl8192e/
obj-$(CONFIG_RTL8723BS) += rtl8723bs/
obj-$(CONFIG_R8712U) += rtl8712/
obj-$(CONFIG_RTS5208) += rts5208/
obj-$(CONFIG_OCTEON_ETHERNET) += octeon/
obj-$(CONFIG_VT6655) += vt6655/

21
drivers/staging/rtl8712/Kconfig
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@ -1,21 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
config R8712U
tristate "RealTek RTL8712U (RTL8192SU) Wireless LAN NIC driver"
depends on WLAN && USB && CFG80211
select WIRELESS_EXT
select WEXT_PRIV
select FW_LOADER
help
This option adds the Realtek RTL8712 USB device such as the
D-Link DWA-130.
If built as a module, it will be called r8712u.
config R8712_TX_AGGR
bool "Realtek RTL8712U Transmit Aggregation code"
depends on R8712U && BROKEN
help
This option provides transmit aggregation for the Realtek
RTL8712 USB device.

35
drivers/staging/rtl8712/Makefile
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@ -1,35 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
r8712u-y := \
rtl871x_cmd.o \
rtl8712_cmd.o \
rtl871x_security.o \
rtl871x_eeprom.o \
rtl8712_efuse.o \
hal_init.o \
usb_halinit.o \
usb_ops.o \
usb_ops_linux.o \
rtl871x_io.o \
rtl8712_io.o \
rtl871x_ioctl_linux.o \
rtl871x_ioctl_rtl.o \
rtl871x_ioctl_set.o \
rtl8712_led.o \
rtl871x_mlme.o \
ieee80211.o \
rtl871x_mp_ioctl.o \
rtl871x_mp.o \
mlme_linux.o \
recv_linux.o \
xmit_linux.o \
usb_intf.o \
os_intfs.o \
rtl871x_pwrctrl.o \
rtl8712_recv.o \
rtl871x_recv.o \
rtl871x_sta_mgt.o \
rtl871x_xmit.o \
rtl8712_xmit.o
obj-$(CONFIG_R8712U) := r8712u.o

13
drivers/staging/rtl8712/TODO
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@ -1,13 +0,0 @@
TODO:
- merge Realtek's bugfixes and new features into the driver
- switch to use LIB80211
- switch to use MAC80211
- checkpatch.pl fixes - only a few remain
A replacement for this driver with MAC80211 support is available
at https://github.com/chunkeey/rtl8192su
Please send any patches to Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Larry Finger <Larry.Finger@lwfinger.net>,
Florian Schilhabel <florian.c.schilhabel@googlemail.com> and
Linux Driver Project Developer List <driverdev-devel@linuxdriverproject.org>.

28
drivers/staging/rtl8712/basic_types.h
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@ -1,28 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
*
* Modifications for inclusion into the Linux staging tree are
* Copyright(c) 2010 Larry Finger. All rights reserved.
*
* Contact information:
* WLAN FAE <wlanfae@realtek.com>
* Larry Finger <Larry.Finger@lwfinger.net>
*
******************************************************************************/
#ifndef __BASIC_TYPES_H__
#define __BASIC_TYPES_H__
#include <linux/types.h>
#define sint signed int
/* Should we extend this to be host_addr_t and target_addr_t for case:
* host : x86_64
* target : mips64
*/
#define addr_t unsigned long
#endif /*__BASIC_TYPES_H__*/

175
drivers/staging/rtl8712/drv_types.h
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@ -1,175 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
*
* Modifications for inclusion into the Linux staging tree are
* Copyright(c) 2010 Larry Finger. All rights reserved.
*
* Contact information:
* WLAN FAE <wlanfae@realtek.com>
* Larry Finger <Larry.Finger@lwfinger.net>
*
******************************************************************************/
/* ---------------------------------------------------------------------
*
* For type defines and data structure defines
*
* ---------------------------------------------------------------------
*/
#ifndef __DRV_TYPES_H__
#define __DRV_TYPES_H__
struct _adapter;
#include "osdep_service.h"
#include "wlan_bssdef.h"
#include "rtl8712_spec.h"
#include "rtl8712_hal.h"
#include <linux/mutex.h>
#include <linux/completion.h>
enum _NIC_VERSION {
RTL8711_NIC,
RTL8712_NIC,
RTL8713_NIC,
RTL8716_NIC
};
struct qos_priv {
/* bit mask option: u-apsd, s-apsd, ts, block ack... */
unsigned int qos_option;
};
#include "rtl871x_ht.h"
#include "rtl871x_cmd.h"
#include "rtl871x_xmit.h"
#include "rtl871x_recv.h"
#include "rtl871x_security.h"
#include "rtl871x_pwrctrl.h"
#include "rtl871x_io.h"
#include "rtl871x_eeprom.h"
#include "sta_info.h"
#include "rtl871x_mlme.h"
#include "rtl871x_mp.h"
#include "rtl871x_debug.h"
#include "rtl871x_rf.h"
#include "rtl871x_event.h"
#include "rtl871x_led.h"
#define SPEC_DEV_ID_DISABLE_HT BIT(1)
struct specific_device_id {
u32 flags;
u16 idVendor;
u16 idProduct;
};
struct registry_priv {
u8 chip_version;
u8 rfintfs;
u8 lbkmode;
u8 hci;
u8 network_mode; /*infra, ad-hoc, auto*/
struct ndis_802_11_ssid ssid;
u8 channel;/* ad-hoc support requirement */
u8 wireless_mode;/* A, B, G, auto */
u8 vrtl_carrier_sense; /*Enable, Disable, Auto*/
u8 vcs_type;/*RTS/CTS, CTS-to-self*/
u16 rts_thresh;
u16 frag_thresh;
u8 preamble;/*long, short, auto*/
u8 scan_mode;/*active, passive*/
u8 adhoc_tx_pwr;
u8 soft_ap;
u8 smart_ps;
u8 power_mgnt;
u8 radio_enable;
u8 long_retry_lmt;
u8 short_retry_lmt;
u16 busy_thresh;
u8 ack_policy;
u8 mp_mode;
u8 software_encrypt;
u8 software_decrypt;
/* UAPSD */
u8 wmm_enable;
u8 uapsd_enable;
u8 uapsd_max_sp;
u8 uapsd_acbk_en;
u8 uapsd_acbe_en;
u8 uapsd_acvi_en;
u8 uapsd_acvo_en;
struct wlan_bssid_ex dev_network;
u8 ht_enable;
u8 cbw40_enable;
u8 ampdu_enable;/*for tx*/
u8 rf_config;
u8 low_power;
u8 wifi_test;
};
struct dvobj_priv {
struct _adapter *padapter;
u32 nr_endpoint;
u8 ishighspeed;
uint (*inirp_init)(struct _adapter *adapter);
uint (*inirp_deinit)(struct _adapter *adapter);
struct usb_device *pusbdev;
};
/**
* struct _adapter - the main adapter structure for this device.
*
* bup: True indicates that the interface is up.
*/
struct _adapter {
struct dvobj_priv dvobjpriv;
struct mlme_priv mlmepriv;
struct cmd_priv cmdpriv;
struct evt_priv evtpriv;
struct io_queue *pio_queue;
struct xmit_priv xmitpriv;
struct recv_priv recvpriv;
struct sta_priv stapriv;
struct security_priv securitypriv;
struct registry_priv registrypriv;
struct wlan_acl_pool acl_list;
struct pwrctrl_priv pwrctrlpriv;
struct eeprom_priv eeprompriv;
struct hal_priv halpriv;
struct led_priv ledpriv;
struct mp_priv mppriv;
bool driver_stopped;
bool surprise_removed;
bool suspended;
u8 eeprom_address_size;
u8 hw_init_completed;
struct task_struct *cmd_thread;
uint (*dvobj_init)(struct _adapter *adapter);
void (*dvobj_deinit)(struct _adapter *adapter);
struct net_device *pnetdev;
int bup;
struct net_device_stats stats;
struct iw_statistics iwstats;
int pid; /*process id from UI*/
struct work_struct wk_filter_rx_ff0;
const struct firmware *fw;
struct usb_interface *pusb_intf;
struct mutex mutex_start;
struct completion rtl8712_fw_ready;
struct completion rx_filter_ready;
};
static inline u8 *myid(struct eeprom_priv *peepriv)
{
return peepriv->mac_addr;
}
u8 r8712_usb_hal_bus_init(struct _adapter *adapter);
#endif /*__DRV_TYPES_H__*/

21
drivers/staging/rtl8712/ethernet.h
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@ -1,21 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
*
* Modifications for inclusion into the Linux staging tree are
* Copyright(c) 2010 Larry Finger. All rights reserved.
*
* Contact information:
* WLAN FAE <wlanfae@realtek.com>
* Larry Finger <Larry.Finger@lwfinger.net>
*
******************************************************************************/
#ifndef __INC_ETHERNET_H
#define __INC_ETHERNET_H
#define ETHERNET_HEADER_SIZE 14 /*!< Ethernet Header Length*/
#define LLC_HEADER_SIZE 6 /*!< LLC Header Length*/
#endif /* #ifndef __INC_ETHERNET_H */

401
drivers/staging/rtl8712/hal_init.c
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@ -1,401 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/******************************************************************************
*
* Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
* Linux device driver for RTL8192SU
*
* Modifications for inclusion into the Linux staging tree are
* Copyright(c) 2010 Larry Finger. All rights reserved.
*
* Contact information:
* WLAN FAE <wlanfae@realtek.com>.
* Larry Finger <Larry.Finger@lwfinger.net>
*
******************************************************************************/
#define _HAL_INIT_C_
#include <linux/usb.h>
#include <linux/device.h>
#include <linux/usb/ch9.h>
#include <linux/firmware.h>
#include <linux/module.h>
#include "osdep_service.h"
#include "drv_types.h"
#include "usb_osintf.h"
#define FWBUFF_ALIGN_SZ 512
#define MAX_DUMP_FWSZ (48 * 1024)
static void rtl871x_load_fw_fail(struct _adapter *adapter)
{
struct usb_device *udev = adapter->dvobjpriv.pusbdev;
struct device *dev = &udev->dev;
struct device *parent = dev->parent;
complete(&adapter->rtl8712_fw_ready);
dev_err(&udev->dev, "r8712u: Firmware request failed\n");
if (parent)
device_lock(parent);
device_release_driver(dev);
if (parent)
device_unlock(parent);
}
static void rtl871x_load_fw_cb(const struct firmware *firmware, void *context)
{
struct _adapter *adapter = context;
if (!firmware) {
rtl871x_load_fw_fail(adapter);
return;
}
adapter->fw = firmware;
/* firmware available - start netdev */
register_netdev(adapter->pnetdev);
complete(&adapter->rtl8712_fw_ready);
}
static const char firmware_file[] = "rtlwifi/rtl8712u.bin";
int rtl871x_load_fw(struct _adapter *padapter)
{
struct device *dev = &padapter->dvobjpriv.pusbdev->dev;
int rc;
init_completion(&padapter->rtl8712_fw_ready);
dev_info(dev, "r8712u: Loading firmware from \"%s\"\n", firmware_file);
rc = request_firmware_nowait(THIS_MODULE, 1, firmware_file, dev,
GFP_KERNEL, padapter, rtl871x_load_fw_cb);
if (rc)
dev_err(dev, "r8712u: Firmware request error %d\n", rc);
return rc;
}
MODULE_FIRMWARE("rtlwifi/rtl8712u.bin");
static u32 rtl871x_open_fw(struct _adapter *adapter, const u8 **mappedfw)
{
if (adapter->fw->size > 200000) {
dev_err(&adapter->pnetdev->dev, "r8712u: Bad fw->size of %zu\n",
adapter->fw->size);
return 0;
}
*mappedfw = adapter->fw->data;
return adapter->fw->size;
}
static void fill_fwpriv(struct _adapter *adapter, struct fw_priv *fwpriv)
{
struct dvobj_priv *dvobj = &adapter->dvobjpriv;
struct registry_priv *regpriv = &adapter->registrypriv;
memset(fwpriv, 0, sizeof(struct fw_priv));
/* todo: check if needs endian conversion */
fwpriv->hci_sel = RTL8712_HCI_TYPE_72USB;
fwpriv->usb_ep_num = (u8)dvobj->nr_endpoint;
fwpriv->bw_40MHz_en = regpriv->cbw40_enable;
switch (regpriv->rf_config) {
case RTL8712_RF_1T1R:
fwpriv->rf_config = RTL8712_RFC_1T1R;
break;
case RTL8712_RF_2T2R:
fwpriv->rf_config = RTL8712_RFC_2T2R;
break;
case RTL8712_RF_1T2R:
default:
fwpriv->rf_config = RTL8712_RFC_1T2R;
}
fwpriv->mp_mode = (regpriv->mp_mode == 1);
/* 0:off 1:on 2:auto */
fwpriv->vcs_type = regpriv->vrtl_carrier_sense;
fwpriv->vcs_mode = regpriv->vcs_type; /* 1:RTS/CTS 2:CTS to self */
/* default enable turbo_mode */
fwpriv->turbo_mode = (regpriv->wifi_test != 1);
fwpriv->low_power_mode = regpriv->low_power;
}
static void update_fwhdr(struct fw_hdr *pfwhdr, const u8 *pmappedfw)
{
pfwhdr->signature = le16_to_cpu(*(__le16 *)pmappedfw);
pfwhdr->version = le16_to_cpu(*(__le16 *)(pmappedfw + 2));
/* define the size of boot loader */
pfwhdr->dmem_size = le32_to_cpu(*(__le32 *)(pmappedfw + 4));
/* define the size of FW in IMEM */
pfwhdr->img_IMEM_size = le32_to_cpu(*(__le32 *)(pmappedfw + 8));
/* define the size of FW in SRAM */
pfwhdr->img_SRAM_size = le32_to_cpu(*(__le32 *)(pmappedfw + 12));
/* define the size of DMEM variable */
pfwhdr->fw_priv_sz = le32_to_cpu(*(__le32 *)(pmappedfw + 16));
}
static u8 chk_fwhdr(struct fw_hdr *pfwhdr, u32 ulfilelength)
{
u32 fwhdrsz, fw_sz;
/* check signature */
if ((pfwhdr->signature != 0x8712) && (pfwhdr->signature != 0x8192))
return _FAIL;
/* check fw_priv_sze & sizeof(struct fw_priv) */
if (pfwhdr->fw_priv_sz != sizeof(struct fw_priv))
return _FAIL;
/* check fw_sz & image_fw_sz */
fwhdrsz = offsetof(struct fw_hdr, fwpriv) + pfwhdr->fw_priv_sz;
fw_sz = fwhdrsz + pfwhdr->img_IMEM_size + pfwhdr->img_SRAM_size +
pfwhdr->dmem_size;
if (fw_sz != ulfilelength)
return _FAIL;
return _SUCCESS;
}
static u8 rtl8712_dl_fw(struct _adapter *adapter)
{
sint i;
u8 tmp8, tmp8_a;
u16 tmp16;
u32 maxlen = 0; /* for compare usage */
uint dump_imem_sz, imem_sz, dump_emem_sz, emem_sz; /* max = 49152; */
struct fw_hdr fwhdr;
u32 ulfilelength; /* FW file size */
const u8 *mappedfw = NULL;
u8 *tmpchar = NULL, *payload, *ptr;
struct tx_desc *txdesc;
u32 txdscp_sz = sizeof(struct tx_desc);
u8 ret = _FAIL;
ulfilelength = rtl871x_open_fw(adapter, &mappedfw);
if (mappedfw && (ulfilelength > 0)) {
update_fwhdr(&fwhdr, mappedfw);
if (chk_fwhdr(&fwhdr, ulfilelength) == _FAIL)
return ret;
fill_fwpriv(adapter, &fwhdr.fwpriv);
/* firmware check ok */
maxlen = (fwhdr.img_IMEM_size > fwhdr.img_SRAM_size) ?
fwhdr.img_IMEM_size : fwhdr.img_SRAM_size;
maxlen += txdscp_sz;
tmpchar = kmalloc(maxlen + FWBUFF_ALIGN_SZ, GFP_KERNEL);
if (!tmpchar)
return ret;
txdesc = (struct tx_desc *)(tmpchar + FWBUFF_ALIGN_SZ -
((addr_t)(tmpchar) & (FWBUFF_ALIGN_SZ - 1)));
payload = (u8 *)(txdesc) + txdscp_sz;
ptr = (u8 *)mappedfw + offsetof(struct fw_hdr, fwpriv) +
fwhdr.fw_priv_sz;
/* Download FirmWare */
/* 1. determine IMEM code size and Load IMEM Code Section */
imem_sz = fwhdr.img_IMEM_size;
do {
memset(txdesc, 0, TXDESC_SIZE);
if (imem_sz > MAX_DUMP_FWSZ/*49152*/) {
dump_imem_sz = MAX_DUMP_FWSZ;
} else {
dump_imem_sz = imem_sz;
txdesc->txdw0 |= cpu_to_le32(BIT(28));
}
txdesc->txdw0 |= cpu_to_le32(dump_imem_sz &
0x0000ffff);
memcpy(payload, ptr, dump_imem_sz);
r8712_write_mem(adapter, RTL8712_DMA_VOQ,
dump_imem_sz + TXDESC_SIZE,
(u8 *)txdesc);
ptr += dump_imem_sz;
imem_sz -= dump_imem_sz;
} while (imem_sz > 0);
i = 10;
tmp16 = r8712_read16(adapter, TCR);
while (((tmp16 & _IMEM_CODE_DONE) == 0) && (i > 0)) {
usleep_range(10, 1000);
tmp16 = r8712_read16(adapter, TCR);
i--;
}
if (i == 0 || (tmp16 & _IMEM_CHK_RPT) == 0)
goto exit_fail;
/* 2.Download EMEM code size and Load EMEM Code Section */
emem_sz = fwhdr.img_SRAM_size;
do {
memset(txdesc, 0, TXDESC_SIZE);
if (emem_sz > MAX_DUMP_FWSZ) { /* max=48k */
dump_emem_sz = MAX_DUMP_FWSZ;
} else {
dump_emem_sz = emem_sz;
txdesc->txdw0 |= cpu_to_le32(BIT(28));
}
txdesc->txdw0 |= cpu_to_le32(dump_emem_sz &
0x0000ffff);
memcpy(payload, ptr, dump_emem_sz);
r8712_write_mem(adapter, RTL8712_DMA_VOQ,
dump_emem_sz + TXDESC_SIZE,
(u8 *)txdesc);
ptr += dump_emem_sz;
emem_sz -= dump_emem_sz;
} while (emem_sz > 0);
i = 5;
tmp16 = r8712_read16(adapter, TCR);
while (((tmp16 & _EMEM_CODE_DONE) == 0) && (i > 0)) {
usleep_range(10, 1000);
tmp16 = r8712_read16(adapter, TCR);
i--;
}
if (i == 0 || (tmp16 & _EMEM_CHK_RPT) == 0)
goto exit_fail;
/* 3.Enable CPU */
tmp8 = r8712_read8(adapter, SYS_CLKR);
r8712_write8(adapter, SYS_CLKR, tmp8 | BIT(2));
tmp8_a = r8712_read8(adapter, SYS_CLKR);
if (tmp8_a != (tmp8 | BIT(2)))
goto exit_fail;
tmp8 = r8712_read8(adapter, SYS_FUNC_EN + 1);
r8712_write8(adapter, SYS_FUNC_EN + 1, tmp8 | BIT(2));
tmp8_a = r8712_read8(adapter, SYS_FUNC_EN + 1);
if (tmp8_a != (tmp8 | BIT(2)))
goto exit_fail;
r8712_read32(adapter, TCR);
/* 4.polling IMEM Ready */
i = 100;
tmp16 = r8712_read16(adapter, TCR);
while (((tmp16 & _IMEM_RDY) == 0) && (i > 0)) {
msleep(20);
tmp16 = r8712_read16(adapter, TCR);
i--;
}
if (i == 0) {
r8712_write16(adapter, 0x10250348, 0xc000);
r8712_write16(adapter, 0x10250348, 0xc001);
r8712_write16(adapter, 0x10250348, 0x2000);
r8712_write16(adapter, 0x10250348, 0x2001);
r8712_write16(adapter, 0x10250348, 0x2002);
r8712_write16(adapter, 0x10250348, 0x2003);
goto exit_fail;
}
/* 5.Download DMEM code size and Load EMEM Code Section */
memset(txdesc, 0, TXDESC_SIZE);
txdesc->txdw0 |= cpu_to_le32(fwhdr.fw_priv_sz & 0x0000ffff);
txdesc->txdw0 |= cpu_to_le32(BIT(28));
memcpy(payload, &fwhdr.fwpriv, fwhdr.fw_priv_sz);
r8712_write_mem(adapter, RTL8712_DMA_VOQ,
fwhdr.fw_priv_sz + TXDESC_SIZE, (u8 *)txdesc);
/* polling dmem code done */
i = 100;
tmp16 = r8712_read16(adapter, TCR);
while (((tmp16 & _DMEM_CODE_DONE) == 0) && (i > 0)) {
msleep(20);
tmp16 = r8712_read16(adapter, TCR);
i--;
}
if (i == 0)
goto exit_fail;
tmp8 = r8712_read8(adapter, 0x1025000A);
if (tmp8 & BIT(4)) /* When boot from EEPROM,
* & FW need more time to read EEPROM
*/
i = 60;
else /* boot from EFUSE */
i = 30;
tmp16 = r8712_read16(adapter, TCR);
while (((tmp16 & _FWRDY) == 0) && (i > 0)) {
msleep(100);
tmp16 = r8712_read16(adapter, TCR);
i--;
}
if (i == 0)
goto exit_fail;
} else {
goto exit_fail;
}
ret = _SUCCESS;
exit_fail:
kfree(tmpchar);
return ret;
}
uint rtl8712_hal_init(struct _adapter *padapter)
{
u32 val32;
int i;
/* r8712 firmware download */
if (rtl8712_dl_fw(padapter) != _SUCCESS)
return _FAIL;
netdev_info(padapter->pnetdev, "1 RCR=0x%x\n",
r8712_read32(padapter, RCR));
val32 = r8712_read32(padapter, RCR);
r8712_write32(padapter, RCR, (val32 | BIT(26))); /* Enable RX TCP
* Checksum offload
*/
netdev_info(padapter->pnetdev, "2 RCR=0x%x\n",
r8712_read32(padapter, RCR));
val32 = r8712_read32(padapter, RCR);
r8712_write32(padapter, RCR, (val32 | BIT(25))); /* Append PHY status */
val32 = r8712_read32(padapter, 0x10250040);
r8712_write32(padapter, 0x10250040, (val32 & 0x00FFFFFF));
/* for usb rx aggregation */
r8712_write8(padapter, 0x102500B5, r8712_read8(padapter, 0x102500B5) |
BIT(0)); /* page = 128bytes */
r8712_write8(padapter, 0x102500BD, r8712_read8(padapter, 0x102500BD) |
BIT(7)); /* enable usb rx aggregation */
r8712_write8(padapter, 0x102500D9, 1); /* TH=1 => means that invalidate
* usb rx aggregation
*/
r8712_write8(padapter, 0x1025FE5B, 0x04); /* 1.7ms/4 */
/* Fix the RX FIFO issue(USB error) */
r8712_write8(padapter, 0x1025fe5C, r8712_read8(padapter, 0x1025fe5C)
| BIT(7));
for (i = 0; i < ETH_ALEN; i++)
padapter->eeprompriv.mac_addr[i] = r8712_read8(padapter,
MACID + i);
return _SUCCESS;
}
uint rtl8712_hal_deinit(struct _adapter *padapter)
{
r8712_write8(padapter, RF_CTRL, 0x00);
/* Turn off BB */
msleep(20);
/* Turn off MAC */
r8712_write8(padapter, SYS_CLKR + 1, 0x38); /* Switch Control Path */
r8712_write8(padapter, SYS_FUNC_EN + 1, 0x70);
r8712_write8(padapter, PMC_FSM, 0x06); /* Enable Loader Data Keep */
r8712_write8(padapter, SYS_ISO_CTRL, 0xF9); /* Isolation signals from
* CORE, PLL
*/
r8712_write8(padapter, SYS_ISO_CTRL + 1, 0xe8); /* Enable EFUSE 1.2V */
r8712_write8(padapter, AFE_PLL_CTRL, 0x00); /* Disable AFE PLL. */
r8712_write8(padapter, LDOA15_CTRL, 0x54); /* Disable A15V */
r8712_write8(padapter, SYS_FUNC_EN + 1, 0x50); /* Disable E-Fuse 1.2V */
r8712_write8(padapter, LDOV12D_CTRL, 0x24); /* Disable LDO12(for CE) */
r8712_write8(padapter, AFE_MISC, 0x30); /* Disable AFE BG&MB */
/* Option for Disable 1.6V LDO. */
r8712_write8(padapter, SPS0_CTRL, 0x56); /* Disable 1.6V LDO */
r8712_write8(padapter, SPS0_CTRL + 1, 0x43); /* Set SW PFM */
return _SUCCESS;
}
uint rtl871x_hal_init(struct _adapter *padapter)
{
padapter->hw_init_completed = false;
if (!padapter->halpriv.hal_bus_init)
return _FAIL;
if (padapter->halpriv.hal_bus_init(padapter) != _SUCCESS)
return _FAIL;
if (rtl8712_hal_init(padapter) == _SUCCESS) {
padapter->hw_init_completed = true;
} else {
padapter->hw_init_completed = false;
return _FAIL;
}
return _SUCCESS;
}

415
drivers/staging/rtl8712/ieee80211.c
View File

@ -1,415 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/******************************************************************************
* ieee80211.c
*
* Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
* Linux device driver for RTL8192SU
*
* Modifications for inclusion into the Linux staging tree are
* Copyright(c) 2010 Larry Finger. All rights reserved.
*
* Contact information:
* WLAN FAE <wlanfae@realtek.com>.
* Larry Finger <Larry.Finger@lwfinger.net>
*
******************************************************************************/
#define _IEEE80211_C
#include "drv_types.h"
#include "ieee80211.h"
#include "wifi.h"
#include "osdep_service.h"
#include "wlan_bssdef.h"
static const u8 WPA_OUI_TYPE[] = {0x00, 0x50, 0xf2, 1};
static const u8 WPA_CIPHER_SUITE_NONE[] = {0x00, 0x50, 0xf2, 0};
static const u8 WPA_CIPHER_SUITE_WEP40[] = {0x00, 0x50, 0xf2, 1};
static const u8 WPA_CIPHER_SUITE_TKIP[] = {0x00, 0x50, 0xf2, 2};
static const u8 WPA_CIPHER_SUITE_CCMP[] = {0x00, 0x50, 0xf2, 4};
static const u8 WPA_CIPHER_SUITE_WEP104[] = {0x00, 0x50, 0xf2, 5};
static const u8 RSN_CIPHER_SUITE_NONE[] = {0x00, 0x0f, 0xac, 0};
static const u8 RSN_CIPHER_SUITE_WEP40[] = {0x00, 0x0f, 0xac, 1};
static const u8 RSN_CIPHER_SUITE_TKIP[] = {0x00, 0x0f, 0xac, 2};
static const u8 RSN_CIPHER_SUITE_CCMP[] = {0x00, 0x0f, 0xac, 4};
static const u8 RSN_CIPHER_SUITE_WEP104[] = {0x00, 0x0f, 0xac, 5};
/*-----------------------------------------------------------
* for adhoc-master to generate ie and provide supported-rate to fw
*-----------------------------------------------------------
*/
static u8 WIFI_CCKRATES[] = {
(IEEE80211_CCK_RATE_1MB | IEEE80211_BASIC_RATE_MASK),
(IEEE80211_CCK_RATE_2MB | IEEE80211_BASIC_RATE_MASK),
(IEEE80211_CCK_RATE_5MB | IEEE80211_BASIC_RATE_MASK),
(IEEE80211_CCK_RATE_11MB | IEEE80211_BASIC_RATE_MASK)
};
static u8 WIFI_OFDMRATES[] = {
(IEEE80211_OFDM_RATE_6MB),
(IEEE80211_OFDM_RATE_9MB),
(IEEE80211_OFDM_RATE_12MB),
(IEEE80211_OFDM_RATE_18MB),
(IEEE80211_OFDM_RATE_24MB),
(IEEE80211_OFDM_RATE_36MB),
(IEEE80211_OFDM_RATE_48MB),
(IEEE80211_OFDM_RATE_54MB)
};
uint r8712_is_cckrates_included(u8 *rate)
{
u32 i = 0;
while (rate[i] != 0) {
if ((((rate[i]) & 0x7f) == 2) || (((rate[i]) & 0x7f) == 4) ||
(((rate[i]) & 0x7f) == 11) || (((rate[i]) & 0x7f) == 22))
return true;
i++;
}
return false;
}
uint r8712_is_cckratesonly_included(u8 *rate)
{
u32 i = 0;
while (rate[i] != 0) {
if ((((rate[i]) & 0x7f) != 2) && (((rate[i]) & 0x7f) != 4) &&
(((rate[i]) & 0x7f) != 11) && (((rate[i]) & 0x7f) != 22))
return false;
i++;
}
return true;
}
/* r8712_set_ie will update frame length */
u8 *r8712_set_ie(u8 *pbuf, sint index, uint len, u8 *source, uint *frlen)
{
*pbuf = (u8)index;
*(pbuf + 1) = (u8)len;
if (len > 0)
memcpy((void *)(pbuf + 2), (void *)source, len);
*frlen = *frlen + (len + 2);
return pbuf + len + 2;
}
/* ---------------------------------------------------------------------------
* index: the information element id index, limit is the limit for search
* ---------------------------------------------------------------------------
*/
u8 *r8712_get_ie(u8 *pbuf, sint index, uint *len, sint limit)
{
sint tmp, i;
u8 *p;
if (limit < 1)
return NULL;
p = pbuf;
i = 0;
*len = 0;
while (1) {
if (*p == index) {
*len = *(p + 1);
return p;
}
tmp = *(p + 1);
p += (tmp + 2);
i += (tmp + 2);
if (i >= limit)
break;
}
return NULL;
}
static void set_supported_rate(u8 *rates, uint mode)
{
memset(rates, 0, NDIS_802_11_LENGTH_RATES_EX);
switch (mode) {
case WIRELESS_11B:
memcpy(rates, WIFI_CCKRATES, IEEE80211_CCK_RATE_LEN);
break;
case WIRELESS_11G:
case WIRELESS_11A:
memcpy(rates, WIFI_OFDMRATES, IEEE80211_NUM_OFDM_RATESLEN);
break;
case WIRELESS_11BG:
memcpy(rates, WIFI_CCKRATES, IEEE80211_CCK_RATE_LEN);
memcpy(rates + IEEE80211_CCK_RATE_LEN, WIFI_OFDMRATES,
IEEE80211_NUM_OFDM_RATESLEN);
break;
}
}
static uint r8712_get_rateset_len(u8 *rateset)
{
uint i = 0;
while (1) {
if ((rateset[i]) == 0)
break;
if (i > 12)
break;
i++;
}
return i;
}
int r8712_generate_ie(struct registry_priv *registrypriv)
{
int rate_len;
uint sz = 0;
struct wlan_bssid_ex *dev_network = &registrypriv->dev_network;
u8 *ie = dev_network->IEs;
u16 beacon_period = (u16)dev_network->Configuration.BeaconPeriod;
/*timestamp will be inserted by hardware*/
sz += 8;
ie += sz;
/*beacon interval : 2bytes*/
*(__le16 *)ie = cpu_to_le16(beacon_period);
sz += 2;
ie += 2;
/*capability info*/
*(u16 *)ie = 0;
*(__le16 *)ie |= cpu_to_le16(WLAN_CAPABILITY_IBSS);
if (registrypriv->preamble == PREAMBLE_SHORT)
*(__le16 *)ie |= cpu_to_le16(WLAN_CAPABILITY_SHORT_PREAMBLE);
if (dev_network->Privacy)
*(__le16 *)ie |= cpu_to_le16(WLAN_CAPABILITY_PRIVACY);
sz += 2;
ie += 2;
/*SSID*/
ie = r8712_set_ie(ie, WLAN_EID_SSID, dev_network->Ssid.SsidLength,
dev_network->Ssid.Ssid, &sz);
/*supported rates*/
set_supported_rate(dev_network->rates, registrypriv->wireless_mode);
rate_len = r8712_get_rateset_len(dev_network->rates);
if (rate_len > 8) {
ie = r8712_set_ie(ie, WLAN_EID_SUPP_RATES, 8,
dev_network->rates, &sz);
ie = r8712_set_ie(ie, WLAN_EID_EXT_SUPP_RATES, (rate_len - 8),
(dev_network->rates + 8), &sz);
} else {
ie = r8712_set_ie(ie, WLAN_EID_SUPP_RATES,
rate_len, dev_network->rates, &sz);
}
/*DS parameter set*/
ie = r8712_set_ie(ie, WLAN_EID_DS_PARAMS, 1,
(u8 *)&dev_network->Configuration.DSConfig, &sz);
/*IBSS Parameter Set*/
ie = r8712_set_ie(ie, WLAN_EID_IBSS_PARAMS, 2,
(u8 *)&dev_network->Configuration.ATIMWindow, &sz);
return sz;
}
unsigned char *r8712_get_wpa_ie(unsigned char *ie, uint *wpa_ie_len, int limit)
{
u32 len;
u16 val16;
unsigned char wpa_oui_type[] = {0x00, 0x50, 0xf2, 0x01};
u8 *buf = ie;
while (1) {
buf = r8712_get_ie(buf, _WPA_IE_ID_, &len, limit);
if (buf) {
/*check if oui matches...*/
if (memcmp((buf + 2), wpa_oui_type,
sizeof(wpa_oui_type)))
goto check_next_ie;
/*check version...*/
memcpy((u8 *)&val16, (buf + 6), sizeof(val16));
le16_to_cpus(&val16);
if (val16 != 0x0001)
goto check_next_ie;
*wpa_ie_len = *(buf + 1);
return buf;
}
*wpa_ie_len = 0;
return NULL;
check_next_ie:
limit = limit - (buf - ie) - 2 - len;
if (limit <= 0)
break;
buf += (2 + len);
}
*wpa_ie_len = 0;
return NULL;
}
unsigned char *r8712_get_wpa2_ie(unsigned char *pie, uint *rsn_ie_len,
int limit)
{
return r8712_get_ie(pie, _WPA2_IE_ID_, rsn_ie_len, limit);
}
static int r8712_get_wpa_cipher_suite(u8 *s)
{
if (!memcmp(s, (void *)WPA_CIPHER_SUITE_NONE, WPA_SELECTOR_LEN))
return WPA_CIPHER_NONE;
if (!memcmp(s, (void *)WPA_CIPHER_SUITE_WEP40, WPA_SELECTOR_LEN))
return WPA_CIPHER_WEP40;
if (!memcmp(s, (void *)WPA_CIPHER_SUITE_TKIP, WPA_SELECTOR_LEN))
return WPA_CIPHER_TKIP;
if (!memcmp(s, (void *)WPA_CIPHER_SUITE_CCMP, WPA_SELECTOR_LEN))
return WPA_CIPHER_CCMP;
if (!memcmp(s, (void *)WPA_CIPHER_SUITE_WEP104, WPA_SELECTOR_LEN))
return WPA_CIPHER_WEP104;
return 0;
}
static int r8712_get_wpa2_cipher_suite(u8 *s)
{
if (!memcmp(s, (void *)RSN_CIPHER_SUITE_NONE, RSN_SELECTOR_LEN))
return WPA_CIPHER_NONE;
if (!memcmp(s, (void *)RSN_CIPHER_SUITE_WEP40, RSN_SELECTOR_LEN))
return WPA_CIPHER_WEP40;
if (!memcmp(s, (void *)RSN_CIPHER_SUITE_TKIP, RSN_SELECTOR_LEN))
return WPA_CIPHER_TKIP;
if (!memcmp(s, (void *)RSN_CIPHER_SUITE_CCMP, RSN_SELECTOR_LEN))
return WPA_CIPHER_CCMP;
if (!memcmp(s, (void *)RSN_CIPHER_SUITE_WEP104, RSN_SELECTOR_LEN))
return WPA_CIPHER_WEP104;
return 0;
}
int r8712_parse_wpa_ie(u8 *wpa_ie, int wpa_ie_len, int *group_cipher,
int *pairwise_cipher)
{
int i;
int left, count;
u8 *pos;
if (wpa_ie_len <= 0) {
/* No WPA IE - fail silently */
return -EINVAL;
}
if ((*wpa_ie != _WPA_IE_ID_) ||
(*(wpa_ie + 1) != (u8)(wpa_ie_len - 2)) ||
(memcmp(wpa_ie + 2, (void *)WPA_OUI_TYPE, WPA_SELECTOR_LEN)))
return -EINVAL;
pos = wpa_ie;
pos += 8;
left = wpa_ie_len - 8;
/*group_cipher*/
if (left >= WPA_SELECTOR_LEN) {
*group_cipher = r8712_get_wpa_cipher_suite(pos);
pos += WPA_SELECTOR_LEN;
left -= WPA_SELECTOR_LEN;
} else if (left > 0) {
return -EINVAL;
}
/*pairwise_cipher*/
if (left >= 2) {
count = le16_to_cpu(*(__le16 *)pos);
pos += 2;
left -= 2;
if (count == 0 || left < count * WPA_SELECTOR_LEN)
return -EINVAL;
for (i = 0; i < count; i++) {
*pairwise_cipher |= r8712_get_wpa_cipher_suite(pos);
pos += WPA_SELECTOR_LEN;
left -= WPA_SELECTOR_LEN;
}
} else if (left == 1) {
return -EINVAL;
}
return 0;
}
int r8712_parse_wpa2_ie(u8 *rsn_ie, int rsn_ie_len, int *group_cipher,
int *pairwise_cipher)
{
int i;
int left, count;
u8 *pos;
if (rsn_ie_len <= 0) {
/* No RSN IE - fail silently */
return -EINVAL;
}
if ((*rsn_ie != _WPA2_IE_ID_) ||
(*(rsn_ie + 1) != (u8)(rsn_ie_len - 2)))
return -EINVAL;
pos = rsn_ie;
pos += 4;
left = rsn_ie_len - 4;
/*group_cipher*/
if (left >= RSN_SELECTOR_LEN) {
*group_cipher = r8712_get_wpa2_cipher_suite(pos);
pos += RSN_SELECTOR_LEN;
left -= RSN_SELECTOR_LEN;
} else if (left > 0) {
return -EINVAL;
}
/*pairwise_cipher*/
if (left >= 2) {
count = le16_to_cpu(*(__le16 *)pos);
pos += 2;
left -= 2;
if (count == 0 || left < count * RSN_SELECTOR_LEN)
return -EINVAL;
for (i = 0; i < count; i++) {
*pairwise_cipher |= r8712_get_wpa2_cipher_suite(pos);
pos += RSN_SELECTOR_LEN;
left -= RSN_SELECTOR_LEN;
}
} else if (left == 1) {
return -EINVAL;
}
return 0;
}
int r8712_get_sec_ie(u8 *in_ie, uint in_len, u8 *rsn_ie, u16 *rsn_len,
u8 *wpa_ie, u16 *wpa_len)
{
u8 authmode;
u8 wpa_oui[4] = {0x0, 0x50, 0xf2, 0x01};
uint cnt;
/*Search required WPA or WPA2 IE and copy to sec_ie[ ]*/
cnt = _TIMESTAMP_ + _BEACON_ITERVAL_ + _CAPABILITY_;
while (cnt < in_len) {
authmode = in_ie[cnt];
if ((authmode == _WPA_IE_ID_) &&
(!memcmp(&in_ie[cnt + 2], &wpa_oui[0], 4))) {
memcpy(wpa_ie, &in_ie[cnt], in_ie[cnt + 1] + 2);
*wpa_len = in_ie[cnt + 1] + 2;
cnt += in_ie[cnt + 1] + 2; /*get next */
} else {
if (authmode == _WPA2_IE_ID_) {
memcpy(rsn_ie, &in_ie[cnt],
in_ie[cnt + 1] + 2);
*rsn_len = in_ie[cnt + 1] + 2;
cnt += in_ie[cnt + 1] + 2; /*get next*/
} else {
cnt += in_ie[cnt + 1] + 2; /*get next*/
}
}
}
return *rsn_len + *wpa_len;
}
int r8712_get_wps_ie(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen)
{
int match;
uint cnt;
u8 eid, wps_oui[4] = {0x0, 0x50, 0xf2, 0x04};
cnt = 12;
match = false;
while (cnt < in_len) {
eid = in_ie[cnt];
if ((eid == _WPA_IE_ID_) &&
(!memcmp(&in_ie[cnt + 2], wps_oui, 4))) {
memcpy(wps_ie, &in_ie[cnt], in_ie[cnt + 1] + 2);
*wps_ielen = in_ie[cnt + 1] + 2;
cnt += in_ie[cnt + 1] + 2;
match = true;
break;
}
cnt += in_ie[cnt + 1] + 2; /* goto next */
}
return match;
}

165
drivers/staging/rtl8712/ieee80211.h
View File

@ -1,165 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
*
* Modifications for inclusion into the Linux staging tree are
* Copyright(c) 2010 Larry Finger. All rights reserved.
*
* Contact information:
* WLAN FAE <wlanfae@realtek.com>
* Larry Finger <Larry.Finger@lwfinger.net>
*
******************************************************************************/
#ifndef __IEEE80211_H
#define __IEEE80211_H
#include <linux/ieee80211.h>
#define IEEE_CMD_SET_WPA_PARAM 1
#define IEEE_CMD_SET_WPA_IE 2
#define IEEE_CMD_SET_ENCRYPTION 3
#define IEEE_CMD_MLME 4
#define IEEE_PARAM_WPA_ENABLED 1
#define IEEE_PARAM_TKIP_COUNTERMEASURES 2
#define IEEE_PARAM_DROP_UNENCRYPTED 3
#define IEEE_PARAM_PRIVACY_INVOKED 4
#define IEEE_PARAM_AUTH_ALGS 5
#define IEEE_PARAM_IEEE_802_1X 6
#define IEEE_PARAM_WPAX_SELECT 7
#define AUTH_ALG_OPEN_SYSTEM 0x1
#define AUTH_ALG_SHARED_KEY 0x2
#define AUTH_ALG_LEAP 0x00000004
#define IEEE_MLME_STA_DEAUTH 1
#define IEEE_MLME_STA_DISASSOC 2
#define IEEE_CRYPT_ERR_UNKNOWN_ALG 2
#define IEEE_CRYPT_ERR_UNKNOWN_ADDR 3
#define IEEE_CRYPT_ERR_CRYPT_INIT_FAILED 4
#define IEEE_CRYPT_ERR_KEY_SET_FAILED 5
#define IEEE_CRYPT_ERR_TX_KEY_SET_FAILED 6
#define IEEE_CRYPT_ERR_CARD_CONF_FAILED 7
#define IEEE_CRYPT_ALG_NAME_LEN 16
#define WPA_CIPHER_NONE BIT(0)
#define WPA_CIPHER_WEP40 BIT(1)
#define WPA_CIPHER_WEP104 BIT(2)
#define WPA_CIPHER_TKIP BIT(3)
#define WPA_CIPHER_CCMP BIT(4)
#define WPA_SELECTOR_LEN 4
#define RSN_HEADER_LEN 4
#define RSN_SELECTOR_LEN 4
enum NETWORK_TYPE {
WIRELESS_INVALID = 0,
WIRELESS_11B = 1,
WIRELESS_11G = 2,
WIRELESS_11BG = (WIRELESS_11B | WIRELESS_11G),
WIRELESS_11A = 4,
WIRELESS_11N = 8,
WIRELESS_11GN = (WIRELESS_11G | WIRELESS_11N),
WIRELESS_11BGN = (WIRELESS_11B | WIRELESS_11G | WIRELESS_11N),
};
struct ieee_param {
u32 cmd;
u8 sta_addr[ETH_ALEN];
union {
struct {
u8 name;
u32 value;
} wpa_param;
struct {
u32 len;
u8 reserved[32];
u8 data[];
} wpa_ie;
struct {
int command;
int reason_code;
} mlme;
struct {
u8 alg[IEEE_CRYPT_ALG_NAME_LEN];
u8 set_tx;
u32 err;
u8 idx;
u8 seq[8]; /* sequence counter (set: RX, get: TX) */
u16 key_len;
u8 key[];
} crypt;
} u;
};
#define MIN_FRAG_THRESHOLD 256U
#define MAX_FRAG_THRESHOLD 2346U
/* QoS,QOS */
#define NORMAL_ACK 0
/* IEEE 802.11 defines */
#define P80211_OUI_LEN 3
struct ieee80211_snap_hdr {
u8 dsap; /* always 0xAA */
u8 ssap; /* always 0xAA */
u8 ctrl; /* always 0x03 */
u8 oui[P80211_OUI_LEN]; /* organizational universal id */
} __packed;
#define SNAP_SIZE sizeof(struct ieee80211_snap_hdr)
#define IEEE80211_CCK_RATE_LEN 4
#define IEEE80211_NUM_OFDM_RATESLEN 8
#define IEEE80211_CCK_RATE_1MB 0x02
#define IEEE80211_CCK_RATE_2MB 0x04
#define IEEE80211_CCK_RATE_5MB 0x0B
#define IEEE80211_CCK_RATE_11MB 0x16
#define IEEE80211_OFDM_RATE_6MB 0x0C
#define IEEE80211_OFDM_RATE_9MB 0x12
#define IEEE80211_OFDM_RATE_12MB 0x18
#define IEEE80211_OFDM_RATE_18MB 0x24
#define IEEE80211_OFDM_RATE_24MB 0x30
#define IEEE80211_OFDM_RATE_36MB 0x48
#define IEEE80211_OFDM_RATE_48MB 0x60
#define IEEE80211_OFDM_RATE_54MB 0x6C
#define IEEE80211_BASIC_RATE_MASK 0x80
#define WEP_KEYS 4
/* MAX_RATES_LENGTH needs to be 12. The spec says 8, and many APs
* only use 8, and then use extended rates for the remaining supported
* rates. Other APs, however, stick all of their supported rates on the
* main rates information element...
*/
#define MAX_RATES_LENGTH ((u8)12)
#define MAX_WPA_IE_LEN 128
struct registry_priv;
u8 *r8712_set_ie(u8 *pbuf, sint index, uint len, u8 *source, uint *frlen);
u8 *r8712_get_ie(u8 *pbuf, sint index, uint *len, sint limit);
unsigned char *r8712_get_wpa_ie(unsigned char *pie, uint *rsn_ie_len,
int limit);
unsigned char *r8712_get_wpa2_ie(unsigned char *pie, uint *rsn_ie_len,
int limit);
int r8712_parse_wpa_ie(u8 *wpa_ie, int wpa_ie_len, int *group_cipher,
int *pairwise_cipher);
int r8712_parse_wpa2_ie(u8 *wpa_ie, int wpa_ie_len, int *group_cipher,
int *pairwise_cipher);
int r8712_get_sec_ie(u8 *in_ie, uint in_len, u8 *rsn_ie, u16 *rsn_len,
u8 *wpa_ie, u16 *wpa_len);
int r8712_get_wps_ie(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen);
int r8712_generate_ie(struct registry_priv *pregistrypriv);
uint r8712_is_cckrates_included(u8 *rate);
uint r8712_is_cckratesonly_included(u8 *rate);
#endif /* IEEE80211_H */

160
drivers/staging/rtl8712/mlme_linux.c
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@ -1,160 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/******************************************************************************
* mlme_linux.c
*
* Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
* Linux device driver for RTL8192SU
*
* Modifications for inclusion into the Linux staging tree are
* Copyright(c) 2010 Larry Finger. All rights reserved.
*
* Contact information:
* WLAN FAE <wlanfae@realtek.com>.
* Larry Finger <Larry.Finger@lwfinger.net>
*
******************************************************************************/
#define _MLME_OSDEP_C_
#include "osdep_service.h"
#include "drv_types.h"
#include "mlme_osdep.h"
static void sitesurvey_ctrl_handler(struct timer_list *t)
{
struct _adapter *adapter =
from_timer(adapter, t,
mlmepriv.sitesurveyctrl.sitesurvey_ctrl_timer);
_r8712_sitesurvey_ctrl_handler(adapter);
mod_timer(&adapter->mlmepriv.sitesurveyctrl.sitesurvey_ctrl_timer,
jiffies + msecs_to_jiffies(3000));
}
static void join_timeout_handler (struct timer_list *t)
{
struct _adapter *adapter =
from_timer(adapter, t, mlmepriv.assoc_timer);
_r8712_join_timeout_handler(adapter);
}
static void _scan_timeout_handler (struct timer_list *t)
{
struct _adapter *adapter =
from_timer(adapter, t, mlmepriv.scan_to_timer);
r8712_scan_timeout_handler(adapter);
}
static void dhcp_timeout_handler (struct timer_list *t)
{
struct _adapter *adapter =
from_timer(adapter, t, mlmepriv.dhcp_timer);
_r8712_dhcp_timeout_handler(adapter);
}
static void wdg_timeout_handler (struct timer_list *t)
{
struct _adapter *adapter =
from_timer(adapter, t, mlmepriv.wdg_timer);
r8712_wdg_wk_cmd(adapter);
mod_timer(&adapter->mlmepriv.wdg_timer,
jiffies + msecs_to_jiffies(2000));
}
void r8712_init_mlme_timer(struct _adapter *adapter)
{
struct mlme_priv *mlmepriv = &adapter->mlmepriv;
timer_setup(&mlmepriv->assoc_timer, join_timeout_handler, 0);
timer_setup(&mlmepriv->sitesurveyctrl.sitesurvey_ctrl_timer,
sitesurvey_ctrl_handler, 0);
timer_setup(&mlmepriv->scan_to_timer, _scan_timeout_handler, 0);
timer_setup(&mlmepriv->dhcp_timer, dhcp_timeout_handler, 0);
timer_setup(&mlmepriv->wdg_timer, wdg_timeout_handler, 0);
}
void r8712_os_indicate_connect(struct _adapter *adapter)
{
r8712_indicate_wx_assoc_event(adapter);
netif_carrier_on(adapter->pnetdev);
}
static struct RT_PMKID_LIST backupPMKIDList[NUM_PMKID_CACHE];
void r8712_os_indicate_disconnect(struct _adapter *adapter)
{
u8 backupPMKIDIndex = 0;
u8 backupTKIPCountermeasure = 0x00;
r8712_indicate_wx_disassoc_event(adapter);
netif_carrier_off(adapter->pnetdev);
if (adapter->securitypriv.AuthAlgrthm == 2) { /*/802.1x*/
/* We have to backup the PMK information for WiFi PMK Caching
* test item. Backup the btkip_countermeasure information.
* When the countermeasure is trigger, the driver have to
* disconnect with AP for 60 seconds.
*/
memcpy(&backupPMKIDList[0],
&adapter->securitypriv.PMKIDList[0],
sizeof(struct RT_PMKID_LIST) * NUM_PMKID_CACHE);
backupPMKIDIndex = adapter->securitypriv.PMKIDIndex;
backupTKIPCountermeasure =
adapter->securitypriv.btkip_countermeasure;
memset((unsigned char *)&adapter->securitypriv, 0,
sizeof(struct security_priv));
timer_setup(&adapter->securitypriv.tkip_timer,
r8712_use_tkipkey_handler, 0);
/* Restore the PMK information to securitypriv structure
* for the following connection.
*/
memcpy(&adapter->securitypriv.PMKIDList[0],
&backupPMKIDList[0],
sizeof(struct RT_PMKID_LIST) * NUM_PMKID_CACHE);
adapter->securitypriv.PMKIDIndex = backupPMKIDIndex;
adapter->securitypriv.btkip_countermeasure =
backupTKIPCountermeasure;
} else { /*reset values in securitypriv*/
struct security_priv *sec_priv = &adapter->securitypriv;
sec_priv->AuthAlgrthm = 0; /*open system*/
sec_priv->PrivacyAlgrthm = _NO_PRIVACY_;
sec_priv->PrivacyKeyIndex = 0;
sec_priv->XGrpPrivacy = _NO_PRIVACY_;
sec_priv->XGrpKeyid = 1;
sec_priv->ndisauthtype = Ndis802_11AuthModeOpen;
sec_priv->ndisencryptstatus = Ndis802_11WEPDisabled;
sec_priv->wps_phase = false;
}
}
void r8712_report_sec_ie(struct _adapter *adapter, u8 authmode, u8 *sec_ie)
{
uint len;
u8 *buff, *p, i;
union iwreq_data wrqu;
buff = NULL;
if (authmode == _WPA_IE_ID_) {
buff = kzalloc(IW_CUSTOM_MAX, GFP_ATOMIC);
if (!buff)
return;
p = buff;
p += sprintf(p, "ASSOCINFO(ReqIEs=");
len = sec_ie[1] + 2;
len = (len < IW_CUSTOM_MAX) ? len : IW_CUSTOM_MAX;
for (i = 0; i < len; i++)
p += sprintf(p, "%02x", sec_ie[i]);
p += sprintf(p, ")");
memset(&wrqu, 0, sizeof(wrqu));
wrqu.data.length = p - buff;
wrqu.data.length = (wrqu.data.length < IW_CUSTOM_MAX) ?
wrqu.data.length : IW_CUSTOM_MAX;
wireless_send_event(adapter->pnetdev, IWEVCUSTOM, &wrqu, buff);
kfree(buff);
}
}

31
drivers/staging/rtl8712/mlme_osdep.h
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@ -1,31 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
*
* Modifications for inclusion into the Linux staging tree are
* Copyright(c) 2010 Larry Finger. All rights reserved.
*
* Contact information:
* WLAN FAE <wlanfae@realtek.com>
* Larry Finger <Larry.Finger@lwfinger.net>
*
******************************************************************************/
#ifndef __MLME_OSDEP_H_
#define __MLME_OSDEP_H_
#include "osdep_service.h"
#include "drv_types.h"
void r8712_init_mlme_timer(struct _adapter *padapter);
void r8712_os_indicate_disconnect(struct _adapter *adapter);
void r8712_os_indicate_connect(struct _adapter *adapter);
void r8712_report_sec_ie(struct _adapter *adapter, u8 authmode, u8 *sec_ie);
int r8712_recv_indicatepkts_in_order(struct _adapter *adapter,
struct recv_reorder_ctrl *precvreorder_ctrl,
int bforced);
void r8712_indicate_wx_assoc_event(struct _adapter *padapter);
void r8712_indicate_wx_disassoc_event(struct _adapter *padapter);
#endif /*_MLME_OSDEP_H_*/

287
drivers/staging/rtl8712/mp_custom_oid.h
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@ -1,287 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
*
* Modifications for inclusion into the Linux staging tree are
* Copyright(c) 2010 Larry Finger. All rights reserved.
*
* Contact information:
* WLAN FAE <wlanfae@realtek.com>
* Larry Finger <Larry.Finger@lwfinger.net>
*
******************************************************************************/
#ifndef __CUSTOM_OID_H
#define __CUSTOM_OID_H
/* 0xFF818000 - 0xFF81802F RTL8180 Mass Production Kit
* 0xFF818500 - 0xFF81850F RTL8185 Setup Utility
* 0xFF818580 - 0xFF81858F RTL8185 Phy Status Utility
*
* by Owen for Production Kit
* For Production Kit with Agilent Equipments
* in order to make our custom oids hopefully somewhat unique
* we will use 0xFF (indicating implementation specific OID)
* 81(first byte of non zero Realtek unique identifier)
* 80 (second byte of non zero Realtek unique identifier)
* XX (the custom OID number - providing 255 possible custom oids)
*/
#define OID_RT_PRO_RESET_DUT 0xFF818000
#define OID_RT_PRO_SET_DATA_RATE 0xFF818001
#define OID_RT_PRO_START_TEST 0xFF818002
#define OID_RT_PRO_STOP_TEST 0xFF818003
#define OID_RT_PRO_SET_PREAMBLE 0xFF818004
#define OID_RT_PRO_SET_SCRAMBLER 0xFF818005
#define OID_RT_PRO_SET_FILTER_BB 0xFF818006
#define OID_RT_PRO_SET_MANUAL_DIVERSITY_BB 0xFF818007
#define OID_RT_PRO_SET_CHANNEL_DIRECT_CALL 0xFF818008
#define OID_RT_PRO_SET_SLEEP_MODE_DIRECT_CALL 0xFF818009
#define OID_RT_PRO_SET_WAKE_MODE_DIRECT_CALL 0xFF81800A
#define OID_RT_PRO_SET_TX_ANTENNA_BB 0xFF81800D
#define OID_RT_PRO_SET_ANTENNA_BB 0xFF81800E
#define OID_RT_PRO_SET_CR_SCRAMBLER 0xFF81800F
#define OID_RT_PRO_SET_CR_NEW_FILTER 0xFF818010
#define OID_RT_PRO_SET_TX_POWER_CONTROL 0xFF818011
#define OID_RT_PRO_SET_CR_TX_CONFIG 0xFF818012
#define OID_RT_PRO_GET_TX_POWER_CONTROL 0xFF818013
#define OID_RT_PRO_GET_CR_SIGNAL_QUALITY 0xFF818014
#define OID_RT_PRO_SET_CR_SETPOINT 0xFF818015
#define OID_RT_PRO_SET_INTEGRATOR 0xFF818016
#define OID_RT_PRO_SET_SIGNAL_QUALITY 0xFF818017
#define OID_RT_PRO_GET_INTEGRATOR 0xFF818018
#define OID_RT_PRO_GET_SIGNAL_QUALITY 0xFF818019
#define OID_RT_PRO_QUERY_EEPROM_TYPE 0xFF81801A
#define OID_RT_PRO_WRITE_MAC_ADDRESS 0xFF81801B
#define OID_RT_PRO_READ_MAC_ADDRESS 0xFF81801C
#define OID_RT_PRO_WRITE_CIS_DATA 0xFF81801D
#define OID_RT_PRO_READ_CIS_DATA 0xFF81801E
#define OID_RT_PRO_WRITE_POWER_CONTROL 0xFF81801F
#define OID_RT_PRO_READ_POWER_CONTROL 0xFF818020
#define OID_RT_PRO_WRITE_EEPROM 0xFF818021
#define OID_RT_PRO_READ_EEPROM 0xFF818022
#define OID_RT_PRO_RESET_TX_PACKET_SENT 0xFF818023
#define OID_RT_PRO_QUERY_TX_PACKET_SENT 0xFF818024
#define OID_RT_PRO_RESET_RX_PACKET_RECEIVED 0xFF818025
#define OID_RT_PRO_QUERY_RX_PACKET_RECEIVED 0xFF818026
#define OID_RT_PRO_QUERY_RX_PACKET_CRC32_ERROR 0xFF818027
#define OID_RT_PRO_QUERY_CURRENT_ADDRESS 0xFF818028
#define OID_RT_PRO_QUERY_PERMANENT_ADDRESS 0xFF818029
#define OID_RT_PRO_SET_PHILIPS_RF_PARAMETERS 0xFF81802A
#define OID_RT_PRO_RECEIVE_PACKET 0xFF81802C
#define OID_RT_PRO_WRITE_EEPROM_BYTE 0xFF81802D
#define OID_RT_PRO_READ_EEPROM_BYTE 0xFF81802E
#define OID_RT_PRO_SET_MODULATION 0xFF81802F
#define OID_RT_DRIVER_OPTION 0xFF818080
#define OID_RT_RF_OFF 0xFF818081
#define OID_RT_AUTH_STATUS 0xFF818082
#define OID_RT_PRO_SET_CONTINUOUS_TX 0xFF81800B
#define OID_RT_PRO_SET_SINGLE_CARRIER_TX 0xFF81800C
#define OID_RT_PRO_SET_CARRIER_SUPPRESSION_TX 0xFF81802B
#define OID_RT_PRO_SET_SINGLE_TONE_TX 0xFF818043
#define OID_RT_UTILITY_FALSE_ALARM_COUNTERS 0xFF818580
#define OID_RT_UTILITY_SELECT_DEBUG_MODE 0xFF818581
#define OID_RT_UTILITY_SELECT_SUBCARRIER_NUMBER 0xFF818582
#define OID_RT_UTILITY_GET_RSSI_STATUS 0xFF818583
#define OID_RT_UTILITY_GET_FRAME_DETECTION_STATUS 0xFF818584
#define OID_RT_UTILITY_GET_AGC_AND_FREQUENCY_OFFSET_ESTIMATION_STATUS \
0xFF818585
#define OID_RT_UTILITY_GET_CHANNEL_ESTIMATION_STATUS 0xFF818586
#define OID_RT_WIRELESS_MODE 0xFF818500
#define OID_RT_SUPPORTED_RATES 0xFF818501
#define OID_RT_DESIRED_RATES 0xFF818502
#define OID_RT_WIRELESS_MODE_STARTING_ADHOC 0xFF818503
#define OID_RT_GET_CONNECT_STATE 0xFF030001
#define OID_RT_RESCAN 0xFF030002
#define OID_RT_SET_KEY_LENGTH 0xFF030003
#define OID_RT_SET_DEFAULT_KEY_ID 0xFF030004
#define OID_RT_SET_CHANNEL 0xFF010182
#define OID_RT_SET_SNIFFER_MODE 0xFF010183
#define OID_RT_GET_SIGNAL_QUALITY 0xFF010184
#define OID_RT_GET_SMALL_PACKET_CRC 0xFF010185
#define OID_RT_GET_MIDDLE_PACKET_CRC 0xFF010186
#define OID_RT_GET_LARGE_PACKET_CRC 0xFF010187
#define OID_RT_GET_TX_RETRY 0xFF010188
#define OID_RT_GET_RX_RETRY 0xFF010189
#define OID_RT_PRO_SET_FW_DIG_STATE 0xFF01018A
#define OID_RT_PRO_SET_FW_RA_STATE 0xFF01018B
#define OID_RT_GET_RX_TOTAL_PACKET 0xFF010190
#define OID_RT_GET_TX_BEACON_OK 0xFF010191
#define OID_RT_GET_TX_BEACON_ERR 0xFF010192
#define OID_RT_GET_RX_ICV_ERR 0xFF010193
#define OID_RT_SET_ENCRYPTION_ALGORITHM 0xFF010194
#define OID_RT_SET_NO_AUTO_RESCAN 0xFF010195
#define OID_RT_GET_PREAMBLE_MODE 0xFF010196
#define OID_RT_GET_DRIVER_UP_DELTA_TIME 0xFF010197
#define OID_RT_GET_AP_IP 0xFF010198
#define OID_RT_GET_CHANNELPLAN 0xFF010199
#define OID_RT_SET_PREAMBLE_MODE 0xFF01019A
#define OID_RT_SET_BCN_INTVL 0xFF01019B
#define OID_RT_GET_RF_VENDER 0xFF01019C
#define OID_RT_DEDICATE_PROBE 0xFF01019D
#define OID_RT_PRO_RX_FILTER_PATTERN 0xFF01019E
#define OID_RT_GET_DCST_CURRENT_THRESHOLD 0xFF01019F
#define OID_RT_GET_CCA_ERR 0xFF0101A0
#define OID_RT_GET_CCA_UPGRADE_THRESHOLD 0xFF0101A1
#define OID_RT_GET_CCA_FALLBACK_THRESHOLD 0xFF0101A2
#define OID_RT_GET_CCA_UPGRADE_EVALUATE_TIMES 0xFF0101A3
#define OID_RT_GET_CCA_FALLBACK_EVALUATE_TIMES 0xFF0101A4
#define OID_RT_SET_RATE_ADAPTIVE 0xFF0101A5
#define OID_RT_GET_DCST_EVALUATE_PERIOD 0xFF0101A5
#define OID_RT_GET_DCST_TIME_UNIT_INDEX 0xFF0101A6
#define OID_RT_GET_TOTAL_TX_BYTES 0xFF0101A7
#define OID_RT_GET_TOTAL_RX_BYTES 0xFF0101A8
#define OID_RT_CURRENT_TX_POWER_LEVEL 0xFF0101A9
#define OID_RT_GET_ENC_KEY_MISMATCH_COUNT 0xFF0101AA
#define OID_RT_GET_ENC_KEY_MATCH_COUNT 0xFF0101AB
#define OID_RT_GET_CHANNEL 0xFF0101AC
#define OID_RT_SET_CHANNELPLAN 0xFF0101AD
#define OID_RT_GET_HARDWARE_RADIO_OFF 0xFF0101AE
#define OID_RT_CHANNELPLAN_BY_COUNTRY 0xFF0101AF
#define OID_RT_SCAN_AVAILABLE_BSSID 0xFF0101B0
#define OID_RT_GET_HARDWARE_VERSION 0xFF0101B1
#define OID_RT_GET_IS_ROAMING 0xFF0101B2
#define OID_RT_GET_IS_PRIVACY 0xFF0101B3
#define OID_RT_GET_KEY_MISMATCH 0xFF0101B4
#define OID_RT_SET_RSSI_ROAM_TRAFFIC_TH 0xFF0101B5
#define OID_RT_SET_RSSI_ROAM_SIGNAL_TH 0xFF0101B6
#define OID_RT_RESET_LOG 0xFF0101B7
#define OID_RT_GET_LOG 0xFF0101B8
#define OID_RT_SET_INDICATE_HIDDEN_AP 0xFF0101B9
#define OID_RT_GET_HEADER_FAIL 0xFF0101BA
#define OID_RT_SUPPORTED_WIRELESS_MODE 0xFF0101BB
#define OID_RT_GET_CHANNEL_LIST 0xFF0101BC
#define OID_RT_GET_SCAN_IN_PROGRESS 0xFF0101BD
#define OID_RT_GET_TX_INFO 0xFF0101BE
#define OID_RT_RF_READ_WRITE_OFFSET 0xFF0101BF
#define OID_RT_RF_READ_WRITE 0xFF0101C0
#define OID_RT_FORCED_DATA_RATE 0xFF0101C1
#define OID_RT_WIRELESS_MODE_FOR_SCAN_LIST 0xFF0101C2
#define OID_RT_GET_BSS_WIRELESS_MODE 0xFF0101C3
#define OID_RT_SCAN_WITH_MAGIC_PACKET 0xFF0101C4
#define OID_RT_PRO_RX_FILTER 0xFF0111C0
#define OID_CE_USB_WRITE_REGISTRY 0xFF0111C1
#define OID_CE_USB_READ_REGISTRY 0xFF0111C2
#define OID_RT_PRO_SET_INITIAL_GAIN 0xFF0111C3
#define OID_RT_PRO_SET_BB_RF_STANDBY_MODE 0xFF0111C4
#define OID_RT_PRO_SET_BB_RF_SHUTDOWN_MODE 0xFF0111C5
#define OID_RT_PRO_SET_TX_CHARGE_PUMP 0xFF0111C6
#define OID_RT_PRO_SET_RX_CHARGE_PUMP 0xFF0111C7
#define OID_RT_PRO_RF_WRITE_REGISTRY 0xFF0111C8
#define OID_RT_PRO_RF_READ_REGISTRY 0xFF0111C9
#define OID_RT_PRO_QUERY_RF_TYPE 0xFF0111CA
#define OID_RT_AP_GET_ASSOCIATED_STATION_LIST 0xFF010300
#define OID_RT_AP_GET_CURRENT_TIME_STAMP 0xFF010301
#define OID_RT_AP_SWITCH_INTO_AP_MODE 0xFF010302
#define OID_RT_AP_SET_DTIM_PERIOD 0xFF010303
#define OID_RT_AP_SUPPORTED 0xFF010304
#define OID_RT_AP_SET_PASSPHRASE 0xFF010305
#define OID_RT_PRO8187_WI_POLL 0xFF818780
#define OID_RT_PRO_WRITE_BB_REG 0xFF818781
#define OID_RT_PRO_READ_BB_REG 0xFF818782
#define OID_RT_PRO_WRITE_RF_REG 0xFF818783
#define OID_RT_PRO_READ_RF_REG 0xFF818784
#define OID_RT_MH_VENDER_ID 0xFFEDC100
#define OID_RT_PRO8711_JOIN_BSS 0xFF871100
#define OID_RT_PRO_READ_REGISTER 0xFF871101
#define OID_RT_PRO_WRITE_REGISTER 0xFF871102
#define OID_RT_PRO_BURST_READ_REGISTER 0xFF871103
#define OID_RT_PRO_BURST_WRITE_REGISTER 0xFF871104
#define OID_RT_PRO_WRITE_TXCMD 0xFF871105
#define OID_RT_PRO_READ16_EEPROM 0xFF871106
#define OID_RT_PRO_WRITE16_EEPROM 0xFF871107
#define OID_RT_PRO_H2C_SET_COMMAND 0xFF871108
#define OID_RT_PRO_H2C_QUERY_RESULT 0xFF871109
#define OID_RT_PRO8711_WI_POLL 0xFF87110A
#define OID_RT_PRO8711_PKT_LOSS 0xFF87110B
#define OID_RT_RD_ATTRIB_MEM 0xFF87110C
#define OID_RT_WR_ATTRIB_MEM 0xFF87110D
/*Method 2 for H2C/C2H*/
#define OID_RT_PRO_H2C_CMD_MODE 0xFF871110
#define OID_RT_PRO_H2C_CMD_RSP_MODE 0xFF871111
#define OID_RT_PRO_H2C_CMD_EVENT_MODE 0xFF871112
#define OID_RT_PRO_WAIT_C2H_EVENT 0xFF871113
#define OID_RT_PRO_RW_ACCESS_PROTOCOL_TEST 0xFF871114
#define OID_RT_PRO_SCSI_ACCESS_TEST 0xFF871115
#define OID_RT_PRO_SCSI_TCPIPOFFLOAD_OUT 0xFF871116
#define OID_RT_PRO_SCSI_TCPIPOFFLOAD_IN 0xFF871117
#define OID_RT_RRO_RX_PKT_VIA_IOCTRL 0xFF871118
#define OID_RT_RRO_RX_PKTARRAY_VIA_IOCTRL 0xFF871119
#define OID_RT_RPO_SET_PWRMGT_TEST 0xFF87111A
#define OID_RT_PRO_QRY_PWRMGT_TEST 0XFF87111B
#define OID_RT_RPO_ASYNC_RWIO_TEST 0xFF87111C
#define OID_RT_RPO_ASYNC_RWIO_POLL 0xFF87111D
#define OID_RT_PRO_SET_RF_INTFS 0xFF87111E
#define OID_RT_POLL_RX_STATUS 0xFF87111F
#define OID_RT_PRO_CFG_DEBUG_MESSAGE 0xFF871120
#define OID_RT_PRO_SET_DATA_RATE_EX 0xFF871121
#define OID_RT_PRO_SET_BASIC_RATE 0xFF871122
#define OID_RT_PRO_READ_TSSI 0xFF871123
#define OID_RT_PRO_SET_POWER_TRACKING 0xFF871124
#define OID_RT_PRO_QRY_PWRSTATE 0xFF871150
#define OID_RT_PRO_SET_PWRSTATE 0xFF871151
/*Method 2 , using workitem */
#define OID_RT_SET_READ_REG 0xFF871181
#define OID_RT_SET_WRITE_REG 0xFF871182
#define OID_RT_SET_BURST_READ_REG 0xFF871183
#define OID_RT_SET_BURST_WRITE_REG 0xFF871184
#define OID_RT_SET_WRITE_TXCMD 0xFF871185
#define OID_RT_SET_READ16_EEPROM 0xFF871186
#define OID_RT_SET_WRITE16_EEPROM 0xFF871187
#define OID_RT_QRY_POLL_WKITEM 0xFF871188
/*For SDIO INTERFACE only*/
#define OID_RT_PRO_SYNCPAGERW_SRAM 0xFF8711A0
#define OID_RT_PRO_871X_DRV_EXT 0xFF8711A1
/*For USB INTERFACE only*/
#define OID_RT_PRO_USB_VENDOR_REQ 0xFF8711B0
#define OID_RT_PRO_SCSI_AUTO_TEST 0xFF8711B1
#define OID_RT_PRO_USB_MAC_AC_FIFO_WRITE 0xFF8711B2
#define OID_RT_PRO_USB_MAC_RX_FIFO_READ 0xFF8711B3
#define OID_RT_PRO_USB_MAC_RX_FIFO_POLLING 0xFF8711B4
#define OID_RT_PRO_H2C_SET_RATE_TABLE 0xFF8711FB
#define OID_RT_PRO_H2C_GET_RATE_TABLE 0xFF8711FC
#define OID_RT_PRO_H2C_C2H_LBK_TEST 0xFF8711FE
#define OID_RT_PRO_ENCRYPTION_CTRL 0xFF871200
#define OID_RT_PRO_ADD_STA_INFO 0xFF871201
#define OID_RT_PRO_DELE_STA_INFO 0xFF871202
#define OID_RT_PRO_QUERY_DR_VARIABLE 0xFF871203
#define OID_RT_PRO_RX_PACKET_TYPE 0xFF871204
#define OID_RT_PRO_READ_EFUSE 0xFF871205
#define OID_RT_PRO_WRITE_EFUSE 0xFF871206
#define OID_RT_PRO_RW_EFUSE_PGPKT 0xFF871207
#define OID_RT_GET_EFUSE_CURRENT_SIZE 0xFF871208
#define OID_RT_SET_BANDWIDTH 0xFF871209
#define OID_RT_SET_CRYSTAL_CAP 0xFF87120A
#define OID_RT_SET_RX_PACKET_TYPE 0xFF87120B
#define OID_RT_GET_EFUSE_MAX_SIZE 0xFF87120C
#define OID_RT_PRO_SET_TX_AGC_OFFSET 0xFF87120D
#define OID_RT_PRO_SET_PKT_TEST_MODE 0xFF87120E
#define OID_RT_PRO_FOR_EVM_TEST_SETTING 0xFF87120F
#define OID_RT_PRO_GET_THERMAL_METER 0xFF871210
#define OID_RT_RESET_PHY_RX_PACKET_COUNT 0xFF871211
#define OID_RT_GET_PHY_RX_PACKET_RECEIVED 0xFF871212
#define OID_RT_GET_PHY_RX_PACKET_CRC32_ERROR 0xFF871213
#define OID_RT_SET_POWER_DOWN 0xFF871214
#define OID_RT_GET_POWER_MODE 0xFF871215
#define OID_RT_PRO_EFUSE 0xFF871216
#define OID_RT_PRO_EFUSE_MAP 0xFF871217
#endif /*#ifndef __CUSTOM_OID_H */

482
drivers/staging/rtl8712/os_intfs.c
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@ -1,482 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/******************************************************************************
* os_intfs.c
*
* Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
* Linux device driver for RTL8192SU
*
* Modifications for inclusion into the Linux staging tree are
* Copyright(c) 2010 Larry Finger. All rights reserved.
*
* Contact information:
* WLAN FAE <wlanfae@realtek.com>.
* Larry Finger <Larry.Finger@lwfinger.net>
*
******************************************************************************/
#define _OS_INTFS_C_
#include <linux/module.h>
#include <linux/kthread.h>
#include <linux/firmware.h>
#include "osdep_service.h"
#include "drv_types.h"
#include "xmit_osdep.h"
#include "recv_osdep.h"
#include "rtl871x_ioctl.h"
#include "usb_osintf.h"
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("rtl871x wireless lan driver");
MODULE_AUTHOR("Larry Finger");
static char ifname[IFNAMSIZ] = "wlan%d";
/* module param defaults */
static int chip_version = RTL8712_2ndCUT;
static int rfintfs = HWPI;
static int lbkmode = RTL8712_AIR_TRX;
static int hci = RTL8712_USB;
static int ampdu_enable = 1;/*for enable tx_ampdu*/
/* The video_mode variable is for video mode.*/
/* It may be specify when inserting module with video_mode=1 parameter.*/
static int video_mode = 1; /* enable video mode*/
/*Ndis802_11Infrastructure; infra, ad-hoc, auto*/
static int network_mode = Ndis802_11IBSS;
static int channel = 1;/*ad-hoc support requirement*/
static int wireless_mode = WIRELESS_11BG;
static int vrtl_carrier_sense = AUTO_VCS;
static int vcs_type = RTS_CTS;
static int frag_thresh = 2346;
static int preamble = PREAMBLE_LONG;/*long, short, auto*/
static int scan_mode = 1;/*active, passive*/
static int adhoc_tx_pwr = 1;
static int soft_ap;
static int smart_ps = 1;
static int power_mgnt = PS_MODE_ACTIVE;
static int radio_enable = 1;
static int long_retry_lmt = 7;
static int short_retry_lmt = 7;
static int busy_thresh = 40;
static int ack_policy = NORMAL_ACK;
static int mp_mode;
static int software_encrypt;
static int software_decrypt;
static int wmm_enable;/* default is set to disable the wmm.*/
static int uapsd_enable;
static int uapsd_max_sp = NO_LIMIT;
static int uapsd_acbk_en;
static int uapsd_acbe_en;
static int uapsd_acvi_en;
static int uapsd_acvo_en;
static int ht_enable = 1;
static int cbw40_enable = 1;
static int rf_config = RTL8712_RF_1T2R; /* 1T2R*/
static int low_power;
/* mac address to use instead of the one stored in Efuse */
char *r8712_initmac;
static char *initmac;
/* if wifi_test = 1, driver will disable the turbo mode and pass it to
* firmware private.
*/
static int wifi_test;
module_param_string(ifname, ifname, sizeof(ifname), 0644);
module_param(wifi_test, int, 0644);
module_param(initmac, charp, 0644);
module_param(video_mode, int, 0644);
module_param(chip_version, int, 0644);
module_param(rfintfs, int, 0644);
module_param(lbkmode, int, 0644);
module_param(hci, int, 0644);
module_param(network_mode, int, 0644);
module_param(channel, int, 0644);
module_param(mp_mode, int, 0644);
module_param(wmm_enable, int, 0644);
module_param(vrtl_carrier_sense, int, 0644);
module_param(vcs_type, int, 0644);
module_param(busy_thresh, int, 0644);
module_param(ht_enable, int, 0644);
module_param(cbw40_enable, int, 0644);
module_param(ampdu_enable, int, 0644);
module_param(rf_config, int, 0644);
module_param(power_mgnt, int, 0644);
module_param(low_power, int, 0644);
MODULE_PARM_DESC(ifname, " Net interface name, wlan%d=default");
MODULE_PARM_DESC(initmac, "MAC-Address, default: use FUSE");
static int netdev_open(struct net_device *pnetdev);
static int netdev_close(struct net_device *pnetdev);
static void loadparam(struct _adapter *padapter, struct net_device *pnetdev)
{
struct registry_priv *registry_par = &padapter->registrypriv;
registry_par->chip_version = (u8)chip_version;
registry_par->rfintfs = (u8)rfintfs;
registry_par->lbkmode = (u8)lbkmode;
registry_par->hci = (u8)hci;
registry_par->network_mode = (u8)network_mode;
memcpy(registry_par->ssid.Ssid, "ANY", 3);
registry_par->ssid.SsidLength = 3;
registry_par->channel = (u8)channel;
registry_par->wireless_mode = (u8)wireless_mode;
registry_par->vrtl_carrier_sense = (u8)vrtl_carrier_sense;
registry_par->vcs_type = (u8)vcs_type;
registry_par->frag_thresh = (u16)frag_thresh;
registry_par->preamble = (u8)preamble;
registry_par->scan_mode = (u8)scan_mode;
registry_par->adhoc_tx_pwr = (u8)adhoc_tx_pwr;
registry_par->soft_ap = (u8)soft_ap;
registry_par->smart_ps = (u8)smart_ps;
registry_par->power_mgnt = (u8)power_mgnt;
registry_par->radio_enable = (u8)radio_enable;
registry_par->long_retry_lmt = (u8)long_retry_lmt;
registry_par->short_retry_lmt = (u8)short_retry_lmt;
registry_par->busy_thresh = (u16)busy_thresh;
registry_par->ack_policy = (u8)ack_policy;
registry_par->mp_mode = (u8)mp_mode;
registry_par->software_encrypt = (u8)software_encrypt;
registry_par->software_decrypt = (u8)software_decrypt;
/*UAPSD*/
registry_par->wmm_enable = (u8)wmm_enable;
registry_par->uapsd_enable = (u8)uapsd_enable;
registry_par->uapsd_max_sp = (u8)uapsd_max_sp;
registry_par->uapsd_acbk_en = (u8)uapsd_acbk_en;
registry_par->uapsd_acbe_en = (u8)uapsd_acbe_en;
registry_par->uapsd_acvi_en = (u8)uapsd_acvi_en;
registry_par->uapsd_acvo_en = (u8)uapsd_acvo_en;
registry_par->ht_enable = (u8)ht_enable;
registry_par->cbw40_enable = (u8)cbw40_enable;
registry_par->ampdu_enable = (u8)ampdu_enable;
registry_par->rf_config = (u8)rf_config;
registry_par->low_power = (u8)low_power;
registry_par->wifi_test = (u8)wifi_test;
r8712_initmac = initmac;
}
static int r871x_net_set_mac_address(struct net_device *pnetdev, void *p)
{
struct _adapter *padapter = netdev_priv(pnetdev);
struct sockaddr *addr = p;
if (!padapter->bup)
eth_hw_addr_set(pnetdev, addr->sa_data);
return 0;
}
static struct net_device_stats *r871x_net_get_stats(struct net_device *pnetdev)
{
struct _adapter *padapter = netdev_priv(pnetdev);
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
struct recv_priv *precvpriv = &padapter->recvpriv;
padapter->stats.tx_packets = pxmitpriv->tx_pkts;
padapter->stats.rx_packets = precvpriv->rx_pkts;
padapter->stats.tx_dropped = pxmitpriv->tx_drop;
padapter->stats.rx_dropped = precvpriv->rx_drop;
padapter->stats.tx_bytes = pxmitpriv->tx_bytes;
padapter->stats.rx_bytes = precvpriv->rx_bytes;
return &padapter->stats;
}
static const struct net_device_ops rtl8712_netdev_ops = {
.ndo_open = netdev_open,
.ndo_stop = netdev_close,
.ndo_start_xmit = r8712_xmit_entry,
.ndo_set_mac_address = r871x_net_set_mac_address,
.ndo_get_stats = r871x_net_get_stats,
.ndo_do_ioctl = r871x_ioctl,
};
struct net_device *r8712_init_netdev(void)
{
struct _adapter *padapter;
struct net_device *pnetdev;
pnetdev = alloc_etherdev(sizeof(struct _adapter));
if (!pnetdev)
return NULL;
if (dev_alloc_name(pnetdev, ifname) < 0) {
strscpy(ifname, "wlan%d", sizeof(ifname));
dev_alloc_name(pnetdev, ifname);
}
padapter = netdev_priv(pnetdev);
padapter->pnetdev = pnetdev;
pr_info("r8712u: register rtl8712_netdev_ops to netdev_ops\n");
pnetdev->netdev_ops = &rtl8712_netdev_ops;
pnetdev->watchdog_timeo = HZ; /* 1 second timeout */
pnetdev->wireless_handlers = (struct iw_handler_def *)
&r871x_handlers_def;
loadparam(padapter, pnetdev);
netif_carrier_off(pnetdev);
padapter->pid = 0; /* Initial the PID value used for HW PBC.*/
return pnetdev;
}
static u32 start_drv_threads(struct _adapter *padapter)
{
padapter->cmd_thread = kthread_run(r8712_cmd_thread, padapter, "%s",
padapter->pnetdev->name);
if (IS_ERR(padapter->cmd_thread))
return _FAIL;
return _SUCCESS;
}
void r8712_stop_drv_threads(struct _adapter *padapter)
{
struct completion *completion =
&padapter->cmdpriv.terminate_cmdthread_comp;
/*Below is to terminate r8712_cmd_thread & event_thread...*/
complete(&padapter->cmdpriv.cmd_queue_comp);
if (padapter->cmd_thread)
wait_for_completion_interruptible(completion);
padapter->cmdpriv.cmd_seq = 1;
}
static void start_drv_timers(struct _adapter *padapter)
{
mod_timer(&padapter->mlmepriv.sitesurveyctrl.sitesurvey_ctrl_timer,
jiffies + msecs_to_jiffies(5000));
mod_timer(&padapter->mlmepriv.wdg_timer,
jiffies + msecs_to_jiffies(2000));
}
void r8712_stop_drv_timers(struct _adapter *padapter)
{
del_timer_sync(&padapter->mlmepriv.assoc_timer);
del_timer_sync(&padapter->securitypriv.tkip_timer);
del_timer_sync(&padapter->mlmepriv.scan_to_timer);
del_timer_sync(&padapter->mlmepriv.dhcp_timer);
del_timer_sync(&padapter->mlmepriv.wdg_timer);
del_timer_sync(&padapter->mlmepriv.sitesurveyctrl.sitesurvey_ctrl_timer);
}
static void init_default_value(struct _adapter *padapter)
{
struct registry_priv *pregistrypriv = &padapter->registrypriv;
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct security_priv *psecuritypriv = &padapter->securitypriv;
/*xmit_priv*/
pxmitpriv->vcs_setting = pregistrypriv->vrtl_carrier_sense;
pxmitpriv->vcs = pregistrypriv->vcs_type;
pxmitpriv->vcs_type = pregistrypriv->vcs_type;
pxmitpriv->rts_thresh = pregistrypriv->rts_thresh;
pxmitpriv->frag_len = pregistrypriv->frag_thresh;
/* mlme_priv */
/* Maybe someday we should rename this variable to "active_mode"(Jeff)*/
pmlmepriv->passive_mode = 1; /* 1: active, 0: passive. */
/*ht_priv*/
{
int i;
struct ht_priv *phtpriv = &pmlmepriv->htpriv;
phtpriv->ampdu_enable = false;/*set to disabled*/
for (i = 0; i < 16; i++)
phtpriv->baddbareq_issued[i] = false;
}
/*security_priv*/
psecuritypriv->sw_encrypt = pregistrypriv->software_encrypt;
psecuritypriv->sw_decrypt = pregistrypriv->software_decrypt;
psecuritypriv->binstallGrpkey = _FAIL;
/*pwrctrl_priv*/
/*registry_priv*/
r8712_init_registrypriv_dev_network(padapter);
r8712_update_registrypriv_dev_network(padapter);
/*misc.*/
}
int r8712_init_drv_sw(struct _adapter *padapter)
{
int ret;
ret = r8712_init_cmd_priv(&padapter->cmdpriv);
if (ret)
return ret;
padapter->cmdpriv.padapter = padapter;
ret = r8712_init_evt_priv(&padapter->evtpriv);
if (ret)
goto free_cmd;
ret = r8712_init_mlme_priv(padapter);
if (ret)
goto free_evt;
ret = _r8712_init_xmit_priv(&padapter->xmitpriv, padapter);
if (ret)
goto free_mlme;
ret = _r8712_init_recv_priv(&padapter->recvpriv, padapter);
if (ret)
goto free_xmit;
memset((unsigned char *)&padapter->securitypriv, 0,
sizeof(struct security_priv));
timer_setup(&padapter->securitypriv.tkip_timer,
r8712_use_tkipkey_handler, 0);
ret = _r8712_init_sta_priv(&padapter->stapriv);
if (ret)
goto free_recv;
padapter->stapriv.padapter = padapter;
r8712_init_bcmc_stainfo(padapter);
r8712_init_pwrctrl_priv(padapter);
mp871xinit(padapter);
init_default_value(padapter);
r8712_InitSwLeds(padapter);
mutex_init(&padapter->mutex_start);
return 0;
free_recv:
_r8712_free_recv_priv(&padapter->recvpriv);
free_xmit:
_free_xmit_priv(&padapter->xmitpriv);
free_mlme:
r8712_free_mlme_priv(&padapter->mlmepriv);
free_evt:
r8712_free_evt_priv(&padapter->evtpriv);
free_cmd:
r8712_free_cmd_priv(&padapter->cmdpriv);
return ret;
}
void r8712_free_drv_sw(struct _adapter *padapter)
{
r8712_free_cmd_priv(&padapter->cmdpriv);
r8712_free_evt_priv(&padapter->evtpriv);
r8712_DeInitSwLeds(padapter);
r8712_free_mlme_priv(&padapter->mlmepriv);
_free_xmit_priv(&padapter->xmitpriv);
_r8712_free_sta_priv(&padapter->stapriv);
_r8712_free_recv_priv(&padapter->recvpriv);
mp871xdeinit(padapter);
}
static void enable_video_mode(struct _adapter *padapter, int cbw40_value)
{
/* bit 8:
* 1 -> enable video mode to 96B AP
* 0 -> disable video mode to 96B AP
* bit 9:
* 1 -> enable 40MHz mode
* 0 -> disable 40MHz mode
* bit 10:
* 1 -> enable STBC
* 0 -> disable STBC
*/
u32 intcmd = 0xf4000500; /* enable bit8, bit10*/
if (cbw40_value) {
/* if the driver supports the 40M bandwidth,
* we can enable the bit 9.
*/
intcmd |= 0x200;
}
r8712_fw_cmd(padapter, intcmd);
}
/*
*
* This function intends to handle the activation of an interface
* i.e. when it is brought Up/Active from a Down state.
*
*/
static int netdev_open(struct net_device *pnetdev)
{
struct _adapter *padapter = netdev_priv(pnetdev);
mutex_lock(&padapter->mutex_start);
if (!padapter->bup) {
padapter->driver_stopped = false;
padapter->surprise_removed = false;
padapter->bup = true;
if (rtl871x_hal_init(padapter) != _SUCCESS)
goto netdev_open_error;
if (!r8712_initmac) {
/* Use the mac address stored in the Efuse */
eth_hw_addr_set(pnetdev,
padapter->eeprompriv.mac_addr);
} else {
/* We have to inform f/w to use user-supplied MAC
* address.
*/
msleep(200);
r8712_setMacAddr_cmd(padapter,
(const u8 *)pnetdev->dev_addr);
/*
* The "myid" function will get the wifi mac address
* from eeprompriv structure instead of netdev
* structure. So, we have to overwrite the mac_addr
* stored in the eeprompriv structure. In this case,
* the real mac address won't be used anymore. So that,
* the eeprompriv.mac_addr should store the mac which
* users specify.
*/
memcpy(padapter->eeprompriv.mac_addr,
pnetdev->dev_addr, ETH_ALEN);
}
if (start_drv_threads(padapter) != _SUCCESS)
goto netdev_open_error;
if (!padapter->dvobjpriv.inirp_init)
goto netdev_open_error;
else
padapter->dvobjpriv.inirp_init(padapter);
r8712_set_ps_mode(padapter, padapter->registrypriv.power_mgnt,
padapter->registrypriv.smart_ps);
}
if (!netif_queue_stopped(pnetdev))
netif_start_queue(pnetdev);
else
netif_wake_queue(pnetdev);
if (video_mode)
enable_video_mode(padapter, cbw40_enable);
/* start driver mlme relation timer */
start_drv_timers(padapter);
padapter->ledpriv.LedControlHandler(padapter, LED_CTL_NO_LINK);
mutex_unlock(&padapter->mutex_start);
return 0;
netdev_open_error:
padapter->bup = false;
netif_carrier_off(pnetdev);
netif_stop_queue(pnetdev);
mutex_unlock(&padapter->mutex_start);
return -1;
}
/*
*
* This function intends to handle the shutdown of an interface
* i.e. when it is brought Down from an Up/Active state.
*
*/
static int netdev_close(struct net_device *pnetdev)
{
struct _adapter *padapter = netdev_priv(pnetdev);
/* Close LED*/
padapter->ledpriv.LedControlHandler(padapter, LED_CTL_POWER_OFF);
msleep(200);
/*s1.*/
if (pnetdev) {
if (!netif_queue_stopped(pnetdev))
netif_stop_queue(pnetdev);
}
/*s2.*/
/*s2-1. issue disassoc_cmd to fw*/
r8712_disassoc_cmd(padapter);
/*s2-2. indicate disconnect to os*/
r8712_ind_disconnect(padapter);
/*s2-3.*/
r8712_free_assoc_resources(padapter);
/*s2-4.*/
r8712_free_network_queue(padapter);
return 0;
}
#include "mlme_osdep.h"

32
drivers/staging/rtl8712/osdep_intf.h
View File

@ -1,32 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
*
* Modifications for inclusion into the Linux staging tree are
* Copyright(c) 2010 Larry Finger. All rights reserved.
*
* Contact information:
* WLAN FAE <wlanfae@realtek.com>
* Larry Finger <Larry.Finger@lwfinger.net>
*
******************************************************************************/
#ifndef __OSDEP_INTF_H_
#define __OSDEP_INTF_H_
#include "osdep_service.h"
#include "drv_types.h"
#define RND4(x) (((x >> 2) + ((x & 3) != 0)) << 2)
struct intf_priv {
u8 *intf_dev;
/* when in USB, IO is through interrupt in/out endpoints */
struct usb_device *udev;
struct urb *piorw_urb;
struct completion io_retevt_comp;
};
int r871x_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
#endif /*_OSDEP_INTF_H_*/

60
drivers/staging/rtl8712/osdep_service.h
View File

@ -1,60 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
*
* Modifications for inclusion into the Linux staging tree are
* Copyright(c) 2010 Larry Finger. All rights reserved.
*
* Contact information:
* WLAN FAE <wlanfae@realtek.com>
* Larry Finger <Larry.Finger@lwfinger.net>
*
******************************************************************************/
#ifndef __OSDEP_SERVICE_H_
#define __OSDEP_SERVICE_H_
#define _SUCCESS 1
#define _FAIL 0
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/semaphore.h>
#include <linux/sched/signal.h>
#include <linux/sem.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <net/iw_handler.h>
#include <linux/proc_fs.h> /* Necessary because we use the proc fs */
#include "basic_types.h"
struct __queue {
struct list_head queue;
spinlock_t lock;
};
#define _pkt struct sk_buff
#define _buffer unsigned char
#define _init_queue(pqueue) \
do { \
INIT_LIST_HEAD(&((pqueue)->queue)); \
spin_lock_init(&((pqueue)->lock)); \
} while (0)
static inline u32 end_of_queue_search(struct list_head *head,
struct list_head *plist)
{
return (head == plist);
}
static inline void flush_signals_thread(void)
{
if (signal_pending(current))
flush_signals(current);
}
#endif

139
drivers/staging/rtl8712/recv_linux.c
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@ -1,139 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/******************************************************************************
* recv_linux.c
*
* Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
* Linux device driver for RTL8192SU
*
* Modifications for inclusion into the Linux staging tree are
* Copyright(c) 2010 Larry Finger. All rights reserved.
*
* Contact information:
* WLAN FAE <wlanfae@realtek.com>.
* Larry Finger <Larry.Finger@lwfinger.net>
*
******************************************************************************/
#define _RECV_OSDEP_C_
#include <linux/usb.h>
#include "osdep_service.h"
#include "drv_types.h"
#include "wifi.h"
#include "recv_osdep.h"
#include "osdep_intf.h"
#include "ethernet.h"
#include <linux/if_arp.h>
#include "usb_ops.h"
/*init os related resource in struct recv_priv*/
/*alloc os related resource in union recv_frame*/
void r8712_os_recv_resource_alloc(struct _adapter *padapter,
union recv_frame *precvframe)
{
precvframe->u.hdr.pkt_newalloc = NULL;
precvframe->u.hdr.pkt = NULL;
}
/*alloc os related resource in struct recv_buf*/
int r8712_os_recvbuf_resource_alloc(struct _adapter *padapter,
struct recv_buf *precvbuf)
{
int res = 0;
precvbuf->irp_pending = false;
precvbuf->purb = usb_alloc_urb(0, GFP_KERNEL);
if (!precvbuf->purb)
res = -ENOMEM;
precvbuf->pskb = NULL;
precvbuf->pallocated_buf = NULL;
precvbuf->pbuf = NULL;
precvbuf->pdata = NULL;
precvbuf->phead = NULL;
precvbuf->ptail = NULL;
precvbuf->pend = NULL;
precvbuf->transfer_len = 0;
precvbuf->len = 0;
return res;
}
/*free os related resource in struct recv_buf*/
void r8712_os_recvbuf_resource_free(struct _adapter *padapter,
struct recv_buf *precvbuf)
{
if (precvbuf->pskb)
dev_kfree_skb_any(precvbuf->pskb);
if (precvbuf->purb) {
usb_kill_urb(precvbuf->purb);
usb_free_urb(precvbuf->purb);
}
}
void r8712_handle_tkip_mic_err(struct _adapter *adapter, u8 bgroup)
{
union iwreq_data wrqu;
struct iw_michaelmicfailure ev;
struct mlme_priv *mlmepriv = &adapter->mlmepriv;
memset(&ev, 0x00, sizeof(ev));
if (bgroup)
ev.flags |= IW_MICFAILURE_GROUP;
else
ev.flags |= IW_MICFAILURE_PAIRWISE;
ev.src_addr.sa_family = ARPHRD_ETHER;
ether_addr_copy(ev.src_addr.sa_data, &mlmepriv->assoc_bssid[0]);
memset(&wrqu, 0x00, sizeof(wrqu));
wrqu.data.length = sizeof(ev);
wireless_send_event(adapter->pnetdev, IWEVMICHAELMICFAILURE, &wrqu,
(char *)&ev);
}
void r8712_recv_indicatepkt(struct _adapter *adapter,
union recv_frame *recvframe)
{
struct recv_priv *recvpriv;
struct __queue *free_recv_queue;
_pkt *skb;
struct rx_pkt_attrib *attrib = &recvframe->u.hdr.attrib;
recvpriv = &adapter->recvpriv;
free_recv_queue = &recvpriv->free_recv_queue;
skb = recvframe->u.hdr.pkt;
if (!skb)
goto _recv_indicatepkt_drop;
skb->data = recvframe->u.hdr.rx_data;
skb->len = recvframe->u.hdr.len;
skb_set_tail_pointer(skb, skb->len);
if ((attrib->tcpchk_valid == 1) && (attrib->tcp_chkrpt == 1))
skb->ip_summed = CHECKSUM_UNNECESSARY;
else
skb->ip_summed = CHECKSUM_NONE;
skb->dev = adapter->pnetdev;
skb->protocol = eth_type_trans(skb, adapter->pnetdev);
netif_rx(skb);
recvframe->u.hdr.pkt = NULL; /* pointers to NULL before
* r8712_free_recvframe()
*/
r8712_free_recvframe(recvframe, free_recv_queue);
return;
_recv_indicatepkt_drop:
/*enqueue back to free_recv_queue*/
if (recvframe)
r8712_free_recvframe(recvframe, free_recv_queue);
recvpriv->rx_drop++;
}
static void _r8712_reordering_ctrl_timeout_handler (struct timer_list *t)
{
struct recv_reorder_ctrl *reorder_ctrl =
from_timer(reorder_ctrl, t, reordering_ctrl_timer);
r8712_reordering_ctrl_timeout_handler(reorder_ctrl);
}
void r8712_init_recv_timer(struct recv_reorder_ctrl *preorder_ctrl)
{
timer_setup(&preorder_ctrl->reordering_ctrl_timer,
_r8712_reordering_ctrl_timeout_handler, 0);
}

39
drivers/staging/rtl8712/recv_osdep.h
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@ -1,39 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
*
* Modifications for inclusion into the Linux staging tree are
* Copyright(c) 2010 Larry Finger. All rights reserved.
*
* Contact information:
* WLAN FAE <wlanfae@realtek.com>
* Larry Finger <Larry.Finger@lwfinger.net>
*
******************************************************************************/
#ifndef __RECV_OSDEP_H_
#define __RECV_OSDEP_H_
#include "osdep_service.h"
#include "drv_types.h"
#include <linux/skbuff.h>
int _r8712_init_recv_priv(struct recv_priv *precvpriv,
struct _adapter *padapter);
void _r8712_free_recv_priv(struct recv_priv *precvpriv);
void r8712_recv_entry(union recv_frame *precv_frame);
void r8712_recv_indicatepkt(struct _adapter *adapter,
union recv_frame *precv_frame);
void r8712_handle_tkip_mic_err(struct _adapter *padapter, u8 bgroup);
int r8712_init_recv_priv(struct recv_priv *precvpriv,
struct _adapter *padapter);
void r8712_free_recv_priv(struct recv_priv *precvpriv);
void r8712_os_recv_resource_alloc(struct _adapter *padapter,
union recv_frame *precvframe);
int r8712_os_recvbuf_resource_alloc(struct _adapter *padapter,
struct recv_buf *precvbuf);
void r8712_os_recvbuf_resource_free(struct _adapter *padapter,
struct recv_buf *precvbuf);
void r8712_init_recv_timer(struct recv_reorder_ctrl *preorder_ctrl);
#endif

26
drivers/staging/rtl8712/rtl8712_bitdef.h
View File

@ -1,26 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
*
******************************************************************************/
#ifndef __RTL8712_BITDEF_H__
#define __RTL8712_BITDEF_H__
#include "rtl8712_cmdctrl_bitdef.h"
#include "rtl8712_syscfg_bitdef.h"
#include "rtl8712_macsetting_bitdef.h"
#include "rtl8712_timectrl_bitdef.h"
#include "rtl8712_fifoctrl_bitdef.h"
#include "rtl8712_ratectrl_bitdef.h"
#include "rtl8712_edcasetting_bitdef.h"
#include "rtl8712_wmac_bitdef.h"
#include "rtl8712_security_bitdef.h"
#include "rtl8712_powersave_bitdef.h"
#include "rtl8712_gp_bitdef.h"
#include "rtl8712_interrupt_bitdef.h"
#include "rtl8712_debugctrl_bitdef.h"
#endif /* __RTL8712_BITDEF_H__ */

409
drivers/staging/rtl8712/rtl8712_cmd.c
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@ -1,409 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/******************************************************************************
* rtl8712_cmd.c
*
* Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
* Linux device driver for RTL8192SU
*
* Modifications for inclusion into the Linux staging tree are
* Copyright(c) 2010 Larry Finger. All rights reserved.
*
* Contact information:
* WLAN FAE <wlanfae@realtek.com>.
* Larry Finger <Larry.Finger@lwfinger.net>
*
******************************************************************************/
#define _RTL8712_CMD_C_
#include <linux/compiler.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/slab.h>
#include <linux/sched/signal.h>
#include <linux/module.h>
#include <linux/kref.h>
#include <linux/netdevice.h>
#include <linux/skbuff.h>
#include <linux/usb.h>
#include <linux/usb/ch9.h>
#include <linux/circ_buf.h>
#include <linux/uaccess.h>
#include <asm/byteorder.h>
#include <linux/atomic.h>
#include <linux/semaphore.h>
#include <linux/rtnetlink.h>
#include "osdep_service.h"
#include "drv_types.h"
#include "recv_osdep.h"
#include "mlme_osdep.h"
#include "rtl871x_ioctl_set.h"
static void check_hw_pbc(struct _adapter *padapter)
{
u8 tmp1byte;
r8712_write8(padapter, MAC_PINMUX_CTRL, (GPIOMUX_EN | GPIOSEL_GPIO));
tmp1byte = r8712_read8(padapter, GPIO_IO_SEL);
tmp1byte &= ~(HAL_8192S_HW_GPIO_WPS_BIT);
r8712_write8(padapter, GPIO_IO_SEL, tmp1byte);
tmp1byte = r8712_read8(padapter, GPIO_CTRL);
if (tmp1byte == 0xff)
return;
if (tmp1byte & HAL_8192S_HW_GPIO_WPS_BIT) {
/* Here we only set bPbcPressed to true
* After trigger PBC, the variable will be set to false
*/
netdev_dbg(padapter->pnetdev, "CheckPbcGPIO - PBC is pressed !!!!\n");
/* 0 is the default value and it means the application monitors
* the HW PBC doesn't provide its pid to driver.
*/
if (padapter->pid == 0)
return;
kill_pid(find_vpid(padapter->pid), SIGUSR1, 1);
}
}
/* query rx phy status from fw.
* Adhoc mode: beacon.
* Infrastructure mode: beacon , data.
*/
static void query_fw_rx_phy_status(struct _adapter *padapter)
{
u32 val32 = 0;
int pollingcnts = 50;
if (check_fwstate(&padapter->mlmepriv, _FW_LINKED)) {
r8712_write32(padapter, IOCMD_CTRL_REG, 0xf4000001);
msleep(100);
/* Wait FW complete IO Cmd */
while ((r8712_read32(padapter, IOCMD_CTRL_REG)) &&
(pollingcnts > 0)) {
pollingcnts--;
msleep(20);
}
if (pollingcnts != 0)
val32 = r8712_read32(padapter, IOCMD_DATA_REG);
else /* time out */
val32 = 0;
val32 >>= 4;
padapter->recvpriv.fw_rssi =
(u8)r8712_signal_scale_mapping(val32);
}
}
/* check mlme, hw, phy, or dynamic algorithm status. */
static void StatusWatchdogCallback(struct _adapter *padapter)
{
check_hw_pbc(padapter);
query_fw_rx_phy_status(padapter);
}
static void r871x_internal_cmd_hdl(struct _adapter *padapter, u8 *pbuf)
{
struct drvint_cmd_parm *pdrvcmd;
if (!pbuf)
return;
pdrvcmd = (struct drvint_cmd_parm *)pbuf;
switch (pdrvcmd->i_cid) {
case WDG_WK_CID:
StatusWatchdogCallback(padapter);
break;
default:
break;
}
kfree(pdrvcmd->pbuf);
}
static u8 read_bbreg_hdl(struct _adapter *padapter, u8 *pbuf)
{
struct cmd_obj *pcmd = (struct cmd_obj *)pbuf;
r8712_free_cmd_obj(pcmd);
return H2C_SUCCESS;
}
static u8 write_bbreg_hdl(struct _adapter *padapter, u8 *pbuf)
{
void (*pcmd_callback)(struct _adapter *dev, struct cmd_obj *pcmd);
struct cmd_obj *pcmd = (struct cmd_obj *)pbuf;
pcmd_callback = cmd_callback[pcmd->cmdcode].callback;
if (!pcmd_callback)
r8712_free_cmd_obj(pcmd);
else
pcmd_callback(padapter, pcmd);
return H2C_SUCCESS;
}
static u8 read_rfreg_hdl(struct _adapter *padapter, u8 *pbuf)
{
u32 val;
void (*pcmd_callback)(struct _adapter *dev, struct cmd_obj *pcmd);
struct cmd_obj *pcmd = (struct cmd_obj *)pbuf;
if (pcmd->rsp && pcmd->rspsz > 0)
memcpy(pcmd->rsp, (u8 *)&val, pcmd->rspsz);
pcmd_callback = cmd_callback[pcmd->cmdcode].callback;
if (!pcmd_callback)
r8712_free_cmd_obj(pcmd);
else
pcmd_callback(padapter, pcmd);
return H2C_SUCCESS;
}
static u8 write_rfreg_hdl(struct _adapter *padapter, u8 *pbuf)
{
void (*pcmd_callback)(struct _adapter *dev, struct cmd_obj *pcmd);
struct cmd_obj *pcmd = (struct cmd_obj *)pbuf;
pcmd_callback = cmd_callback[pcmd->cmdcode].callback;
if (!pcmd_callback)
r8712_free_cmd_obj(pcmd);
else
pcmd_callback(padapter, pcmd);
return H2C_SUCCESS;
}
static u8 sys_suspend_hdl(struct _adapter *padapter, u8 *pbuf)
{
struct cmd_obj *pcmd = (struct cmd_obj *)pbuf;
r8712_free_cmd_obj(pcmd);
return H2C_SUCCESS;
}
static struct cmd_obj *cmd_hdl_filter(struct _adapter *padapter,
struct cmd_obj *pcmd)
{
struct cmd_obj *pcmd_r;
if (!pcmd)
return pcmd;
pcmd_r = NULL;
switch (pcmd->cmdcode) {
case GEN_CMD_CODE(_Read_BBREG):
read_bbreg_hdl(padapter, (u8 *)pcmd);
break;
case GEN_CMD_CODE(_Write_BBREG):
write_bbreg_hdl(padapter, (u8 *)pcmd);
break;
case GEN_CMD_CODE(_Read_RFREG):
read_rfreg_hdl(padapter, (u8 *)pcmd);
break;
case GEN_CMD_CODE(_Write_RFREG):
write_rfreg_hdl(padapter, (u8 *)pcmd);
break;
case GEN_CMD_CODE(_SetUsbSuspend):
sys_suspend_hdl(padapter, (u8 *)pcmd);
break;
case GEN_CMD_CODE(_JoinBss):
r8712_joinbss_reset(padapter);
/* Before set JoinBss_CMD to FW, driver must ensure FW is in
* PS_MODE_ACTIVE. Directly write rpwm to radio on and assign
* new pwr_mode to Driver, instead of use workitem to change
* state.
*/
if (padapter->pwrctrlpriv.pwr_mode > PS_MODE_ACTIVE) {
padapter->pwrctrlpriv.pwr_mode = PS_MODE_ACTIVE;
mutex_lock(&padapter->pwrctrlpriv.mutex_lock);
r8712_set_rpwm(padapter, PS_STATE_S4);
mutex_unlock(&padapter->pwrctrlpriv.mutex_lock);
}
pcmd_r = pcmd;
break;
case _DRV_INT_CMD_:
r871x_internal_cmd_hdl(padapter, pcmd->parmbuf);
r8712_free_cmd_obj(pcmd);
pcmd_r = NULL;
break;
default:
pcmd_r = pcmd;
break;
}
return pcmd_r; /* if returning pcmd_r == NULL, pcmd must be free. */
}
u8 r8712_fw_cmd(struct _adapter *pAdapter, u32 cmd)
{
int pollingcnts = 50;
r8712_write32(pAdapter, IOCMD_CTRL_REG, cmd);
msleep(100);
while ((r8712_read32(pAdapter, IOCMD_CTRL_REG != 0)) &&
(pollingcnts > 0)) {
pollingcnts--;
msleep(20);
}
if (pollingcnts == 0)
return false;
return true;
}
void r8712_fw_cmd_data(struct _adapter *pAdapter, u32 *value, u8 flag)
{
if (flag == 0) /* set */
r8712_write32(pAdapter, IOCMD_DATA_REG, *value);
else /* query */
*value = r8712_read32(pAdapter, IOCMD_DATA_REG);
}
int r8712_cmd_thread(void *context)
{
struct cmd_obj *pcmd;
unsigned int cmdsz, wr_sz;
__le32 *pcmdbuf;
struct tx_desc *pdesc;
void (*pcmd_callback)(struct _adapter *dev, struct cmd_obj *pcmd);
struct _adapter *padapter = context;
struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
struct completion *cmd_queue_comp =
&pcmdpriv->cmd_queue_comp;
struct mutex *pwctrl_lock = &padapter->pwrctrlpriv.mutex_lock;
allow_signal(SIGTERM);
while (1) {
if (wait_for_completion_interruptible(cmd_queue_comp))
break;
if (padapter->driver_stopped || padapter->surprise_removed)
break;
if (r8712_register_cmd_alive(padapter))
continue;
_next:
pcmd = r8712_dequeue_cmd(&pcmdpriv->cmd_queue);
if (!(pcmd)) {
r8712_unregister_cmd_alive(padapter);
continue;
}
pcmdbuf = (__le32 *)pcmdpriv->cmd_buf;
pdesc = (struct tx_desc *)pcmdbuf;
memset(pdesc, 0, TXDESC_SIZE);
pcmd = cmd_hdl_filter(padapter, pcmd);
if (pcmd) { /* if pcmd != NULL, cmd will be handled by f/w */
struct dvobj_priv *pdvobj = &padapter->dvobjpriv;
u8 blnPending = 0;
u16 cmdcode = pcmd->cmdcode;
pcmdpriv->cmd_issued_cnt++;
cmdsz = round_up(pcmd->cmdsz, 8);
wr_sz = TXDESC_SIZE + 8 + cmdsz;
pdesc->txdw0 |= cpu_to_le32((wr_sz - TXDESC_SIZE) &
0x0000ffff);
if (pdvobj->ishighspeed) {
if ((wr_sz % 512) == 0)
blnPending = 1;
} else {
if ((wr_sz % 64) == 0)
blnPending = 1;
}
if (blnPending) { /* 32 bytes for TX Desc - 8 offset */
pdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE +
OFFSET_SZ + 8) << OFFSET_SHT) &
0x00ff0000);
} else {
pdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE +
OFFSET_SZ) <<
OFFSET_SHT) &
0x00ff0000);
}
pdesc->txdw0 |= cpu_to_le32(OWN | FSG | LSG);
pdesc->txdw1 |= cpu_to_le32((0x13 << QSEL_SHT) &
0x00001f00);
pcmdbuf += (TXDESC_SIZE >> 2);
*pcmdbuf = cpu_to_le32((cmdsz & 0x0000ffff) |
(pcmd->cmdcode << 16) |
(pcmdpriv->cmd_seq << 24));
pcmdbuf += 2; /* 8 bytes alignment */
memcpy((u8 *)pcmdbuf, pcmd->parmbuf, pcmd->cmdsz);
if (blnPending)
wr_sz += 8; /* Append 8 bytes */
r8712_write_mem(padapter, RTL8712_DMA_H2CCMD, wr_sz,
(u8 *)pdesc);
pcmdpriv->cmd_seq++;
if (cmdcode == GEN_CMD_CODE(_CreateBss)) {
pcmd->res = H2C_SUCCESS;
pcmd_callback = cmd_callback[cmdcode].callback;
if (pcmd_callback)
pcmd_callback(padapter, pcmd);
continue;
}
if (cmdcode == GEN_CMD_CODE(_SetPwrMode)) {
if (padapter->pwrctrlpriv.bSleep) {
mutex_lock(pwctrl_lock);
r8712_set_rpwm(padapter, PS_STATE_S2);
mutex_unlock(pwctrl_lock);
}
}
r8712_free_cmd_obj(pcmd);
if (list_empty(&pcmdpriv->cmd_queue.queue)) {
r8712_unregister_cmd_alive(padapter);
continue;
} else {
goto _next;
}
} else {
goto _next;
}
flush_signals_thread();
}
/* free all cmd_obj resources */
do {
pcmd = r8712_dequeue_cmd(&pcmdpriv->cmd_queue);
if (!pcmd)
break;
r8712_free_cmd_obj(pcmd);
} while (1);
complete(&pcmdpriv->terminate_cmdthread_comp);
return 0;
}
void r8712_event_handle(struct _adapter *padapter, __le32 *peventbuf)
{
u8 evt_code, evt_seq;
u16 evt_sz;
void (*event_callback)(struct _adapter *dev, u8 *pbuf);
struct evt_priv *pevt_priv = &padapter->evtpriv;
if (!peventbuf)
goto _abort_event_;
evt_sz = (u16)(le32_to_cpu(*peventbuf) & 0xffff);
evt_seq = (u8)((le32_to_cpu(*peventbuf) >> 24) & 0x7f);
evt_code = (u8)((le32_to_cpu(*peventbuf) >> 16) & 0xff);
/* checking event sequence... */
if ((evt_seq & 0x7f) != pevt_priv->event_seq) {
pevt_priv->event_seq = ((evt_seq + 1) & 0x7f);
goto _abort_event_;
}
/* checking if event code is valid */
if (evt_code >= MAX_C2HEVT) {
pevt_priv->event_seq = ((evt_seq + 1) & 0x7f);
goto _abort_event_;
} else if ((evt_code == GEN_EVT_CODE(_Survey)) &&
(evt_sz > sizeof(struct wlan_bssid_ex))) {
pevt_priv->event_seq = ((evt_seq + 1) & 0x7f);
goto _abort_event_;
}
/* checking if event size match the event parm size */
if ((wlanevents[evt_code].parmsize) &&
(wlanevents[evt_code].parmsize != evt_sz)) {
pevt_priv->event_seq = ((evt_seq + 1) & 0x7f);
goto _abort_event_;
} else if ((evt_sz == 0) && (evt_code != GEN_EVT_CODE(_WPS_PBC))) {
pevt_priv->event_seq = ((evt_seq + 1) & 0x7f);
goto _abort_event_;
}
pevt_priv->event_seq++; /* update evt_seq */
if (pevt_priv->event_seq > 127)
pevt_priv->event_seq = 0;
/* move to event content, 8 bytes alignment */
peventbuf = peventbuf + 2;
event_callback = wlanevents[evt_code].event_callback;
if (event_callback)
event_callback(padapter, (u8 *)peventbuf);
pevt_priv->evt_done_cnt++;
_abort_event_:
return;
}

231
drivers/staging/rtl8712/rtl8712_cmd.h
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@ -1,231 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
*
* Modifications for inclusion into the Linux staging tree are
* Copyright(c) 2010 Larry Finger. All rights reserved.
*
* Contact information:
* WLAN FAE <wlanfae@realtek.com>
* Larry Finger <Larry.Finger@lwfinger.net>
*
******************************************************************************/
#ifndef __RTL8712_CMD_H_
#define __RTL8712_CMD_H_
#define CMD_HDR_SZ 8
u8 r8712_fw_cmd(struct _adapter *pAdapter, u32 cmd);
void r8712_fw_cmd_data(struct _adapter *pAdapter, u32 *value, u8 flag);
struct cmd_hdr {
u32 cmd_dw0;
u32 cmd_dw1;
};
enum rtl8712_h2c_cmd {
GEN_CMD_CODE(_Read_MACREG), /*0*/
GEN_CMD_CODE(_Write_MACREG),
GEN_CMD_CODE(_Read_BBREG),
GEN_CMD_CODE(_Write_BBREG),
GEN_CMD_CODE(_Read_RFREG),
GEN_CMD_CODE(_Write_RFREG), /*5*/
GEN_CMD_CODE(_Read_EEPROM),
GEN_CMD_CODE(_Write_EEPROM),
GEN_CMD_CODE(_Read_EFUSE),
GEN_CMD_CODE(_Write_EFUSE),
GEN_CMD_CODE(_Read_CAM), /*10*/
GEN_CMD_CODE(_Write_CAM),
GEN_CMD_CODE(_setBCNITV),
GEN_CMD_CODE(_setMBIDCFG),
GEN_CMD_CODE(_JoinBss), /*14*/
GEN_CMD_CODE(_DisConnect), /*15*/
GEN_CMD_CODE(_CreateBss),
GEN_CMD_CODE(_SetOpMode),
GEN_CMD_CODE(_SiteSurvey), /*18*/
GEN_CMD_CODE(_SetAuth),
GEN_CMD_CODE(_SetKey), /*20*/
GEN_CMD_CODE(_SetStaKey),
GEN_CMD_CODE(_SetAssocSta),
GEN_CMD_CODE(_DelAssocSta),
GEN_CMD_CODE(_SetStaPwrState),
GEN_CMD_CODE(_SetBasicRate), /*25*/
GEN_CMD_CODE(_GetBasicRate),
GEN_CMD_CODE(_SetDataRate),
GEN_CMD_CODE(_GetDataRate),
GEN_CMD_CODE(_SetPhyInfo),
GEN_CMD_CODE(_GetPhyInfo), /*30*/
GEN_CMD_CODE(_SetPhy),
GEN_CMD_CODE(_GetPhy),
GEN_CMD_CODE(_readRssi),
GEN_CMD_CODE(_readGain),
GEN_CMD_CODE(_SetAtim), /*35*/
GEN_CMD_CODE(_SetPwrMode),
GEN_CMD_CODE(_JoinbssRpt),
GEN_CMD_CODE(_SetRaTable),
GEN_CMD_CODE(_GetRaTable),
GEN_CMD_CODE(_GetCCXReport), /*40*/
GEN_CMD_CODE(_GetDTMReport),
GEN_CMD_CODE(_GetTXRateStatistics),
GEN_CMD_CODE(_SetUsbSuspend),
GEN_CMD_CODE(_SetH2cLbk),
GEN_CMD_CODE(_AddBAReq), /*45*/
GEN_CMD_CODE(_SetChannel), /*46*/
/* MP_OFFLOAD Start (47~54)*/
GEN_CMD_CODE(_SetTxPower),
GEN_CMD_CODE(_SwitchAntenna),
GEN_CMD_CODE(_SetCrystalCap),
GEN_CMD_CODE(_SetSingleCarrierTx), /*50*/
GEN_CMD_CODE(_SetSingleToneTx),
GEN_CMD_CODE(_SetCarrierSuppressionTx),
GEN_CMD_CODE(_SetContinuousTx),
GEN_CMD_CODE(_SwitchBandwidth), /*54*/
/* MP_OFFLOAD End*/
GEN_CMD_CODE(_TX_Beacon), /*55*/
GEN_CMD_CODE(_SetPowerTracking),
GEN_CMD_CODE(_AMSDU_TO_AMPDU), /*57*/
GEN_CMD_CODE(_SetMacAddress), /*58*/
GEN_CMD_CODE(_DisconnectCtrl), /*59*/
GEN_CMD_CODE(_SetChannelPlan), /*60*/
GEN_CMD_CODE(_DisconnectCtrlEx), /*61*/
/* To do, modify these h2c cmd, add or delete */
GEN_CMD_CODE(_GetH2cLbk),
/* WPS extra IE */
GEN_CMD_CODE(_SetProbeReqExtraIE),
GEN_CMD_CODE(_SetAssocReqExtraIE),
GEN_CMD_CODE(_SetProbeRspExtraIE),
GEN_CMD_CODE(_SetAssocRspExtraIE),
/* the following is driver will do */
GEN_CMD_CODE(_GetCurDataRate),
GEN_CMD_CODE(_GetTxRetrycnt), /* to record times that Tx retry to
* transmit packet after association
*/
GEN_CMD_CODE(_GetRxRetrycnt), /* to record total number of the
* received frame with ReTry bit set in
* the WLAN header
*/
GEN_CMD_CODE(_GetBCNOKcnt),
GEN_CMD_CODE(_GetBCNERRcnt),
GEN_CMD_CODE(_GetCurTxPwrLevel),
GEN_CMD_CODE(_SetDIG),
GEN_CMD_CODE(_SetRA),
GEN_CMD_CODE(_SetPT),
GEN_CMD_CODE(_ReadTSSI),
MAX_H2CCMD
};
#define _GetBBReg_CMD_ _Read_BBREG_CMD_
#define _SetBBReg_CMD_ _Write_BBREG_CMD_
#define _GetRFReg_CMD_ _Read_RFREG_CMD_
#define _SetRFReg_CMD_ _Write_RFREG_CMD_
#define _DRV_INT_CMD_ (MAX_H2CCMD + 1)
#define _SetRFIntFs_CMD_ (MAX_H2CCMD + 2)
#ifdef _RTL8712_CMD_C_
static struct _cmd_callback cmd_callback[] = {
{GEN_CMD_CODE(_Read_MACREG), NULL}, /*0*/
{GEN_CMD_CODE(_Write_MACREG), NULL},
{GEN_CMD_CODE(_Read_BBREG), NULL},
{GEN_CMD_CODE(_Write_BBREG), NULL},
{GEN_CMD_CODE(_Read_RFREG), &r8712_getbbrfreg_cmdrsp_callback},
{GEN_CMD_CODE(_Write_RFREG), NULL}, /*5*/
{GEN_CMD_CODE(_Read_EEPROM), NULL},
{GEN_CMD_CODE(_Write_EEPROM), NULL},
{GEN_CMD_CODE(_Read_EFUSE), NULL},
{GEN_CMD_CODE(_Write_EFUSE), NULL},
{GEN_CMD_CODE(_Read_CAM), NULL}, /*10*/
{GEN_CMD_CODE(_Write_CAM), NULL},
{GEN_CMD_CODE(_setBCNITV), NULL},
{GEN_CMD_CODE(_setMBIDCFG), NULL},
{GEN_CMD_CODE(_JoinBss), &r8712_joinbss_cmd_callback}, /*14*/
{GEN_CMD_CODE(_DisConnect), &r8712_disassoc_cmd_callback}, /*15*/
{GEN_CMD_CODE(_CreateBss), &r8712_createbss_cmd_callback},
{GEN_CMD_CODE(_SetOpMode), NULL},
{GEN_CMD_CODE(_SiteSurvey), &r8712_survey_cmd_callback}, /*18*/
{GEN_CMD_CODE(_SetAuth), NULL},
{GEN_CMD_CODE(_SetKey), NULL}, /*20*/
{GEN_CMD_CODE(_SetStaKey), &r8712_setstaKey_cmdrsp_callback},
{GEN_CMD_CODE(_SetAssocSta), &r8712_setassocsta_cmdrsp_callback},
{GEN_CMD_CODE(_DelAssocSta), NULL},
{GEN_CMD_CODE(_SetStaPwrState), NULL},
{GEN_CMD_CODE(_SetBasicRate), NULL}, /*25*/
{GEN_CMD_CODE(_GetBasicRate), NULL},
{GEN_CMD_CODE(_SetDataRate), NULL},
{GEN_CMD_CODE(_GetDataRate), NULL},
{GEN_CMD_CODE(_SetPhyInfo), NULL},
{GEN_CMD_CODE(_GetPhyInfo), NULL}, /*30*/
{GEN_CMD_CODE(_SetPhy), NULL},
{GEN_CMD_CODE(_GetPhy), NULL},
{GEN_CMD_CODE(_readRssi), NULL},
{GEN_CMD_CODE(_readGain), NULL},
{GEN_CMD_CODE(_SetAtim), NULL}, /*35*/
{GEN_CMD_CODE(_SetPwrMode), NULL},
{GEN_CMD_CODE(_JoinbssRpt), NULL},
{GEN_CMD_CODE(_SetRaTable), NULL},
{GEN_CMD_CODE(_GetRaTable), NULL},
{GEN_CMD_CODE(_GetCCXReport), NULL}, /*40*/
{GEN_CMD_CODE(_GetDTMReport), NULL},
{GEN_CMD_CODE(_GetTXRateStatistics), NULL},
{GEN_CMD_CODE(_SetUsbSuspend), NULL},
{GEN_CMD_CODE(_SetH2cLbk), NULL},
{GEN_CMD_CODE(_AddBAReq), NULL}, /*45*/
{GEN_CMD_CODE(_SetChannel), NULL}, /*46*/
/* MP_OFFLOAD Start (47~54)*/
{GEN_CMD_CODE(_SetTxPower), NULL},
{GEN_CMD_CODE(_SwitchAntenna), NULL},
{GEN_CMD_CODE(_SetCrystalCap), NULL},
{GEN_CMD_CODE(_SetSingleCarrierTx), NULL}, /*50*/
{GEN_CMD_CODE(_SetSingleToneTx), NULL},
{GEN_CMD_CODE(_SetCarrierSuppressionTx), NULL},
{GEN_CMD_CODE(_SetContinuousTx), NULL},
{GEN_CMD_CODE(_SwitchBandwidth), NULL}, /*54*/
/* MP_OFFLOAD End*/
{GEN_CMD_CODE(_TX_Beacon), NULL}, /*55*/
{GEN_CMD_CODE(_SetPowerTracking), NULL},
{GEN_CMD_CODE(_AMSDU_TO_AMPDU), NULL}, /*57*/
{GEN_CMD_CODE(_SetMacAddress), NULL}, /*58*/
{GEN_CMD_CODE(_DisconnectCtrl), NULL}, /*59*/
{GEN_CMD_CODE(_SetChannelPlan), NULL}, /*60*/
{GEN_CMD_CODE(_DisconnectCtrlEx), NULL}, /*61*/
/* To do, modify these h2c cmd, add or delete */
{GEN_CMD_CODE(_GetH2cLbk), NULL},
{_SetProbeReqExtraIE_CMD_, NULL},
{_SetAssocReqExtraIE_CMD_, NULL},
{_SetProbeRspExtraIE_CMD_, NULL},
{_SetAssocRspExtraIE_CMD_, NULL},
{_GetCurDataRate_CMD_, NULL},
{_GetTxRetrycnt_CMD_, NULL},
{_GetRxRetrycnt_CMD_, NULL},
{_GetBCNOKcnt_CMD_, NULL},
{_GetBCNERRcnt_CMD_, NULL},
{_GetCurTxPwrLevel_CMD_, NULL},
{_SetDIG_CMD_, NULL},
{_SetRA_CMD_, NULL},
{_SetPT_CMD_, NULL},
{GEN_CMD_CODE(_ReadTSSI), &r8712_readtssi_cmdrsp_callback}
};
#endif
#endif

95
drivers/staging/rtl8712/rtl8712_cmdctrl_bitdef.h
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@ -1,95 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
*
******************************************************************************/
#ifndef __RTL8712_CMDCTRL_BITDEF_H__
#define __RTL8712_CMDCTRL_BITDEF_H__
/*
* 2. Command Control Registers (Offset: 0x0040 - 0x004F)
*/
/*--------------------------------------------------------------------------*/
/* 8192S (CMD) command register bits (Offset 0x40, 16 bits)*/
/*--------------------------------------------------------------------------*/
#define _APSDOFF_STATUS BIT(15)
#define _APSDOFF BIT(14)
#define _BBRSTn BIT(13) /*Enable OFDM/CCK*/
#define _BB_GLB_RSTn BIT(12) /*Enable BB*/
#define _SCHEDULE_EN BIT(10) /*Enable MAC scheduler*/
#define _MACRXEN BIT(9)
#define _MACTXEN BIT(8)
#define _DDMA_EN BIT(7) /*FW off load function enable*/
#define _FW2HW_EN BIT(6) /*MAC every module reset */
#define _RXDMA_EN BIT(5)
#define _TXDMA_EN BIT(4)
#define _HCI_RXDMA_EN BIT(3)
#define _HCI_TXDMA_EN BIT(2)
/*TXPAUSE*/
#define _STOPHCCA BIT(6)
#define _STOPHIGH BIT(5)
#define _STOPMGT BIT(4)
#define _STOPVO BIT(3)
#define _STOPVI BIT(2)
#define _STOPBE BIT(1)
#define _STOPBK BIT(0)
/*TCR*/
#define _DISCW BIT(20)
#define _ICV BIT(19)
#define _CFEND_FMT BIT(17)
#define _CRC BIT(16)
#define _FWRDY BIT(7)
#define _BASECHG BIT(6)
#define _IMEM_RDY BIT(5)
#define _DMEM_CODE_DONE BIT(4)
#define _EMEM_CHK_RPT BIT(3)
#define _EMEM_CODE_DONE BIT(2)
#define _IMEM_CHK_RPT BIT(1)
#define _IMEM_CODE_DONE BIT(0)
#define _TXDMA_INIT_VALUE (_IMEM_CHK_RPT | _EMEM_CHK_RPT)
/*RCR*/
#define _ENMBID BIT(27)
#define _APP_PHYST_RXFF BIT(25)
#define _APP_PHYST_STAFF BIT(24)
#define _CBSSID BIT(23)
#define _APWRMGT BIT(22)
#define _ADD3 BIT(21)
#define _AMF BIT(20)
#define _ACF BIT(19)
#define _ADF BIT(18)
#define _APP_MIC BIT(17)
#define _APP_ICV BIT(16)
#define _RXFTH_MSK 0x0000E000
#define _RXFTH_SHT 13
#define _AICV BIT(12)
#define _RXPKTLMT_MSK 0x00000FC0
#define _RXPKTLMT_SHT 6
#define _ACRC32 BIT(5)
#define _AB BIT(3)
#define _AM BIT(2)
#define _APM BIT(1)
#define _AAP BIT(0)
/*MSR*/
#define _NETTYPE_MSK 0x03
#define _NETTYPE_SHT 0
/*BT*/
#define _BTMODE_MSK 0x06
#define _BTMODE_SHT 1
#define _ENBT BIT(0)
/*MBIDCTRL*/
#define _ENMBID_MODE BIT(15)
#define _BCNNO_MSK 0x7000
#define _BCNNO_SHT 12
#define _BCNSPACE_MSK 0x0FFF
#define _BCNSPACE_SHT 0
#endif /* __RTL8712_CMDCTRL_BITDEF_H__*/

19
drivers/staging/rtl8712/rtl8712_cmdctrl_regdef.h
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@ -1,19 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
*
******************************************************************************/
#ifndef __RTL8712_CMDCTRL_REGDEF_H__
#define __RTL8712_CMDCTRL_REGDEF_H__
#define CR (RTL8712_CMDCTRL_ + 0x0000)
#define TXPAUSE (RTL8712_CMDCTRL_ + 0x0002)
#define TCR (RTL8712_CMDCTRL_ + 0x0004)
#define RCR (RTL8712_CMDCTRL_ + 0x0008)
#define MSR (RTL8712_CMDCTRL_ + 0x000C)
#define SYSF_CFG (RTL8712_CMDCTRL_ + 0x000D)
#define MBIDCTRL (RTL8712_CMDCTRL_ + 0x000E)
#endif /* __RTL8712_CMDCTRL_REGDEF_H__ */

41
drivers/staging/rtl8712/rtl8712_debugctrl_bitdef.h
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@ -1,41 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
*
******************************************************************************/
#ifndef __RTL8712_DEBUGCTRL_BITDEF_H__
#define __RTL8712_DEBUGCTRL_BITDEF_H__
/*BIST*/
#define _BIST_RST BIT(0)
/*LMS*/
#define _LMS_MSK 0x03
/*WDG_CTRL*/
#define _OVSEL_MSK 0x0600
#define _OVSEL_SHT 9
#define _WDGCLR BIT(8)
#define _WDGEN_MSK 0x00FF
#define _WDGEN_SHT 0
/*INTM*/
#define _TXTIMER_MSK 0xF000
#define _TXTIMER_SHT 12
#define _TXNUM_MSK 0x0F00
#define _TXNUM_SHT 8
#define _RXTIMER_MSK 0x00F0
#define _RXTIMER_SHT 4
#define _RXNUM_MSK 0x000F
#define _RXNUM_SHT 0
/*FDLOCKTURN0*/
/*FDLOCKTURN1*/
#define _TURN1 BIT(0)
/*FDLOCKFLAG0*/
/*FDLOCKFLAG1*/
#define _LOCKFLAG1_MSK 0x03
#endif /* __RTL8712_DEBUGCTRL_BITDEF_H__ */

32
drivers/staging/rtl8712/rtl8712_debugctrl_regdef.h
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@ -1,32 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
*
******************************************************************************/
#ifndef __RTL8712_DEBUGCTRL_REGDEF_H__
#define __RTL8712_DEBUGCTRL_REGDEF_H__
#define BIST (RTL8712_DEBUGCTRL_ + 0x00)
#define DBS (RTL8712_DEBUGCTRL_ + 0x04)
#define LMS (RTL8712_DEBUGCTRL_ + 0x05)
#define CPUINST (RTL8712_DEBUGCTRL_ + 0x08)
#define CPUCAUSE (RTL8712_DEBUGCTRL_ + 0x0C)
#define LBUS_ERR_ADDR (RTL8712_DEBUGCTRL_ + 0x10)
#define LBUS_ERR_CMD (RTL8712_DEBUGCTRL_ + 0x14)
#define LBUS_ERR_DATA_L (RTL8712_DEBUGCTRL_ + 0x18)
#define LBUS_ERR_DATA_H (RTL8712_DEBUGCTRL_ + 0x1C)
#define LBUS_EXCEPTION_ADDR (RTL8712_DEBUGCTRL_ + 0x20)
#define WDG_CTRL (RTL8712_DEBUGCTRL_ + 0x24)
#define INTMTU (RTL8712_DEBUGCTRL_ + 0x28)
#define INTM (RTL8712_DEBUGCTRL_ + 0x2A)
#define FDLOCKTURN0 (RTL8712_DEBUGCTRL_ + 0x2C)
#define FDLOCKTURN1 (RTL8712_DEBUGCTRL_ + 0x2D)
#define FDLOCKFLAG0 (RTL8712_DEBUGCTRL_ + 0x2E)
#define FDLOCKFLAG1 (RTL8712_DEBUGCTRL_ + 0x2F)
#define TRXPKTBUF_DBG_DATA (RTL8712_DEBUGCTRL_ + 0x30)
#define TRXPKTBUF_DBG_CTRL (RTL8712_DEBUGCTRL_ + 0x38)
#define DPLL_MON (RTL8712_DEBUGCTRL_ + 0x3A)
#endif /* __RTL8712_DEBUGCTRL_REGDEF_H__ */

65
drivers/staging/rtl8712/rtl8712_edcasetting_bitdef.h
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/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
*
* Modifications for inclusion into the Linux staging tree are
* Copyright(c) 2010 Larry Finger. All rights reserved.
*
* Contact information:
* WLAN FAE <wlanfae@realtek.com>
* Larry Finger <Larry.Finger@lwfinger.net>
*
******************************************************************************/
#ifndef __RTL8712_EDCASETTING_BITDEF_H__
#define __RTL8712_EDCASETTING_BITDEF_H__
/*EDCAPARAM*/
#define _TXOPLIMIT_MSK 0xFFFF0000
#define _TXOPLIMIT_SHT 16
#define _ECWIN_MSK 0x0000FF00
#define _ECWIN_SHT 8
#define _AIFS_MSK 0x000000FF
#define _AIFS_SHT 0
/*BCNTCFG*/
#define _BCNECW_MSK 0xFF00
#define _BCNECW_SHT 8
#define _BCNIFS_MSK 0x00FF
#define _BCNIFS_SHT 0
/*CWRR*/
#define _CWRR_MSK 0x03FF
/*ACMAVG*/
#define _AVG_TIME_UP BIT(3)
#define _AVGPERIOD_MSK 0x03
/*ACMHWCTRL*/
#define _VOQ_ACM_STATUS BIT(6)
#define _VIQ_ACM_STATUS BIT(5)
#define _BEQ_ACM_STATUS BIT(4)
#define _VOQ_ACM_EN BIT(3)
#define _VIQ_ACM_EN BIT(2)
#define _BEQ_ACM_EN BIT(1)
#define _ACMHWEN BIT(0)
/*VO_ADMTIME*/
#define _VO_ACM_RUT BIT(18)
#define _VO_ADMTIME_MSK 0x0003FFF
/*VI_ADMTIME*/
#define _VI_ACM_RUT BIT(18)
#define _VI_ADMTIME_MSK 0x0003FFF
/*BE_ADMTIME*/
#define _BE_ACM_RUT BIT(18)
#define _BE_ADMTIME_MSK 0x0003FFF
/*Retry limit reg*/
#define _SRL_MSK 0xFF00
#define _SRL_SHT 8
#define _LRL_MSK 0x00FF
#define _LRL_SHT 0
#endif /* __RTL8712_EDCASETTING_BITDEF_H__*/

24
drivers/staging/rtl8712/rtl8712_edcasetting_regdef.h
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@ -1,24 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
*
******************************************************************************/
#ifndef __RTL8712_EDCASETTING_REGDEF_H__
#define __RTL8712_EDCASETTING_REGDEF_H__
#define EDCA_VO_PARAM (RTL8712_EDCASETTING_ + 0x00)
#define EDCA_VI_PARAM (RTL8712_EDCASETTING_ + 0x04)
#define EDCA_BE_PARAM (RTL8712_EDCASETTING_ + 0x08)
#define EDCA_BK_PARAM (RTL8712_EDCASETTING_ + 0x0C)
#define BCNTCFG (RTL8712_EDCASETTING_ + 0x10)
#define CWRR (RTL8712_EDCASETTING_ + 0x12)
#define ACMAVG (RTL8712_EDCASETTING_ + 0x16)
#define ACMHWCTRL (RTL8712_EDCASETTING_ + 0x17)
#define VO_ADMTIME (RTL8712_EDCASETTING_ + 0x18)
#define VI_ADMTIME (RTL8712_EDCASETTING_ + 0x1C)
#define BE_ADMTIME (RTL8712_EDCASETTING_ + 0x20)
#define RL (RTL8712_EDCASETTING_ + 0x24)
#endif /* __RTL8712_EDCASETTING_REGDEF_H__ */

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drivers/staging/rtl8712/rtl8712_efuse.c
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// SPDX-License-Identifier: GPL-2.0
/*
* rtl8712_efuse.c
*
* Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
* Linux device driver for RTL8192SU
*
* Modifications for inclusion into the Linux staging tree are
* Copyright(c) 2010 Larry Finger. All rights reserved.
*
* Contact information:
* WLAN FAE <wlanfae@realtek.com>.
* Larry Finger <Larry.Finger@lwfinger.net>
*
******************************************************************************/
#define _RTL8712_EFUSE_C_
#include "osdep_service.h"
#include "drv_types.h"
#include "rtl8712_efuse.h"
/* reserve 3 bytes for HW stop read */
static int efuse_available_max_size = EFUSE_MAX_SIZE - 3 /*0x1FD*/;
static void efuse_reg_ctrl(struct _adapter *adapter, u8 bPowerOn)
{
u8 tmpu8 = 0;
if (bPowerOn) {
/* -----------------e-fuse pwr & clk reg ctrl ---------------
* Enable LDOE25 Macro Block
*/
tmpu8 = r8712_read8(adapter, EFUSE_TEST + 3);
tmpu8 |= 0x80;
r8712_write8(adapter, EFUSE_TEST + 3, tmpu8);
msleep(20); /* for some platform , need some delay time */
/* Change Efuse Clock for write action to 40MHZ */
r8712_write8(adapter, EFUSE_CLK_CTRL, 0x03);
msleep(20); /* for some platform , need some delay time */
} else {
/* -----------------e-fuse pwr & clk reg ctrl -----------------
* Disable LDOE25 Macro Block
*/
tmpu8 = r8712_read8(adapter, EFUSE_TEST + 3);
tmpu8 &= 0x7F;
r8712_write8(adapter, EFUSE_TEST + 3, tmpu8);
/* Change Efuse Clock for write action to 500K */
r8712_write8(adapter, EFUSE_CLK_CTRL, 0x02);
}
}
/*
* Before write E-Fuse, this function must be called.
*/
u8 r8712_efuse_reg_init(struct _adapter *adapter)
{
return true;
}
void r8712_efuse_reg_uninit(struct _adapter *adapter)
{
efuse_reg_ctrl(adapter, false);
}
static u8 efuse_one_byte_read(struct _adapter *adapter, u16 addr, u8 *data)
{
u8 tmpidx = 0, bResult;
/* -----------------e-fuse reg ctrl --------------------------------- */
r8712_write8(adapter, EFUSE_CTRL + 1, (u8)(addr & 0xFF)); /* address */
r8712_write8(adapter, EFUSE_CTRL + 2, ((u8)((addr >> 8) & 0x03)) |
(r8712_read8(adapter, EFUSE_CTRL + 2) & 0xFC));
r8712_write8(adapter, EFUSE_CTRL + 3, 0x72); /* read cmd */
/* wait for complete */
while (!(0x80 & r8712_read8(adapter, EFUSE_CTRL + 3)) &&
(tmpidx < 100))
tmpidx++;
if (tmpidx < 100) {
*data = r8712_read8(adapter, EFUSE_CTRL);
bResult = true;
} else {
*data = 0xff;
bResult = false;
}
return bResult;
}
static u8 efuse_one_byte_write(struct _adapter *adapter, u16 addr, u8 data)
{
u8 tmpidx = 0, bResult;
/* -----------------e-fuse reg ctrl -------------------------------- */
r8712_write8(adapter, EFUSE_CTRL + 1, (u8)(addr & 0xFF)); /* address */
r8712_write8(adapter, EFUSE_CTRL + 2, ((u8)((addr >> 8) & 0x03)) |
(r8712_read8(adapter, EFUSE_CTRL + 2) & 0xFC));
r8712_write8(adapter, EFUSE_CTRL, data); /* data */
r8712_write8(adapter, EFUSE_CTRL + 3, 0xF2); /* write cmd */
/* wait for complete */
while ((0x80 & r8712_read8(adapter, EFUSE_CTRL + 3)) &&
(tmpidx < 100))
tmpidx++;
if (tmpidx < 100)
bResult = true;
else
bResult = false;
return bResult;
}
static u8 efuse_one_byte_rw(struct _adapter *adapter, u8 bRead, u16 addr,
u8 *data)
{
u8 tmpidx = 0, tmpv8 = 0, bResult;
/* -----------------e-fuse reg ctrl --------------------------------- */
r8712_write8(adapter, EFUSE_CTRL + 1, (u8)(addr & 0xFF)); /* address */
tmpv8 = ((u8)((addr >> 8) & 0x03)) |
(r8712_read8(adapter, EFUSE_CTRL + 2) & 0xFC);
r8712_write8(adapter, EFUSE_CTRL + 2, tmpv8);
if (bRead) {
r8712_write8(adapter, EFUSE_CTRL + 3, 0x72); /* read cmd */
while (!(0x80 & r8712_read8(adapter, EFUSE_CTRL + 3)) &&
(tmpidx < 100))
tmpidx++;
if (tmpidx < 100) {
*data = r8712_read8(adapter, EFUSE_CTRL);
bResult = true;
} else {
*data = 0;
bResult = false;
}
} else {
r8712_write8(adapter, EFUSE_CTRL, *data); /* data */
r8712_write8(adapter, EFUSE_CTRL + 3, 0xF2); /* write cmd */
while ((0x80 & r8712_read8(adapter, EFUSE_CTRL + 3)) &&
(tmpidx < 100))
tmpidx++;
if (tmpidx < 100)
bResult = true;
else
bResult = false;
}
return bResult;
}
static u8 efuse_is_empty(struct _adapter *adapter, u8 *empty)
{
u8 value, ret = true;
/* read one byte to check if E-Fuse is empty */
if (efuse_one_byte_rw(adapter, true, 0, &value)) {
if (value == 0xFF)
*empty = true;
else
*empty = false;
} else {
ret = false;
}
return ret;
}
void r8712_efuse_change_max_size(struct _adapter *adapter)
{
u16 pre_pg_data_saddr = 0x1FB;
u16 i;
u16 pre_pg_data_size = 5;
u8 pre_pg_data[5];
for (i = 0; i < pre_pg_data_size; i++)
efuse_one_byte_read(adapter, pre_pg_data_saddr + i,
&pre_pg_data[i]);
if ((pre_pg_data[0] == 0x03) && (pre_pg_data[1] == 0x00) &&
(pre_pg_data[2] == 0x00) && (pre_pg_data[3] == 0x00) &&
(pre_pg_data[4] == 0x0C))
efuse_available_max_size -= pre_pg_data_size;
}
int r8712_efuse_get_max_size(struct _adapter *adapter)
{
return efuse_available_max_size;
}
static u8 calculate_word_cnts(const u8 word_en)
{
u8 word_cnts = 0;
u8 word_idx;
for (word_idx = 0; word_idx < PGPKG_MAX_WORDS; word_idx++)
if (!(word_en & BIT(word_idx)))
word_cnts++; /* 0 : write enable */
return word_cnts;
}
static void pgpacket_copy_data(const u8 word_en, const u8 *sourdata,
u8 *targetdata)
{
u8 tmpindex = 0;
u8 word_idx, byte_idx;
for (word_idx = 0; word_idx < PGPKG_MAX_WORDS; word_idx++) {
if (!(word_en & BIT(word_idx))) {
byte_idx = word_idx * 2;
targetdata[byte_idx] = sourdata[tmpindex++];
targetdata[byte_idx + 1] = sourdata[tmpindex++];
}
}
}
u16 r8712_efuse_get_current_size(struct _adapter *adapter)
{
int bContinual = true;
u16 efuse_addr = 0;
u8 hworden = 0;
u8 efuse_data, word_cnts = 0;
while (bContinual && efuse_one_byte_read(adapter, efuse_addr,
&efuse_data) && (efuse_addr < efuse_available_max_size)) {
if (efuse_data != 0xFF) {
hworden = efuse_data & 0x0F;
word_cnts = calculate_word_cnts(hworden);
/* read next header */
efuse_addr = efuse_addr + (word_cnts * 2) + 1;
} else {
bContinual = false;
}
}
return efuse_addr;
}
u8 r8712_efuse_pg_packet_read(struct _adapter *adapter, u8 offset, u8 *data)
{
u8 hoffset = 0, hworden = 0, word_cnts = 0;
u16 efuse_addr = 0;
u8 efuse_data;
u8 tmpidx = 0;
u8 tmpdata[PGPKT_DATA_SIZE];
u8 ret = true;
if (!data)
return false;
if (offset > 0x0f)
return false;
memset(data, 0xFF, sizeof(u8) * PGPKT_DATA_SIZE);
while (efuse_addr < efuse_available_max_size) {
if (efuse_one_byte_read(adapter, efuse_addr, &efuse_data)) {
if (efuse_data == 0xFF)
break;
hoffset = (efuse_data >> 4) & 0x0F;
hworden = efuse_data & 0x0F;
word_cnts = calculate_word_cnts(hworden);
if (hoffset == offset) {
memset(tmpdata, 0xFF, PGPKT_DATA_SIZE);
for (tmpidx = 0; tmpidx < word_cnts * 2;
tmpidx++) {
if (efuse_one_byte_read(adapter,
efuse_addr + 1 + tmpidx,
&efuse_data)) {
tmpdata[tmpidx] = efuse_data;
} else {
ret = false;
}
}
pgpacket_copy_data(hworden, tmpdata, data);
}
efuse_addr += 1 + (word_cnts * 2);
} else {
ret = false;
break;
}
}
return ret;
}
static u8 fix_header(struct _adapter *adapter, u8 header, u16 header_addr)
{
struct PGPKT_STRUCT pkt;
u8 offset, word_en, value;
u16 addr;
int i;
u8 ret = true;
pkt.offset = GET_EFUSE_OFFSET(header);
pkt.word_en = GET_EFUSE_WORD_EN(header);
addr = header_addr + 1 + calculate_word_cnts(pkt.word_en) * 2;
if (addr > efuse_available_max_size)
return false;
/* retrieve original data */
addr = 0;
while (addr < header_addr) {
if (!efuse_one_byte_read(adapter, addr++, &value)) {
ret = false;
break;
}
offset = GET_EFUSE_OFFSET(value);
word_en = GET_EFUSE_WORD_EN(value);
if (pkt.offset != offset) {
addr += calculate_word_cnts(word_en) * 2;
continue;
}
for (i = 0; i < PGPKG_MAX_WORDS; i++) {
if (!(BIT(i) & word_en))
continue;
if (BIT(i) & pkt.word_en) {
if (efuse_one_byte_read(adapter,
addr,
&value))
pkt.data[i * 2] = value;
else
return false;
if (efuse_one_byte_read(adapter,
addr + 1,
&value))
pkt.data[i * 2 + 1] = value;
else
return false;
}
addr += 2;
}
}
if (addr != header_addr)
return false;
addr++;
/* fill original data */
for (i = 0; i < PGPKG_MAX_WORDS; i++) {
if (BIT(i) & pkt.word_en) {
efuse_one_byte_write(adapter, addr, pkt.data[i * 2]);
efuse_one_byte_write(adapter, addr + 1,
pkt.data[i * 2 + 1]);
/* additional check */
if (!efuse_one_byte_read(adapter, addr, &value)) {
ret = false;
} else if (pkt.data[i * 2] != value) {
ret = false;
if (value == 0xFF) /* write again */
efuse_one_byte_write(adapter, addr,
pkt.data[i * 2]);
}
if (!efuse_one_byte_read(adapter, addr + 1, &value)) {
ret = false;
} else if (pkt.data[i * 2 + 1] != value) {
ret = false;
if (value == 0xFF) /* write again */
efuse_one_byte_write(adapter, addr + 1,
pkt.data[i * 2 +
1]);
}
}
addr += 2;
}
return ret;
}
u8 r8712_efuse_pg_packet_write(struct _adapter *adapter, const u8 offset,
const u8 word_en, const u8 *data)
{
u8 pg_header = 0;
u16 efuse_addr = 0, curr_size = 0;
u8 efuse_data, target_word_cnts = 0;
int repeat_times;
int sub_repeat;
u8 bResult = true;
/* check if E-Fuse Clock Enable and E-Fuse Clock is 40M */
efuse_data = r8712_read8(adapter, EFUSE_CLK_CTRL);
if (efuse_data != 0x03)
return false;
pg_header = MAKE_EFUSE_HEADER(offset, word_en);
target_word_cnts = calculate_word_cnts(word_en);
repeat_times = 0;
efuse_addr = 0;
while (efuse_addr < efuse_available_max_size) {
curr_size = r8712_efuse_get_current_size(adapter);
if ((curr_size + 1 + target_word_cnts * 2) >
efuse_available_max_size)
return false; /*target_word_cnts + pg header(1 byte)*/
efuse_addr = curr_size; /* current size is also the last addr*/
efuse_one_byte_write(adapter, efuse_addr, pg_header); /*hdr*/
sub_repeat = 0;
/* check if what we read is what we write */
while (!efuse_one_byte_read(adapter, efuse_addr,
&efuse_data)) {
if (++sub_repeat > _REPEAT_THRESHOLD_) {
bResult = false; /* continue to blind write */
break; /* continue to blind write */
}
}
if ((sub_repeat > _REPEAT_THRESHOLD_) ||
(pg_header == efuse_data)) {
/* write header ok OR can't check header(creep) */
u8 i;
/* go to next address */
efuse_addr++;
for (i = 0; i < target_word_cnts * 2; i++) {
efuse_one_byte_write(adapter,
efuse_addr + i,
*(data + i));
if (!efuse_one_byte_read(adapter,
efuse_addr + i,
&efuse_data))
bResult = false;
else if (*(data + i) != efuse_data) /* fail */
bResult = false;
}
break;
}
/* write header fail */
bResult = false;
if (efuse_data == 0xFF)
return bResult; /* nothing damaged. */
/* call rescue procedure */
if (!fix_header(adapter, efuse_data, efuse_addr))
return false; /* rescue fail */
if (++repeat_times > _REPEAT_THRESHOLD_) /* fail */
break;
/* otherwise, take another risk... */
}
return bResult;
}
u8 r8712_efuse_access(struct _adapter *adapter, u8 bRead, u16 start_addr,
u16 cnts, u8 *data)
{
int i;
u8 res = true;
if (start_addr > EFUSE_MAX_SIZE)
return false;
if (!bRead && ((start_addr + cnts) >
efuse_available_max_size))
return false;
if (!bRead && !r8712_efuse_reg_init(adapter))
return false;
/* -----------------e-fuse one byte read / write ---------------------*/
for (i = 0; i < cnts; i++) {
if ((start_addr + i) > EFUSE_MAX_SIZE) {
res = false;
break;
}
res = efuse_one_byte_rw(adapter, bRead, start_addr + i,
data + i);
if (!bRead && !res)
break;
}
if (!bRead)
r8712_efuse_reg_uninit(adapter);
return res;
}
u8 r8712_efuse_map_read(struct _adapter *adapter, u16 addr, u16 cnts, u8 *data)
{
u8 offset, ret = true;
u8 pktdata[PGPKT_DATA_SIZE];
int i, idx;
if ((addr + cnts) > EFUSE_MAP_MAX_SIZE)
return false;
if (efuse_is_empty(adapter, &offset) && offset) {
for (i = 0; i < cnts; i++)
data[i] = 0xFF;
return ret;
}
offset = (addr >> 3) & 0xF;
ret = r8712_efuse_pg_packet_read(adapter, offset, pktdata);
i = addr & 0x7; /* pktdata index */
idx = 0; /* data index */
do {
for (; i < PGPKT_DATA_SIZE; i++) {
data[idx++] = pktdata[i];
if (idx == cnts)
return ret;
}
offset++;
if (!r8712_efuse_pg_packet_read(adapter, offset, pktdata))
ret = false;
i = 0;
} while (1);
return ret;
}
u8 r8712_efuse_map_write(struct _adapter *adapter, u16 addr, u16 cnts,
u8 *data)
{
u8 offset, word_en, empty;
u8 pktdata[PGPKT_DATA_SIZE], newdata[PGPKT_DATA_SIZE];
int i, j, idx;
if ((addr + cnts) > EFUSE_MAP_MAX_SIZE)
return false;
/* check if E-Fuse Clock Enable and E-Fuse Clock is 40M */
empty = r8712_read8(adapter, EFUSE_CLK_CTRL);
if (empty != 0x03)
return false;
if (efuse_is_empty(adapter, &empty)) {
if (empty)
memset(pktdata, 0xFF, PGPKT_DATA_SIZE);
} else {
return false;
}
offset = (addr >> 3) & 0xF;
if (!empty)
if (!r8712_efuse_pg_packet_read(adapter, offset, pktdata))
return false;
word_en = 0xF;
memset(newdata, 0xFF, PGPKT_DATA_SIZE);
i = addr & 0x7; /* pktdata index */
j = 0; /* newdata index */
idx = 0; /* data index */
if (i & 0x1) {
/* odd start */
if (data[idx] != pktdata[i]) {
word_en &= ~BIT(i >> 1);
newdata[j++] = pktdata[i - 1];
newdata[j++] = data[idx];
}
i++;
idx++;
}
do {
for (; i < PGPKT_DATA_SIZE; i += 2) {
if ((cnts - idx) == 1) {
if (data[idx] != pktdata[i]) {
word_en &= ~BIT(i >> 1);
newdata[j++] = data[idx];
newdata[j++] = pktdata[1 + 1];
}
idx++;
break;
}
if ((data[idx] != pktdata[i]) || (data[idx + 1] !=
pktdata[i + 1])) {
word_en &= ~BIT(i >> 1);
newdata[j++] = data[idx];
newdata[j++] = data[idx + 1];
}
idx += 2;
if (idx == cnts)
break;
}
if (word_en != 0xF)
if (!r8712_efuse_pg_packet_write(adapter, offset,
word_en, newdata))
return false;
if (idx == cnts)
break;
offset++;
if (!empty)
if (!r8712_efuse_pg_packet_read(adapter, offset,
pktdata))
return false;
i = 0;
j = 0;
word_en = 0xF;
memset(newdata, 0xFF, PGPKT_DATA_SIZE);
} while (1);
return true;
}

44
drivers/staging/rtl8712/rtl8712_efuse.h
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@ -1,44 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __RTL8712_EFUSE_H__
#define __RTL8712_EFUSE_H__
#include "osdep_service.h"
#define _REPEAT_THRESHOLD_ 3
#define EFUSE_MAX_SIZE 512
#define EFUSE_MAP_MAX_SIZE 128
#define PGPKG_MAX_WORDS 4
#define PGPKT_DATA_SIZE 8 /* PGPKG_MAX_WORDS*2; BYTES sizeof(u8)*8*/
#define MAX_PGPKT_SIZE 9 /* 1 + PGPKT_DATA_SIZE; header + 2 * 4 words (BYTES)*/
#define GET_EFUSE_OFFSET(header) ((header & 0xF0) >> 4)
#define GET_EFUSE_WORD_EN(header) (header & 0x0F)
#define MAKE_EFUSE_HEADER(offset, word_en) ((((offset) & 0x0F) << 4) | \
((word_en) & 0x0F))
/*--------------------------------------------------------------------------*/
struct PGPKT_STRUCT {
u8 offset;
u8 word_en;
u8 data[PGPKT_DATA_SIZE];
};
/*--------------------------------------------------------------------------*/
u8 r8712_efuse_reg_init(struct _adapter *padapter);
void r8712_efuse_reg_uninit(struct _adapter *padapter);
u16 r8712_efuse_get_current_size(struct _adapter *padapter);
int r8712_efuse_get_max_size(struct _adapter *padapter);
void r8712_efuse_change_max_size(struct _adapter *padapter);
u8 r8712_efuse_pg_packet_read(struct _adapter *padapter,
u8 offset, u8 *data);
u8 r8712_efuse_pg_packet_write(struct _adapter *padapter,
const u8 offset, const u8 word_en,
const u8 *data);
u8 r8712_efuse_access(struct _adapter *padapter, u8 bRead,
u16 start_addr, u16 cnts, u8 *data);
u8 r8712_efuse_map_read(struct _adapter *padapter, u16 addr,
u16 cnts, u8 *data);
u8 r8712_efuse_map_write(struct _adapter *padapter, u16 addr,
u16 cnts, u8 *data);
#endif

86
drivers/staging/rtl8712/rtl8712_event.h
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/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
*
* Modifications for inclusion into the Linux staging tree are
* Copyright(c) 2010 Larry Finger. All rights reserved.
*
* Contact information:
* WLAN FAE <wlanfae@realtek.com>
* Larry Finger <Larry.Finger@lwfinger.net>
*
******************************************************************************/
#ifndef _RTL8712_EVENT_H_
#define _RTL8712_EVENT_H_
void r8712_event_handle(struct _adapter *padapter, __le32 *peventbuf);
void r8712_got_addbareq_event_callback(struct _adapter *adapter, u8 *pbuf);
enum rtl8712_c2h_event {
GEN_EVT_CODE(_Read_MACREG) = 0, /*0*/
GEN_EVT_CODE(_Read_BBREG),
GEN_EVT_CODE(_Read_RFREG),
GEN_EVT_CODE(_Read_EEPROM),
GEN_EVT_CODE(_Read_EFUSE),
GEN_EVT_CODE(_Read_CAM), /*5*/
GEN_EVT_CODE(_Get_BasicRate),
GEN_EVT_CODE(_Get_DataRate),
GEN_EVT_CODE(_Survey), /*8*/
GEN_EVT_CODE(_SurveyDone), /*9*/
GEN_EVT_CODE(_JoinBss), /*10*/
GEN_EVT_CODE(_AddSTA),
GEN_EVT_CODE(_DelSTA),
GEN_EVT_CODE(_AtimDone),
GEN_EVT_CODE(_TX_Report),
GEN_EVT_CODE(_CCX_Report), /*15*/
GEN_EVT_CODE(_DTM_Report),
GEN_EVT_CODE(_TX_Rate_Statistics),
GEN_EVT_CODE(_C2HLBK),
GEN_EVT_CODE(_FWDBG),
GEN_EVT_CODE(_C2HFEEDBACK), /*20*/
GEN_EVT_CODE(_ADDBA),
GEN_EVT_CODE(_C2HBCN),
GEN_EVT_CODE(_ReportPwrState), /*filen: only for PCIE, USB*/
GEN_EVT_CODE(_WPS_PBC), /*24*/
GEN_EVT_CODE(_ADDBAReq_Report), /*25*/
MAX_C2HEVT
};
#ifdef _RTL8712_CMD_C_
static struct fwevent wlanevents[] = {
{0, NULL}, /*0*/
{0, NULL},
{0, NULL},
{0, NULL},
{0, NULL},
{0, NULL},
{0, NULL},
{0, NULL},
{0, &r8712_survey_event_callback}, /*8*/
{sizeof(struct surveydone_event),
&r8712_surveydone_event_callback}, /*9*/
{0, &r8712_joinbss_event_callback}, /*10*/
{sizeof(struct stassoc_event), &r8712_stassoc_event_callback},
{sizeof(struct stadel_event), &r8712_stadel_event_callback},
{0, &r8712_atimdone_event_callback},
{0, NULL},
{0, NULL}, /*15*/
{0, NULL},
{0, NULL},
{0, NULL},
{0, NULL}, /*fwdbg_event_callback},*/
{0, NULL}, /*20*/
{0, NULL},
{0, NULL},
{0, &r8712_cpwm_event_callback},
{0, &r8712_wpspbc_event_callback},
{0, &r8712_got_addbareq_event_callback},
};
#endif/*_RTL8712_CMD_C_*/
#endif

131
drivers/staging/rtl8712/rtl8712_fifoctrl_bitdef.h
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@ -1,131 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
*
******************************************************************************/
#ifndef __RTL8712_FIFOCTRL_BITDEF_H__
#define __RTL8712_FIFOCTRL_BITDEF_H__
/*PBP*/
#define _PSTX_MSK 0xF0
#define _PSTX_SHT 4
#define _PSRX_MSK 0x0F
#define _PSRX_SHT 0
/*TXFF_STATUS*/
#define _TXSTATUS_OVF BIT(15)
/*RXFF_STATUS*/
#define _STATUSFF1_OVF BIT(7)
#define _STATUSFF1_EMPTY BIT(6)
#define _STATUSFF0_OVF BIT(5)
#define _STATUSFF0_EMPTY BIT(4)
#define _RXFF1_OVF BIT(3)
#define _RXFF1_EMPTY BIT(2)
#define _RXFF0_OVF BIT(1)
#define _RXFF0_EMPTY BIT(0)
/*TXFF_EMPTY_TH*/
#define _BKQ_EMPTY_TH_MSK 0x0F0000
#define _BKQ_EMPTY_TH_SHT 16
#define _BEQ_EMPTY_TH_MSK 0x00F000
#define _BEQ_EMPTY_TH_SHT 12
#define _VIQ_EMPTY_TH_MSK 0x000F00
#define _VIQ_EMPTY_TH_SHT 8
#define _VOQ_EMPTY_TH_MSK 0x0000F0
#define _VOQ_EMPTY_TH_SHT 4
#define _BMCQ_EMPTY_TH_MSK 0x00000F
#define _BMCQ_EMPTY_TH_SHT 0
/*SDIO_RX_BLKSZ*/
#define _SDIO_RX_BLKSZ_MSK 0x07
/*RXDMA_CTRL*/
#define _C2HFF_POLL BIT(4)
#define _RXPKT_POLL BIT(0)
/*RXPKT_NUM*/
#define _RXCMD_NUM_MSK 0xFF00
#define _RXCMD_NUM_SHT 8
#define _RXFF0_NUM_MSK 0x00FF
#define _RXFF0_NUM_SHT 0
/*FIFOPAGE2*/
#define _PUB_AVAL_PG_MSK 0xFFFF0000
#define _PUB_AVAL_PG_SHT 16
#define _BCN_AVAL_PG_MSK 0x0000FFFF
#define _BCN_AVAL_PG_SHT 0
/*RX0PKTNUM*/
#define _RXFF0_DEC_POLL BIT(15)
#define _RXFF0_PKT_DEC_NUM_MSK 0x3F00
#define _RXFF0_PKT_DEC_NUM_SHT 8
#define _RXFF0_PKTNUM_RPT_MSK 0x00FF
#define _RXFF0_PKTNUM_RPT_SHT 0
/*RX1PKTNUM*/
#define _RXFF1_DEC_POLL BIT(15)
#define _RXFF1_PKT_DEC_NUM_MSK 0x3F00
#define _RXFF1_PKT_DEC_NUM_SHT 8
#define _RXFF1_PKTNUM_RPT_MSK 0x00FF
#define _RXFF1_PKTNUM_RPT_SHT 0
/*RXFLTMAP0*/
#define _MGTFLT13EN BIT(13)
#define _MGTFLT12EN BIT(12)
#define _MGTFLT11EN BIT(11)
#define _MGTFLT10EN BIT(10)
#define _MGTFLT9EN BIT(9)
#define _MGTFLT8EN BIT(8)
#define _MGTFLT5EN BIT(5)
#define _MGTFLT4EN BIT(4)
#define _MGTFLT3EN BIT(3)
#define _MGTFLT2EN BIT(2)
#define _MGTFLT1EN BIT(1)
#define _MGTFLT0EN BIT(0)
/*RXFLTMAP1*/
#define _CTRLFLT15EN BIT(15)
#define _CTRLFLT14EN BIT(14)
#define _CTRLFLT13EN BIT(13)
#define _CTRLFLT12EN BIT(12)
#define _CTRLFLT11EN BIT(11)
#define _CTRLFLT10EN BIT(10)
#define _CTRLFLT9EN BIT(9)
#define _CTRLFLT8EN BIT(8)
#define _CTRLFLT7EN BIT(7)
#define _CTRLFLT6EN BIT(6)
/*RXFLTMAP2*/
#define _DATAFLT15EN BIT(15)
#define _DATAFLT14EN BIT(14)
#define _DATAFLT13EN BIT(13)
#define _DATAFLT12EN BIT(12)
#define _DATAFLT11EN BIT(11)
#define _DATAFLT10EN BIT(10)
#define _DATAFLT9EN BIT(9)
#define _DATAFLT8EN BIT(8)
#define _DATAFLT7EN BIT(7)
#define _DATAFLT6EN BIT(6)
#define _DATAFLT5EN BIT(5)
#define _DATAFLT4EN BIT(4)
#define _DATAFLT3EN BIT(3)
#define _DATAFLT2EN BIT(2)
#define _DATAFLT1EN BIT(1)
#define _DATAFLT0EN BIT(0)
/*RXFLTMAP3*/
#define _MESHAFLT1EN BIT(1)
#define _MESHAFLT0EN BIT(0)
/*TXPKT_NUM_CTRL*/
#define _TXPKTNUM_DEC BIT(8)
#define _TXPKTNUM_MSK 0x00FF
#define _TXPKTNUM_SHT 0
/*TXFF_PG_NUM*/
#define _TXFF_PG_NUM_MSK 0x0FFF
#endif /* __RTL8712_FIFOCTRL_BITDEF_H__ */

61
drivers/staging/rtl8712/rtl8712_fifoctrl_regdef.h
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@ -1,61 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
*
******************************************************************************/
#ifndef __RTL8712_FIFOCTRL_REGDEF_H__
#define __RTL8712_FIFOCTRL_REGDEF_H__
#define RQPN (RTL8712_FIFOCTRL_ + 0x00)
#define RXFF_BNDY (RTL8712_FIFOCTRL_ + 0x0C)
#define RXRPT_BNDY (RTL8712_FIFOCTRL_ + 0x10)
#define TXPKTBUF_PGBNDY (RTL8712_FIFOCTRL_ + 0x14)
#define PBP (RTL8712_FIFOCTRL_ + 0x15)
#define RX_DRVINFO_SZ (RTL8712_FIFOCTRL_ + 0x16)
#define TXFF_STATUS (RTL8712_FIFOCTRL_ + 0x17)
#define RXFF_STATUS (RTL8712_FIFOCTRL_ + 0x18)
#define TXFF_EMPTY_TH (RTL8712_FIFOCTRL_ + 0x19)
#define SDIO_RX_BLKSZ (RTL8712_FIFOCTRL_ + 0x1C)
#define RXDMA_RXCTRL (RTL8712_FIFOCTRL_ + 0x1D)
#define RXPKT_NUM (RTL8712_FIFOCTRL_ + 0x1E)
#define RXPKT_NUM_C2H (RTL8712_FIFOCTRL_ + 0x1F)
#define C2HCMD_UDT_SIZE (RTL8712_FIFOCTRL_ + 0x20)
#define C2HCMD_UDT_ADDR (RTL8712_FIFOCTRL_ + 0x22)
#define FIFOPAGE2 (RTL8712_FIFOCTRL_ + 0x24)
#define FIFOPAGE1 (RTL8712_FIFOCTRL_ + 0x28)
#define FW_RSVD_PG_CTRL (RTL8712_FIFOCTRL_ + 0x30)
#define TXRPTFF_RDPTR (RTL8712_FIFOCTRL_ + 0x40)
#define TXRPTFF_WTPTR (RTL8712_FIFOCTRL_ + 0x44)
#define C2HFF_RDPTR (RTL8712_FIFOCTRL_ + 0x48)
#define C2HFF_WTPTR (RTL8712_FIFOCTRL_ + 0x4C)
#define RXFF0_RDPTR (RTL8712_FIFOCTRL_ + 0x50)
#define RXFF0_WTPTR (RTL8712_FIFOCTRL_ + 0x54)
#define RXFF1_RDPTR (RTL8712_FIFOCTRL_ + 0x58)
#define RXFF1_WTPTR (RTL8712_FIFOCTRL_ + 0x5C)
#define RXRPT0FF_RDPTR (RTL8712_FIFOCTRL_ + 0x60)
#define RXRPT0FF_WTPTR (RTL8712_FIFOCTRL_ + 0x64)
#define RXRPT1FF_RDPTR (RTL8712_FIFOCTRL_ + 0x68)
#define RXRPT1FF_WTPTR (RTL8712_FIFOCTRL_ + 0x6C)
#define RX0PKTNUM (RTL8712_FIFOCTRL_ + 0x72)
#define RX1PKTNUM (RTL8712_FIFOCTRL_ + 0x74)
#define RXFLTMAP0 (RTL8712_FIFOCTRL_ + 0x76)
#define RXFLTMAP1 (RTL8712_FIFOCTRL_ + 0x78)
#define RXFLTMAP2 (RTL8712_FIFOCTRL_ + 0x7A)
#define RXFLTMAP3 (RTL8712_FIFOCTRL_ + 0x7c)
#define TBDA (RTL8712_FIFOCTRL_ + 0x84)
#define THPDA (RTL8712_FIFOCTRL_ + 0x88)
#define TCDA (RTL8712_FIFOCTRL_ + 0x8C)
#define TMDA (RTL8712_FIFOCTRL_ + 0x90)
#define HDA (RTL8712_FIFOCTRL_ + 0x94)
#define TVODA (RTL8712_FIFOCTRL_ + 0x98)
#define TVIDA (RTL8712_FIFOCTRL_ + 0x9C)
#define TBEDA (RTL8712_FIFOCTRL_ + 0xA0)
#define TBKDA (RTL8712_FIFOCTRL_ + 0xA4)
#define RCDA (RTL8712_FIFOCTRL_ + 0xA8)
#define RDSA (RTL8712_FIFOCTRL_ + 0xAC)
#define TXPKT_NUM_CTRL (RTL8712_FIFOCTRL_ + 0xB0)
#define TXQ_PGADD (RTL8712_FIFOCTRL_ + 0xB3)
#define TXFF_PG_NUM (RTL8712_FIFOCTRL_ + 0xB4)
#endif /* __RTL8712_FIFOCTRL_REGDEF_H__ */

68
drivers/staging/rtl8712/rtl8712_gp_bitdef.h
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@ -1,68 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
*
* Modifications for inclusion into the Linux staging tree are
* Copyright(c) 2010 Larry Finger. All rights reserved.
*
* Contact information:
* WLAN FAE <wlanfae@realtek.com>
* Larry Finger <Larry.Finger@lwfinger.net>
*
******************************************************************************/
#ifndef __RTL8712_GP_BITDEF_H__
#define __RTL8712_GP_BITDEF_H__
/*GPIO_CTRL*/
#define _GPIO_MOD_MSK 0xFF000000
#define _GPIO_MOD_SHT 24
#define _GPIO_IO_SEL_MSK 0x00FF0000
#define _GPIO_IO_SEL_SHT 16
#define _GPIO_OUT_MSK 0x0000FF00
#define _GPIO_OUT_SHT 8
#define _GPIO_IN_MSK 0x000000FF
#define _GPIO_IN_SHT 0
/*SYS_PINMUX_CFG*/
#define _GPIOSEL_MSK 0x0003
#define _GPIOSEL_SHT 0
/*LED_CFG*/
#define _LED1SV BIT(7)
#define _LED1CM_MSK 0x0070
#define _LED1CM_SHT 4
#define _LED0SV BIT(3)
#define _LED0CM_MSK 0x0007
#define _LED0CM_SHT 0
/*PHY_REG*/
#define _HST_RDRDY_SHT 0
#define _HST_RDRDY_MSK 0xFF
#define _HST_RDRDY BIT(_HST_RDRDY_SHT)
#define _CPU_WTBUSY_SHT 1
#define _CPU_WTBUSY_MSK 0xFF
#define _CPU_WTBUSY BIT(_CPU_WTBUSY_SHT)
/* 11. General Purpose Registers (Offset: 0x02E0 - 0x02FF)*/
/* 8192S GPIO Config Setting (offset 0x2F1, 1 byte)*/
/*----------------------------------------------------------------------------*/
#define GPIOMUX_EN BIT(3) /* When this bit is set to "1",
* GPIO PINs will switch to MAC
* GPIO Function
*/
#define GPIOSEL_GPIO 0 /* UART or JTAG or pure GPIO*/
#define GPIOSEL_PHYDBG 1 /* PHYDBG*/
#define GPIOSEL_BT 2 /* BT_coex*/
#define GPIOSEL_WLANDBG 3 /* WLANDBG*/
#define GPIOSEL_GPIO_MASK (~(BIT(0) | BIT(1)))
/* HW Radio OFF switch (GPIO BIT) */
#define HAL_8192S_HW_GPIO_OFF_BIT BIT(3)
#define HAL_8192S_HW_GPIO_OFF_MASK 0xF7
#define HAL_8192S_HW_GPIO_WPS_BIT BIT(4)
#endif /*__RTL8712_GP_BITDEF_H__*/

29
drivers/staging/rtl8712/rtl8712_gp_regdef.h
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@ -1,29 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
*
* Modifications for inclusion into the Linux staging tree are
* Copyright(c) 2010 Larry Finger. All rights reserved.
*
* Contact information:
* WLAN FAE <wlanfae@realtek.com>
* Larry Finger <Larry.Finger@lwfinger.net>
*
******************************************************************************/
#ifndef __RTL8712_GP_REGDEF_H__
#define __RTL8712_GP_REGDEF_H__
#define PSTIMER (RTL8712_GP_ + 0x00)
#define TIMER1 (RTL8712_GP_ + 0x04)
#define TIMER2 (RTL8712_GP_ + 0x08)
#define GPIO_CTRL (RTL8712_GP_ + 0x0C)
#define GPIO_IO_SEL (RTL8712_GP_ + 0x0E)
#define GPIO_INTCTRL (RTL8712_GP_ + 0x10)
#define MAC_PINMUX_CTRL (RTL8712_GP_ + 0x11)
#define LEDCFG (RTL8712_GP_ + 0x12)
#define PHY_REG_RPT (RTL8712_GP_ + 0x13)
#define PHY_REG_DATA (RTL8712_GP_ + 0x14)
#endif /*__RTL8712_GP_REGDEF_H__ */

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drivers/staging/rtl8712/rtl8712_hal.h
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/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
*
* Modifications for inclusion into the Linux staging tree are
* Copyright(c) 2010 Larry Finger. All rights reserved.
*
* Contact information:
* WLAN FAE <wlanfae@realtek.com>
* Larry Finger <Larry.Finger@lwfinger.net>
*
******************************************************************************/
#ifndef __RTL8712_HAL_H__
#define __RTL8712_HAL_H__
enum _HW_VERSION {
RTL8712_FPGA,
RTL8712_1stCUT, /*A Cut (RTL8712_ASIC)*/
RTL8712_2ndCUT, /*B Cut*/
RTL8712_3rdCUT, /*C Cut*/
};
enum _LOOPBACK_TYPE {
RTL8712_AIR_TRX = 0,
RTL8712_MAC_LBK,
RTL8712_BB_LBK,
RTL8712_MAC_FW_LBK = 4,
RTL8712_BB_FW_LBK = 8,
};
enum RTL871X_HCI_TYPE {
RTL8712_SDIO,
RTL8712_USB,
};
enum RTL8712_RF_CONFIG {
RTL8712_RF_1T1R,
RTL8712_RF_1T2R,
RTL8712_RF_2T2R
};
enum _RTL8712_HCI_TYPE_ {
RTL8712_HCI_TYPE_PCIE = 0x01,
RTL8712_HCI_TYPE_AP_PCIE = 0x81,
RTL8712_HCI_TYPE_USB = 0x02,
RTL8712_HCI_TYPE_92USB = 0x02,
RTL8712_HCI_TYPE_AP_USB = 0x82,
RTL8712_HCI_TYPE_72USB = 0x12,
RTL8712_HCI_TYPE_SDIO = 0x04,
RTL8712_HCI_TYPE_72SDIO = 0x14
};
struct fw_priv { /*8-bytes alignment required*/
/*--- long word 0 ----*/
unsigned char signature_0; /*0x12: CE product, 0x92: IT product*/
unsigned char signature_1; /*0x87: CE product, 0x81: IT product*/
unsigned char hci_sel; /*0x81: PCI-AP, 01:PCIe, 02: 92S-U, 0x82: USB-AP,
* 0x12: 72S-U, 03:SDIO
*/
unsigned char chip_version; /*the same value as register value*/
unsigned char customer_ID_0; /*customer ID low byte*/
unsigned char customer_ID_1; /*customer ID high byte*/
unsigned char rf_config; /*0x11: 1T1R, 0x12: 1T2R, 0x92: 1T2R turbo,
* 0x22: 2T2R
*/
unsigned char usb_ep_num; /* 4: 4EP, 6: 6EP, 11: 11EP*/
/*--- long word 1 ----*/
unsigned char regulatory_class_0; /*regulatory class bit map 0*/
unsigned char regulatory_class_1; /*regulatory class bit map 1*/
unsigned char regulatory_class_2; /*regulatory class bit map 2*/
unsigned char regulatory_class_3; /*regulatory class bit map 3*/
unsigned char rfintfs; /* 0:SWSI, 1:HWSI, 2:HWPI*/
unsigned char def_nettype;
unsigned char turbo_mode;
unsigned char low_power_mode;/* 0: normal mode, 1: low power mode*/
/*--- long word 2 ----*/
unsigned char lbk_mode; /*0x00: normal, 0x03: MACLBK, 0x01: PHYLBK*/
unsigned char mp_mode; /* 1: for MP use, 0: for normal driver */
unsigned char vcs_type; /* 0:off 1:on 2:auto */
unsigned char vcs_mode; /* 1:RTS/CTS 2:CTS to self */
unsigned char rsvd022;
unsigned char rsvd023;
unsigned char rsvd024;
unsigned char rsvd025;
/*--- long word 3 ----*/
unsigned char qos_en; /*1: QoS enable*/
unsigned char bw_40MHz_en; /*1: 40MHz BW enable*/
unsigned char AMSDU2AMPDU_en; /*1: 4181 convert AMSDU to AMPDU,
* 0: disable
*/
unsigned char AMPDU_en; /*1: 11n AMPDU enable*/
unsigned char rate_control_offload; /*1: FW offloads,0: driver handles*/
unsigned char aggregation_offload; /*1: FW offloads,0: driver handles*/
unsigned char rsvd030;
unsigned char rsvd031;
/*--- long word 4 ----*/
unsigned char beacon_offload; /* 1. FW offloads, 0: driver handles*/
unsigned char MLME_offload; /* 2. FW offloads, 0: driver handles*/
unsigned char hwpc_offload; /* 3. FW offloads, 0: driver handles*/
unsigned char tcp_checksum_offload; /*4. FW offloads,0: driver handles*/
unsigned char tcp_offload; /* 5. FW offloads, 0: driver handles*/
unsigned char ps_control_offload; /* 6. FW offloads, 0: driver handles*/
unsigned char WWLAN_offload; /* 7. FW offloads, 0: driver handles*/
unsigned char rsvd040;
/*--- long word 5 ----*/
unsigned char tcp_tx_frame_len_L; /*tcp tx packet length low byte*/
unsigned char tcp_tx_frame_len_H; /*tcp tx packet length high byte*/
unsigned char tcp_rx_frame_len_L; /*tcp rx packet length low byte*/
unsigned char tcp_rx_frame_len_H; /*tcp rx packet length high byte*/
unsigned char rsvd050;
unsigned char rsvd051;
unsigned char rsvd052;
unsigned char rsvd053;
};
struct fw_hdr {/*8-byte alignment required*/
unsigned short signature;
unsigned short version; /* 0x8000 ~ 0x8FFF for FPGA version,
* 0x0000 ~ 0x7FFF for ASIC version,
*/
unsigned int dmem_size; /*define the size of boot loader*/
unsigned int img_IMEM_size; /*define the size of FW in IMEM*/
unsigned int img_SRAM_size; /*define the size of FW in SRAM*/
unsigned int fw_priv_sz; /*define the size of DMEM variable*/
unsigned short efuse_addr;
unsigned short h2ccnd_resp_addr;
unsigned int SVNRevision;
unsigned int release_time; /*Mon:Day:Hr:Min*/
struct fw_priv fwpriv;
};
struct hal_priv {
/*Endpoint handles*/
struct net_device *pipehdls_r8712[10];
u8 (*hal_bus_init)(struct _adapter *adapter);
};
uint rtl8712_hal_init(struct _adapter *padapter);
int rtl871x_load_fw(struct _adapter *padapter);
#endif

44
drivers/staging/rtl8712/rtl8712_interrupt_bitdef.h
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@ -1,44 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
*
******************************************************************************/
#ifndef __RTL8712_INTERRUPT_BITDEF_H__
#define __RTL8712_INTERRUPT_BITDEF_H__
/*HIMR*/
/*HISR*/
#define _CPUERR BIT(29)
#define _ATIMEND BIT(28)
#define _TXBCNOK BIT(27)
#define _TXBCNERR BIT(26)
#define _BCNDMAINT4 BIT(25)
#define _BCNDMAINT3 BIT(24)
#define _BCNDMAINT2 BIT(23)
#define _BCNDMAINT1 BIT(22)
#define _BCNDOK4 BIT(21)
#define _BCNDOK3 BIT(20)
#define _BCNDOK2 BIT(19)
#define _BCNDOK1 BIT(18)
#define _TIMEOUT2 BIT(17)
#define _TIMEOUT1 BIT(16)
#define _TXFOVW BIT(15)
#define _PSTIMEOUT BIT(14)
#define _BCNDMAINT0 BIT(13)
#define _FOVW BIT(12)
#define _RDU BIT(11)
#define _RXCMDOK BIT(10)
#define _BCNDOK0 BIT(9)
#define _HIGHDOK BIT(8)
#define _COMDOK BIT(7)
#define _MGTDOK BIT(6)
#define _HCCADOK BIT(5)
#define _BKDOK BIT(4)
#define _BEDOK BIT(3)
#define _VIDOK BIT(2)
#define _VODOK BIT(1)
#define _RXOK BIT(0)
#endif /*__RTL8712_INTERRUPT_BITDEF_H__*/

99
drivers/staging/rtl8712/rtl8712_io.c
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@ -1,99 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/******************************************************************************
* rtl8712_io.c
*
* Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
* Linux device driver for RTL8192SU
*
* Modifications for inclusion into the Linux staging tree are
* Copyright(c) 2010 Larry Finger. All rights reserved.
*
* Contact information:
* WLAN FAE <wlanfae@realtek.com>.
* Larry Finger <Larry.Finger@lwfinger.net>
*
******************************************************************************/
#define _RTL8712_IO_C_
#include "osdep_service.h"
#include "drv_types.h"
#include "rtl871x_io.h"
#include "osdep_intf.h"
#include "usb_ops.h"
u8 r8712_read8(struct _adapter *adapter, u32 addr)
{
struct intf_hdl *hdl = &adapter->pio_queue->intf;
return hdl->io_ops._read8(hdl, addr);
}
u16 r8712_read16(struct _adapter *adapter, u32 addr)
{
struct intf_hdl *hdl = &adapter->pio_queue->intf;
return hdl->io_ops._read16(hdl, addr);
}
u32 r8712_read32(struct _adapter *adapter, u32 addr)
{
struct intf_hdl *hdl = &adapter->pio_queue->intf;
return hdl->io_ops._read32(hdl, addr);
}
void r8712_write8(struct _adapter *adapter, u32 addr, u8 val)
{
struct intf_hdl *hdl = &adapter->pio_queue->intf;
hdl->io_ops._write8(hdl, addr, val);
}
void r8712_write16(struct _adapter *adapter, u32 addr, u16 val)
{
struct intf_hdl *hdl = &adapter->pio_queue->intf;
hdl->io_ops._write16(hdl, addr, val);
}
void r8712_write32(struct _adapter *adapter, u32 addr, u32 val)
{
struct intf_hdl *hdl = &adapter->pio_queue->intf;
hdl->io_ops._write32(hdl, addr, val);
}
void r8712_read_mem(struct _adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
{
struct intf_hdl *hdl = &adapter->pio_queue->intf;
if (adapter->driver_stopped || adapter->surprise_removed)
return;
hdl->io_ops._read_mem(hdl, addr, cnt, pmem);
}
void r8712_write_mem(struct _adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
{
struct intf_hdl *hdl = &adapter->pio_queue->intf;
hdl->io_ops._write_mem(hdl, addr, cnt, pmem);
}
void r8712_read_port(struct _adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
{
struct intf_hdl *hdl = &adapter->pio_queue->intf;
if (adapter->driver_stopped || adapter->surprise_removed)
return;
hdl->io_ops._read_port(hdl, addr, cnt, pmem);
}
void r8712_write_port(struct _adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
{
struct intf_hdl *hdl = &adapter->pio_queue->intf;
hdl->io_ops._write_port(hdl, addr, cnt, pmem);
}

1830
drivers/staging/rtl8712/rtl8712_led.c
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File diff suppressed because it is too large Load Diff

31
drivers/staging/rtl8712/rtl8712_macsetting_bitdef.h
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@ -1,31 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
*
******************************************************************************/
#ifndef __RTL8712_MACSETTING_BITDEF_H__
#define __RTL8712_MACSETTING_BITDEF_H__
/*MACID*/
/*BSSID*/
/*HWVID*/
#define _HWVID_MSK 0x0F
/*MAR*/
/*MBIDCANCONTENT*/
/*MBIDCANCFG*/
#define _POOLING BIT(31)
#define _WRITE_EN BIT(16)
#define _CAM_ADDR_MSK 0x001F
#define _CAM_ADDR_SHT 0
/*BUILDTIME*/
#define _BUILDTIME_MSK 0x3FFFFFFF
/*BUILDUSER*/
#endif /* __RTL8712_MACSETTING_BITDEF_H__*/

20
drivers/staging/rtl8712/rtl8712_macsetting_regdef.h
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@ -1,20 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
*
******************************************************************************/
#ifndef __RTL8712_MACSETTING_REGDEF_H__
#define __RTL8712_MACSETTING_REGDEF_H__
#define MACID (RTL8712_MACIDSETTING_ + 0x0000)
#define BSSIDR (RTL8712_MACIDSETTING_ + 0x0008)
#define HWVID (RTL8712_MACIDSETTING_ + 0x000E)
#define MAR (RTL8712_MACIDSETTING_ + 0x0010)
#define MBIDCANCONTENT (RTL8712_MACIDSETTING_ + 0x0018)
#define MBIDCANCFG (RTL8712_MACIDSETTING_ + 0x0020)
#define BUILDTIME (RTL8712_MACIDSETTING_ + 0x0024)
#define BUILDUSER (RTL8712_MACIDSETTING_ + 0x0028)
#endif /*__RTL8712_MACSETTING_REGDEF_H__*/

39
drivers/staging/rtl8712/rtl8712_powersave_bitdef.h
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@ -1,39 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
*
******************************************************************************/
#ifndef __RTL8712_POWERSAVE_BITDEF_H__
#define __RTL8712_POWERSAVE_BITDEF_H__
/*WOWCTRL*/
#define _UWF BIT(3)
#define _MAGIC BIT(2)
#define _WOW_EN BIT(1)
#define _PMEN BIT(0)
/*PSSTATUS*/
#define _PSSTATUS_SEL_MSK 0x0F
/*PSSWITCH*/
#define _PSSWITCH_ACT BIT(7)
#define _PSSWITCH_SEL_MSK 0x0F
#define _PSSWITCH_SEL_SHT 0
/*LPNAV_CTRL*/
#define _LPNAV_EN BIT(31)
#define _LPNAV_EARLY_MSK 0x7FFF0000
#define _LPNAV_EARLY_SHT 16
#define _LPNAV_TH_MSK 0x0000FFFF
#define _LPNAV_TH_SHT 0
/*RPWM*/
/*CPWM*/
#define _TOGGLING BIT(7)
#define _WWLAN BIT(3)
#define _RPS_ST BIT(2)
#define _WLAN_TRX BIT(1)
#define _SYS_CLK BIT(0)
#endif /* __RTL8712_POWERSAVE_BITDEF_H__*/

26
drivers/staging/rtl8712/rtl8712_powersave_regdef.h
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@ -1,26 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
*
******************************************************************************/
#ifndef __RTL8712_POWERSAVE_REGDEF_H__
#define __RTL8712_POWERSAVE_REGDEF_H__
#define WOWCTRL (RTL8712_POWERSAVE_ + 0x00)
#define PSSTATUS (RTL8712_POWERSAVE_ + 0x01)
#define PSSWITCH (RTL8712_POWERSAVE_ + 0x02)
#define MIMOPS_WAITPERIOD (RTL8712_POWERSAVE_ + 0x03)
#define LPNAV_CTRL (RTL8712_POWERSAVE_ + 0x04)
#define WFM0 (RTL8712_POWERSAVE_ + 0x10)
#define WFM1 (RTL8712_POWERSAVE_ + 0x20)
#define WFM2 (RTL8712_POWERSAVE_ + 0x30)
#define WFM3 (RTL8712_POWERSAVE_ + 0x40)
#define WFM4 (RTL8712_POWERSAVE_ + 0x50)
#define WFM5 (RTL8712_POWERSAVE_ + 0x60)
#define WFCRC (RTL8712_POWERSAVE_ + 0x70)
#define RPWM (RTL8712_POWERSAVE_ + 0x7C)
#define CPWM (RTL8712_POWERSAVE_ + 0x7D)
#endif /* __RTL8712_POWERSAVE_REGDEF_H__ */

36
drivers/staging/rtl8712/rtl8712_ratectrl_bitdef.h
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@ -1,36 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
*
******************************************************************************/
#ifndef __RTL8712_RATECTRL_BITDEF_H__
#define __RTL8712_RATECTRL_BITDEF_H__
/*INIRTSMCS_SEL*/
#define _INIRTSMCS_SEL_MSK 0x3F
/* RRSR*/
#define _RRSR_SHORT BIT(23)
#define _RRSR_RSC_MSK 0x600000
#define _RRSR_RSC_SHT 21
#define _RRSR_BITMAP_MSK 0x0FFFFF
#define _RRSR_BITMAP_SHT 0
/* AGGLEN_LMT_H*/
#define _AGGLMT_MCS32_MSK 0xF0
#define _AGGLMT_MCS32_SHT 4
#define _AGGLMT_MCS15_SGI_MSK 0x0F
#define _AGGLMT_MCS15_SGI_SHT 0
/* DARFRC*/
/* RARFRC*/
/* MCS_TXAGC*/
/* CCK_TXAGC*/
#define _CCK_MSK 0xFF00
#define _CCK_SHT 8
#define _BARKER_MSK 0x00FF
#define _BARKER_SHT 0
#endif /* __RTL8712_RATECTRL_BITDEF_H__*/

43
drivers/staging/rtl8712/rtl8712_ratectrl_regdef.h
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@ -1,43 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
*
* Modifications for inclusion into the Linux staging tree are
* Copyright(c) 2010 Larry Finger. All rights reserved.
*
* Contact information:
* WLAN FAE <wlanfae@realtek.com>
* Larry Finger <Larry.Finger@lwfinger.net>
*
******************************************************************************/
#ifndef __RTL8712_RATECTRL_REGDEF_H__
#define __RTL8712_RATECTRL_REGDEF_H__
#define INIMCS_SEL (RTL8712_RATECTRL_ + 0x00)
#define INIRTSMCS_SEL (RTL8712_RATECTRL_ + 0x20)
#define RRSR (RTL8712_RATECTRL_ + 0x21)
#define ARFR0 (RTL8712_RATECTRL_ + 0x24)
#define ARFR1 (RTL8712_RATECTRL_ + 0x28)
#define ARFR2 (RTL8712_RATECTRL_ + 0x2C)
#define ARFR3 (RTL8712_RATECTRL_ + 0x30)
#define ARFR4 (RTL8712_RATECTRL_ + 0x34)
#define ARFR5 (RTL8712_RATECTRL_ + 0x38)
#define ARFR6 (RTL8712_RATECTRL_ + 0x3C)
#define ARFR7 (RTL8712_RATECTRL_ + 0x40)
#define AGGLEN_LMT_H (RTL8712_RATECTRL_ + 0x47)
#define AGGLEN_LMT_L (RTL8712_RATECTRL_ + 0x48)
#define DARFRC (RTL8712_RATECTRL_ + 0x50)
#define RARFRC (RTL8712_RATECTRL_ + 0x58)
#define MCS_TXAGC0 (RTL8712_RATECTRL_ + 0x60)
#define MCS_TXAGC1 (RTL8712_RATECTRL_ + 0x61)
#define MCS_TXAGC2 (RTL8712_RATECTRL_ + 0x62)
#define MCS_TXAGC3 (RTL8712_RATECTRL_ + 0x63)
#define MCS_TXAGC4 (RTL8712_RATECTRL_ + 0x64)
#define MCS_TXAGC5 (RTL8712_RATECTRL_ + 0x65)
#define MCS_TXAGC6 (RTL8712_RATECTRL_ + 0x66)
#define MCS_TXAGC7 (RTL8712_RATECTRL_ + 0x67)
#define CCK_TXAGC (RTL8712_RATECTRL_ + 0x68)
#endif /*__RTL8712_RATECTRL_REGDEF_H__*/

1080
drivers/staging/rtl8712/rtl8712_recv.c
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File diff suppressed because it is too large Load Diff

145
drivers/staging/rtl8712/rtl8712_recv.h
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@ -1,145 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
*
* Modifications for inclusion into the Linux staging tree are
* Copyright(c) 2010 Larry Finger. All rights reserved.
*
* Contact information:
* WLAN FAE <wlanfae@realtek.com>
* Larry Finger <Larry.Finger@lwfinger.net>
*
******************************************************************************/
#ifndef _RTL8712_RECV_H_
#define _RTL8712_RECV_H_
#include "osdep_service.h"
#include "drv_types.h"
/* Realtek's v2.6.6 reduced this to 4. However, under heavy network and CPU
* loads, even 8 receive buffers might not be enough; cutting it to 4 seemed
* unwise.
*/
#define NR_RECVBUFF (8)
#define NR_PREALLOC_RECV_SKB (8)
#define RXDESC_SIZE 24
#define RXDESC_OFFSET RXDESC_SIZE
#define RECV_BLK_SZ 512
#define RECV_BLK_CNT 16
#define RECV_BLK_TH RECV_BLK_CNT
#define MAX_RECVBUF_SZ 9100
#define RECVBUFF_ALIGN_SZ 512
#define RSVD_ROOM_SZ (0)
/*These definition is used for Rx packet reordering.*/
#define SN_LESS(a, b) (((a-b) & 0x800) != 0)
#define SN_EQUAL(a, b) (a == b)
#define REORDER_WAIT_TIME 30 /* (ms)*/
struct recv_stat {
__le32 rxdw0;
__le32 rxdw1;
__le32 rxdw2;
__le32 rxdw3;
__le32 rxdw4;
__le32 rxdw5;
};
struct phy_cck_rx_status {
/* For CCK rate descriptor. This is a unsigned 8:1 variable.
* LSB bit present 0.5. And MSB 7 bts present a signed value.
* Range from -64~+63.5.
*/
u8 adc_pwdb_X[4];
u8 sq_rpt;
u8 cck_agc_rpt;
};
struct phy_stat {
__le32 phydw0;
__le32 phydw1;
__le32 phydw2;
__le32 phydw3;
__le32 phydw4;
__le32 phydw5;
__le32 phydw6;
__le32 phydw7;
};
#define PHY_STAT_GAIN_TRSW_SHT 0
#define PHY_STAT_PWDB_ALL_SHT 4
#define PHY_STAT_CFOSHO_SHT 5
#define PHY_STAT_CCK_AGC_RPT_SHT 5
#define PHY_STAT_CFOTAIL_SHT 9
#define PHY_STAT_RXEVM_SHT 13
#define PHY_STAT_RXSNR_SHT 15
#define PHY_STAT_PDSNR_SHT 19
#define PHY_STAT_CSI_CURRENT_SHT 21
#define PHY_STAT_CSI_TARGET_SHT 23
#define PHY_STAT_SIGEVM_SHT 25
#define PHY_STAT_MAX_EX_PWR_SHT 26
union recvstat {
struct recv_stat recv_stat;
unsigned int value[RXDESC_SIZE>>2];
};
struct recv_buf {
struct list_head list;
spinlock_t recvbuf_lock;
u32 ref_cnt;
struct _adapter *adapter;
struct urb *purb;
_pkt *pskb;
u8 irp_pending;
u32 transfer_len;
uint len;
u8 *phead;
u8 *pdata;
u8 *ptail;
u8 *pend;
u8 *pbuf;
u8 *pallocated_buf;
};
/*
* head ----->
* data ----->
* payload
* tail ----->
* end ----->
* len = (unsigned int )(tail - data);
*/
struct recv_frame_hdr {
struct list_head list;
_pkt *pkt;
_pkt *pkt_newalloc;
struct _adapter *adapter;
u8 fragcnt;
struct rx_pkt_attrib attrib;
uint len;
u8 *rx_head;
u8 *rx_data;
u8 *rx_tail;
u8 *rx_end;
void *precvbuf;
struct sta_info *psta;
/*for A-MPDU Rx reordering buffer control*/
struct recv_reorder_ctrl *preorder_ctrl;
};
union recv_frame {
union {
struct list_head list;
struct recv_frame_hdr hdr;
} u;
};
void r8712_init_recvbuf(struct _adapter *padapter, struct recv_buf *precvbuf);
void r8712_rxcmd_event_hdl(struct _adapter *padapter, void *prxcmdbuf);
s32 r8712_signal_scale_mapping(s32 cur_sig);
void r8712_reordering_ctrl_timeout_handler(void *pcontext);
#endif

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