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arm64/sysreg: Update TCR_EL1 register

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Update TCR_EL1 register fields as per latest ARM ARM DDI 0487 L.B and while
here drop an explicit sysreg definition SYS_TCR_EL1 from sysreg.h, which is
now redundant.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Reviewed-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
This commit is contained in:
Anshuman Khandual 2025-09-21 06:22:58 +05:30 committed by Will Deacon
parent 382cbbe7fb
commit 14f158552e
2 changed files with 44 additions and 10 deletions
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2
arch/arm64/include/asm/sysreg.h
View File

@ -281,8 +281,6 @@
#define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5)
#define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6)
#define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2)
#define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0)
#define SYS_APIAKEYHI_EL1 sys_reg(3, 0, 2, 1, 1)
#define SYS_APIBKEYLO_EL1 sys_reg(3, 0, 2, 1, 2)

52
arch/arm64/tools/sysreg
View File

@ -4748,17 +4748,53 @@ Field 37 TBI0
Field 36 AS
Res0 35
Field 34:32 IPS
Field 31:30 TG1
Field 29:28 SH1
Field 27:26 ORGN1
Field 25:24 IRGN1
Enum 31:30 TG1
0b01 16K
0b10 4K
0b11 64K
EndEnum
Enum 29:28 SH1
0b00 NONE
0b10 OUTER
0b11 INNER
EndEnum
Enum 27:26 ORGN1
0b00 NC
0b01 WBWA
0b10 WT
0b11 WBnWA
EndEnum
Enum 25:24 IRGN1
0b00 NC
0b01 WBWA
0b10 WT
0b11 WBnWA
EndEnum
Field 23 EPD1
Field 22 A1
Field 21:16 T1SZ
Field 15:14 TG0
Field 13:12 SH0
Field 11:10 ORGN0
Field 9:8 IRGN0
Enum 15:14 TG0
0b00 4K
0b01 64K
0b10 16K
EndEnum
Enum 13:12 SH0
0b00 NONE
0b10 OUTER
0b11 INNER
EndEnum
Enum 11:10 ORGN0
0b00 NC
0b01 WBWA
0b10 WT
0b11 WBnWA
EndEnum
Enum 9:8 IRGN0
0b00 NC
0b01 WBWA
0b10 WT
0b11 WBnWA
EndEnum
Field 7 EPD0
Res0 6
Field 5:0 T0SZ