From 4184f0190792aea06553af963741a24cc9b47689 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 13 Aug 2025 01:59:27 +0800 Subject: [PATCH 01/20] arm64: dts: allwinner: a527: cubie-a5e: Add LEDs The Radxa Cubie A5E has a 3-color LED. The green and blue LEDs are wired to GPIO pins on the SoC, and the green one is lit by default to serve as a power indicator. The red LED is wired to the M.2 slot. Add device nodes for the green and blue LEDs. A default "heartbeat" trigger is set for the green power LED, though in practice it might be better if it were inverted, i.e. lit most of the time. Acked-by: Jernej Skrabec Link: https://patch.msgid.link/20250812175927.2199219-1-wens@kernel.org Signed-off-by: Chen-Yu Tsai --- .../dts/allwinner/sun55i-a527-cubie-a5e.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts index 553ad774ed13..70d439bc845c 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts @@ -6,6 +6,7 @@ #include "sun55i-a523.dtsi" #include +#include / { model = "Radxa Cubie A5E"; @@ -27,6 +28,24 @@ clock-output-names = "ext_osc32k"; }; + leds { + compatible = "gpio-leds"; + + power-led { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>; /* PL4 */ + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + use-led { + function = LED_FUNCTION_ACTIVITY; + color = ; + gpios = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL5 */ + }; + }; + reg_vcc5v: vcc5v { /* board wide 5V supply from the USB-C connector */ compatible = "regulator-fixed"; From a15f095b590bcc1968fbf2ced8fe87fbd8d012e0 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 9 Sep 2025 02:10:55 +0800 Subject: [PATCH 02/20] arm64: dts: allwinner: a527: cubie-a5e: Add ethernet PHY reset setting The external Ethernet PHY has a reset pin that is connected to the SoC. It is missing from the original submission. Add it to complete the description. Fixes: acca163f3f51 ("arm64: dts: allwinner: a527: add EMAC0 to Radxa A5E board") Acked-by: Jernej Skrabec Link: https://patch.msgid.link/20250908181059.1785605-7-wens@kernel.org Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts index 70d439bc845c..d4cee2222104 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts @@ -94,6 +94,9 @@ ext_rgmii_phy: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; + reset-gpios = <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */ + reset-assert-us = <10000>; + reset-deassert-us = <150000>; }; }; From 8dc3f973b2ff7ea19f7637983c11b005daa8fe45 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 9 Sep 2025 02:10:57 +0800 Subject: [PATCH 03/20] arm64: dts: allwinner: t527: avaota-a1: Add ethernet PHY reset setting The external Ethernet PHY has a reset pin that is connected to the SoC. It is missing from the original submission. Add it to complete the description. Fixes: c6800f15998b ("arm64: dts: allwinner: t527: add EMAC0 to Avaota-A1 board") Acked-by: Jernej Skrabec Link: https://patch.msgid.link/20250908181059.1785605-9-wens@kernel.org Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts index b9eeb6753e9e..e7713678208d 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts @@ -85,6 +85,9 @@ ext_rgmii_phy: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; + reset-gpios = <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */ + reset-assert-us = <10000>; + reset-deassert-us = <150000>; }; }; From e9671ddd82eee96146a7359431a4e1f04ac2b076 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 12 Sep 2025 01:47:04 +0800 Subject: [PATCH 04/20] dt-bindings: clock: sun55i-a523-ccu: Add missing NPU module clock The main clock controller on the A523/T527 has the NPU's module clock. It was missing from the original submission, likely because that was based on the A523 user manual; the A523 is marketed without the NPU. Reviewed-by: Andre Przywara Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20250911174710.3149589-2-wens@kernel.org Signed-off-by: Chen-Yu Tsai --- include/dt-bindings/clock/sun55i-a523-ccu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/sun55i-a523-ccu.h b/include/dt-bindings/clock/sun55i-a523-ccu.h index c8259ac5ada7..54808fcfd556 100644 --- a/include/dt-bindings/clock/sun55i-a523-ccu.h +++ b/include/dt-bindings/clock/sun55i-a523-ccu.h @@ -185,5 +185,6 @@ #define CLK_FANOUT0 176 #define CLK_FANOUT1 177 #define CLK_FANOUT2 178 +#define CLK_NPU 179 #endif /* _DT_BINDINGS_CLK_SUN55I_A523_CCU_H_ */ From 0f610e650d4e979490ccfa4c22ca29ca547f41e7 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 12 Sep 2025 01:47:05 +0800 Subject: [PATCH 05/20] dt-bindings: clock: sun55i-a523-ccu: Add A523 MCU CCU clock controller There are four clock controllers in the A523 SoC. The existing binding already covers two of them that are critical for basic operation. The remaining ones are the MCU clock controller and CPU PLL clock controller. Add a description for the MCU CCU. This unit controls and provides clocks to the MCU (RISC-V) subsystem and peripherals meant to operate under low power conditions. Reviewed-by: Rob Herring (Arm) Link: https://patch.msgid.link/20250911174710.3149589-3-wens@kernel.org Signed-off-by: Chen-Yu Tsai --- .../clock/allwinner,sun55i-a523-ccu.yaml | 37 ++++++++++++- .../dt-bindings/clock/sun55i-a523-mcu-ccu.h | 54 +++++++++++++++++++ .../dt-bindings/reset/sun55i-a523-mcu-ccu.h | 30 +++++++++++ 3 files changed, 119 insertions(+), 2 deletions(-) create mode 100644 include/dt-bindings/clock/sun55i-a523-mcu-ccu.h create mode 100644 include/dt-bindings/reset/sun55i-a523-mcu-ccu.h diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun55i-a523-ccu.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun55i-a523-ccu.yaml index f5f62e9a10a1..58be701a720e 100644 --- a/Documentation/devicetree/bindings/clock/allwinner,sun55i-a523-ccu.yaml +++ b/Documentation/devicetree/bindings/clock/allwinner,sun55i-a523-ccu.yaml @@ -19,6 +19,7 @@ properties: compatible: enum: - allwinner,sun55i-a523-ccu + - allwinner,sun55i-a523-mcu-ccu - allwinner,sun55i-a523-r-ccu reg: @@ -26,11 +27,11 @@ properties: clocks: minItems: 4 - maxItems: 5 + maxItems: 9 clock-names: minItems: 4 - maxItems: 5 + maxItems: 9 required: - "#clock-cells" @@ -63,6 +64,38 @@ allOf: - const: iosc - const: losc-fanout + - if: + properties: + compatible: + enum: + - allwinner,sun55i-a523-mcu-ccu + + then: + properties: + clocks: + items: + - description: High Frequency Oscillator (usually at 24MHz) + - description: Low Frequency Oscillator (usually at 32kHz) + - description: Internal Oscillator + - description: Audio PLL (4x) + - description: Peripherals PLL 0 (300 MHz output) + - description: DSP module clock + - description: MBUS clock + - description: PRCM AHB clock + - description: PRCM APB0 clock + + clock-names: + items: + - const: hosc + - const: losc + - const: iosc + - const: pll-audio0-4x + - const: pll-periph0-300m + - const: dsp + - const: mbus + - const: r-ahb + - const: r-apb0 + - if: properties: compatible: diff --git a/include/dt-bindings/clock/sun55i-a523-mcu-ccu.h b/include/dt-bindings/clock/sun55i-a523-mcu-ccu.h new file mode 100644 index 000000000000..6efc6bc7e11a --- /dev/null +++ b/include/dt-bindings/clock/sun55i-a523-mcu-ccu.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (C) 2025 Chen-Yu Tsai + */ + +#ifndef _DT_BINDINGS_CLK_SUN55I_A523_MCU_CCU_H_ +#define _DT_BINDINGS_CLK_SUN55I_A523_MCU_CCU_H_ + +#define CLK_MCU_PLL_AUDIO1 0 +#define CLK_MCU_PLL_AUDIO1_DIV2 1 +#define CLK_MCU_PLL_AUDIO1_DIV5 2 +#define CLK_MCU_AUDIO_OUT 3 +#define CLK_MCU_DSP 4 +#define CLK_MCU_I2S0 5 +#define CLK_MCU_I2S1 6 +#define CLK_MCU_I2S2 7 +#define CLK_MCU_I2S3 8 +#define CLK_MCU_I2S3_ASRC 9 +#define CLK_BUS_MCU_I2S0 10 +#define CLK_BUS_MCU_I2S1 11 +#define CLK_BUS_MCU_I2S2 12 +#define CLK_BUS_MCU_I2S3 13 +#define CLK_MCU_SPDIF_TX 14 +#define CLK_MCU_SPDIF_RX 15 +#define CLK_BUS_MCU_SPDIF 16 +#define CLK_MCU_DMIC 17 +#define CLK_BUS_MCU_DMIC 18 +#define CLK_MCU_AUDIO_CODEC_DAC 19 +#define CLK_MCU_AUDIO_CODEC_ADC 20 +#define CLK_BUS_MCU_AUDIO_CODEC 21 +#define CLK_BUS_MCU_DSP_MSGBOX 22 +#define CLK_BUS_MCU_DSP_CFG 23 +#define CLK_BUS_MCU_NPU_HCLK 24 +#define CLK_BUS_MCU_NPU_ACLK 25 +#define CLK_MCU_TIMER0 26 +#define CLK_MCU_TIMER1 27 +#define CLK_MCU_TIMER2 28 +#define CLK_MCU_TIMER3 29 +#define CLK_MCU_TIMER4 30 +#define CLK_MCU_TIMER5 31 +#define CLK_BUS_MCU_TIMER 32 +#define CLK_BUS_MCU_DMA 33 +#define CLK_MCU_TZMA0 34 +#define CLK_MCU_TZMA1 35 +#define CLK_BUS_MCU_PUBSRAM 36 +#define CLK_MCU_MBUS_DMA 37 +#define CLK_MCU_MBUS 38 +#define CLK_MCU_RISCV 39 +#define CLK_BUS_MCU_RISCV_CFG 40 +#define CLK_BUS_MCU_RISCV_MSGBOX 41 +#define CLK_MCU_PWM0 42 +#define CLK_BUS_MCU_PWM0 43 + +#endif /* _DT_BINDINGS_CLK_SUN55I_A523_MCU_CCU_H_ */ diff --git a/include/dt-bindings/reset/sun55i-a523-mcu-ccu.h b/include/dt-bindings/reset/sun55i-a523-mcu-ccu.h new file mode 100644 index 000000000000..a89a0b44f08b --- /dev/null +++ b/include/dt-bindings/reset/sun55i-a523-mcu-ccu.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (C) 2025 Chen-Yu Tsai + */ + +#ifndef _DT_BINDINGS_RST_SUN55I_A523_MCU_CCU_H_ +#define _DT_BINDINGS_RST_SUN55I_A523_MCU_CCU_H_ + +#define RST_BUS_MCU_I2S0 0 +#define RST_BUS_MCU_I2S1 1 +#define RST_BUS_MCU_I2S2 2 +#define RST_BUS_MCU_I2S3 3 +#define RST_BUS_MCU_SPDIF 4 +#define RST_BUS_MCU_DMIC 5 +#define RST_BUS_MCU_AUDIO_CODEC 6 +#define RST_BUS_MCU_DSP_MSGBOX 7 +#define RST_BUS_MCU_DSP_CFG 8 +#define RST_BUS_MCU_NPU 9 +#define RST_BUS_MCU_TIMER 10 +#define RST_BUS_MCU_DSP_DEBUG 11 +#define RST_BUS_MCU_DSP 12 +#define RST_BUS_MCU_DMA 13 +#define RST_BUS_MCU_PUBSRAM 14 +#define RST_BUS_MCU_RISCV_CFG 15 +#define RST_BUS_MCU_RISCV_DEBUG 16 +#define RST_BUS_MCU_RISCV_CORE 17 +#define RST_BUS_MCU_RISCV_MSGBOX 18 +#define RST_BUS_MCU_PWM0 19 + +#endif /* _DT_BINDINGS_RST_SUN55I_A523_MCU_CCU_H_ */ From edd63e54e516b54c0b7071463d6e839445efab68 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 12 Sep 2025 01:47:09 +0800 Subject: [PATCH 06/20] arm64: dts: allwinner: a523: Add MCU PRCM CCU node Add a device node for the third supported clock controller found in the A523 / T527 SoCs. This controller has clocks and resets for the RISC-V MCU, and others peripherals possibly meant to operate in low power mode driven by the MCU, such as audio interfaces, an audio DSP, and the NPU. Reviewed-by: Andre Przywara Reviewed-by: Jernej Skrabec Link: https://patch.msgid.link/20250911174710.3149589-7-wens@kernel.org Signed-off-by: Chen-Yu Tsai --- .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi index 6b6f2296bdff..a5100e5d19aa 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -4,8 +4,10 @@ #include #include #include +#include #include #include +#include #include #include #include @@ -690,5 +692,30 @@ clock-names = "bus", "hosc", "ahb"; #clock-cells = <1>; }; + + mcu_ccu: clock-controller@7102000 { + compatible = "allwinner,sun55i-a523-mcu-ccu"; + reg = <0x7102000 0x200>; + clocks = <&osc24M>, + <&rtc CLK_OSC32K>, + <&rtc CLK_IOSC>, + <&ccu CLK_PLL_AUDIO0_4X>, + <&ccu CLK_PLL_PERIPH0_300M>, + <&ccu CLK_DSP>, + <&ccu CLK_MBUS>, + <&r_ccu CLK_R_AHB>, + <&r_ccu CLK_R_APB0>; + clock-names = "hosc", + "losc", + "iosc", + "pll-audio0-4x", + "pll-periph0-300m", + "dsp", + "mbus", + "r-ahb", + "r-apb0"; + #clock-cells = <1>; + #reset-cells = <1>; + }; }; }; From a1845487afd06899502714a3500b60f815d98203 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 12 Sep 2025 01:47:10 +0800 Subject: [PATCH 07/20] arm64: dts: allwinner: a523: Add NPU device node The Allwinner T527 SoC has an NPU built in. Based on identifiers found in the BSP, it is a Vivante IP block. After enabling it, the etnaviv driver reports it as a GC9000 revision 9003. The standard bindings are used as everything matches directly. There is no option for DVFS at the moment. That might require some more work, perhaps on the efuse side to map speed bins. It is unclear whether the NPU block is fused out at the hardware level or the BSP limits use of the NPU through software, as the author only has boards with the T527. Reviewed-by: Andre Przywara Reviewed-by: Jernej Skrabec Link: https://patch.msgid.link/20250911174710.3149589-8-wens@kernel.org Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi index a5100e5d19aa..d00da1cd744e 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -717,5 +717,17 @@ #clock-cells = <1>; #reset-cells = <1>; }; + + npu: npu@7122000 { + compatible = "vivante,gc"; + reg = <0x07122000 0x1000>; + interrupts = ; + clocks = <&mcu_ccu CLK_BUS_MCU_NPU_ACLK>, + <&ccu CLK_NPU>, + <&mcu_ccu CLK_BUS_MCU_NPU_HCLK>; + clock-names = "bus", "core", "reg"; + resets = <&mcu_ccu RST_BUS_MCU_NPU>; + power-domains = <&ppu PD_NPU>; + }; }; }; From 3173a760021b9340923831aa5edc5530d61a6b9b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=2E=20Neusch=C3=A4fer?= Date: Thu, 11 Sep 2025 22:23:55 +0200 Subject: [PATCH 08/20] ARM: dts: allwinner: orangepi-zero: Add default audio routing MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Line out playback and microphone capture work, after enabling the corresponding ALSA controls. Tested with the Orange Pi Zero interface board. Signed-off-by: J. Neuschäfer Link: https://patch.msgid.link/20250911-opz-audio-v3-1-9dfd317a8163@posteo.net Signed-off-by: Chen-Yu Tsai --- .../dts/allwinner/sun8i-h2-plus-orangepi-zero.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts index 1b001f2ad0ef..b23cec5b89eb 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts +++ b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts @@ -112,6 +112,20 @@ }; }; +/* + * Audio input/output is exposed on the 13-pin header and can't be used for + * anything else. However, adapter boards may use different audio routing. + * - https://linux-sunxi.org/Xunlong_Orange_Pi_Zero#Expansion_Port + * - Allwinner H3 Datasheet, section 3.1. Pin Characteristics + */ +&codec { + allwinner,audio-routing = + "Line Out", "LINEOUT", + "MIC1", "Mic", + "Mic", "MBIAS"; + status = "disabled"; +}; + &cpu0 { cpu-supply = <®_vdd_cpux>; }; From fd5c7bf8ddb51373a6c9456865b3af99f53642a2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=2E=20Neusch=C3=A4fer?= Date: Thu, 11 Sep 2025 22:23:56 +0200 Subject: [PATCH 09/20] ARM: dts: allwinner: orangepi-zero-plus2: Add default audio routing MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Orange Pi Zero Plus 2 has the same pinout[1] as the Orange Pi Zero[2] (with the possible exception of line-out left/right being swapped), and the Orange Pi Zero Interface Board is sold[3] as compatible with both of them. We can thus use the same audio routing. [1]: http://www.orangepi.org/html/hardWare/computerAndMicrocontrollers/details/Orange-Pi-Zero-Plus-2.html [2]: https://linux-sunxi.org/Xunlong_Orange_Pi_Zero#Expansion_Port [3]: https://orangepi.com/index.php?route=product/product&product_id=871 Signed-off-by: J. Neuschäfer Link: https://patch.msgid.link/20250911-opz-audio-v3-2-9dfd317a8163@posteo.net Signed-off-by: Chen-Yu Tsai --- .../dts/allwinner/sun8i-h3-orangepi-zero-plus2.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-zero-plus2.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-zero-plus2.dts index 7a6444a10e25..97a3565ac7a8 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-zero-plus2.dts +++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-zero-plus2.dts @@ -99,6 +99,20 @@ }; }; +/* + * Audio input/output is exposed on the 13-pin header and can't be used for + * anything else. However, adapter boards may use different audio routing. + * - http://www.orangepi.org/html/hardWare/computerAndMicrocontrollers/details/Orange-Pi-Zero-Plus-2.html + * - Allwinner H3 Datasheet, section 3.1. Pin Characteristics + */ +&codec { + allwinner,audio-routing = + "Line Out", "LINEOUT", + "MIC1", "Mic", + "Mic", "MBIAS"; + status = "disabled"; +}; + &de { status = "okay"; }; From b65ee02e77cb14486cf30709e978430e91f74d2e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=2E=20Neusch=C3=A4fer?= Date: Thu, 11 Sep 2025 22:23:57 +0200 Subject: [PATCH 10/20] ARM: dts: allwinner: Add Orange Pi Zero Interface Board overlay MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Orange Pi Zero interface board is a (mostly) passive adapter from the 13-pin header of the Orange Pi Zero and Orange Pi Zero Plus2 to standard connectors (2x USB A, 1x Audio/Video output, 1x built-in microphone, 1x infrared input). Headphones, microphone, infrared (CIR) input, and USB have been tested with the Orange Pi Zero. CVBS output is currently not supported. https://orangepi.com/index.php?route=product/product&product_id=871 Signed-off-by: J. Neuschäfer Link: https://patch.msgid.link/20250911-opz-audio-v3-3-9dfd317a8163@posteo.net Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/allwinner/Makefile | 7 +++ .../sun8i-orangepi-zero-interface-board.dtso | 46 +++++++++++++++++++ 2 files changed, 53 insertions(+) create mode 100644 arch/arm/boot/dts/allwinner/sun8i-orangepi-zero-interface-board.dtso diff --git a/arch/arm/boot/dts/allwinner/Makefile b/arch/arm/boot/dts/allwinner/Makefile index d799ad153b37..97d0a205493f 100644 --- a/arch/arm/boot/dts/allwinner/Makefile +++ b/arch/arm/boot/dts/allwinner/Makefile @@ -182,6 +182,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \ sun7i-a20-wits-pro-a20-dkt.dtb # Enables support for device-tree overlays for all pis +DTC_FLAGS_sun8i-h2-plus-orangepi-zero := -@ DTC_FLAGS_sun8i-h3-orangepi-lite := -@ DTC_FLAGS_sun8i-h3-bananapi-m2-plus := -@ DTC_FLAGS_sun8i-h3-nanopi-m1-plus := -@ @@ -225,6 +226,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-h2-plus-libretech-all-h3-cc.dtb \ sun8i-h2-plus-orangepi-r1.dtb \ sun8i-h2-plus-orangepi-zero.dtb \ + sun8i-h2-plus-orangepi-zero-interface-board.dtb \ sun8i-h3-bananapi-m2-plus.dtb \ sun8i-h3-bananapi-m2-plus-v1.2.dtb \ sun8i-h3-beelink-x2.dtb \ @@ -244,6 +246,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-h3-orangepi-plus.dtb \ sun8i-h3-orangepi-plus2e.dtb \ sun8i-h3-orangepi-zero-plus2.dtb \ + sun8i-h3-orangepi-zero-plus2-interface-board.dtb \ sun8i-h3-rervision-dvk.dtb \ sun8i-h3-zeropi.dtb \ sun8i-h3-emlid-neutis-n5h3-devboard.dtb \ @@ -264,6 +267,10 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-v3s-licheepi-zero-dock.dtb \ sun8i-v3s-netcube-kumquat.dtb \ sun8i-v40-bananapi-m2-berry.dtb +sun8i-h2-plus-orangepi-zero-interface-board-dtbs += \ + sun8i-h2-plus-orangepi-zero.dtb sun8i-orangepi-zero-interface-board.dtbo +sun8i-h3-orangepi-zero-plus2-interface-board-dtbs += \ + sun8i-h3-orangepi-zero-plus2.dtb sun8i-orangepi-zero-interface-board.dtbo dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-optimus.dtb \ sun9i-a80-cubieboard4.dtb diff --git a/arch/arm/boot/dts/allwinner/sun8i-orangepi-zero-interface-board.dtso b/arch/arm/boot/dts/allwinner/sun8i-orangepi-zero-interface-board.dtso new file mode 100644 index 000000000000..e137eefee341 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-orangepi-zero-interface-board.dtso @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR X11) +/* + * Copyright (C) 2025 J. Neuschäfer + * + * Devicetree overlay for the Orange Pi Zero Interface board (OP0014). + * + * https://orangepi.com/index.php?route=product/product&product_id=871 + * + * This overlay applies to the following base files: + * + * - arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts + * - arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-zero-plus2.dts + */ + +/dts-v1/; +/plugin/; + +&codec { + status = "okay"; +}; + +&de { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&ehci3 { + status = "okay"; +}; + +&ir { + pinctrl-names = "default"; + pinctrl-0 = <&r_ir_rx_pin>; + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +&ohci3 { + status = "okay"; +}; From db5796c5c5c6db72339e818b54e6a2e043f7032c Mon Sep 17 00:00:00 2001 From: Lukas Schmid Date: Sun, 31 Aug 2025 18:25:30 +0200 Subject: [PATCH 11/20] dt-bindings: arm: sunxi: Add NetCube Systems Nagami SoM and carrier board bindings The NetCube Systems Nagami is an System on Module base on the Allwinner T113s SoC. It is intended to be used in low cost devices which require simple layouts and low BOM cost. The NetCube Systems Nagami Basic Carrier Board is a simple carrier for the Nagami SoM. It is intended to serve as a simple reference design for a custom implementation or just evaluating the module with other peripherals The NetCube Systems Nagami Keypad Carrier is a custom board intended to fit a standard Ritto Intercom enclosure and provides a Keypad, NFC-Reader and Status-LED all controllable over Ethernet with PoE support. Signed-off-by: Lukas Schmid Reviewed-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20250831162536.2380589-2-lukas.schmid@netcube.li Signed-off-by: Chen-Yu Tsai --- Documentation/devicetree/bindings/arm/sunxi.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index c25a22fe4d25..72ef861a0b68 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -595,6 +595,14 @@ properties: - const: netcube,kumquat - const: allwinner,sun8i-v3s + - description: NetCube Systems Nagami SoM based boards + items: + - enum: + - netcube,nagami-basic-carrier + - netcube,nagami-keypad-carrier + - const: netcube,nagami + - const: allwinner,sun8i-t113s + - description: NextThing Co. CHIP items: - const: nextthing,chip From cbce6d5326b116f55dc29f7fc0a7d56a9a03d9e5 Mon Sep 17 00:00:00 2001 From: Lukas Schmid Date: Sun, 31 Aug 2025 18:25:31 +0200 Subject: [PATCH 12/20] riscv: dts: allwinner: d1s-t113: Add pinctrl's required by NetCube Systems Nagami SoM Added the following pinctrl's used by the NetCube Systems Nagami SoM * i2c2_pins * i2c3_pins * i2s1_pins, i2s1_din_pins, i2s1_dout_pins * spi1_pins, spi1_hold_pin, spi1_wp_pin Signed-off-by: Lukas Schmid Link: https://patch.msgid.link/20250831162536.2380589-3-lukas.schmid@netcube.li [wens@csie.org: Fix up node names and labels for i2c* and i2s1_d* pins] Signed-off-by: Chen-Yu Tsai --- .../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi index e4175adb028d..63e252b44973 100644 --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi @@ -78,6 +78,36 @@ function = "dsi"; }; + /omit-if-no-ref/ + i2c2_pd_pins: i2c2-pd-pins { + pins = "PD20", "PD21"; + function = "i2c2"; + }; + + /omit-if-no-ref/ + i2c3_pg_pins: i2c3-pg-pins { + pins = "PG10", "PG11"; + function = "i2c3"; + }; + + /omit-if-no-ref/ + i2s1_pins: i2s1-pins { + pins = "PG12", "PG13"; + function = "i2s1"; + }; + + /omit-if-no-ref/ + i2s1_din0_pin: i2s1-din0-pin { + pins = "PG14"; + function = "i2s1_din"; + }; + + /omit-if-no-ref/ + i2s1_dout0_pin: i2s1-dout0-pin { + pins = "PG15"; + function = "i2s1_dout"; + }; + /omit-if-no-ref/ lcd_rgb666_pins: lcd-rgb666-pins { pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", @@ -126,6 +156,24 @@ function = "spi0"; }; + /omit-if-no-ref/ + spi1_pins: spi1-pins { + pins = "PD10", "PD11", "PD12", "PD13"; + function = "spi1"; + }; + + /omit-if-no-ref/ + spi1_hold_pin: spi1-hold-pin { + pins = "PD14"; + function = "spi1"; + }; + + /omit-if-no-ref/ + spi1_wp_pin: spi1-wp-pin { + pins = "PD15"; + function = "spi1"; + }; + /omit-if-no-ref/ uart1_pg6_pins: uart1-pg6-pins { pins = "PG6", "PG7"; From cba2febbd6465aabdff157fb95b1c07d090af1f0 Mon Sep 17 00:00:00 2001 From: Lukas Schmid Date: Sun, 31 Aug 2025 18:25:32 +0200 Subject: [PATCH 13/20] ARM: dts: sunxi: add support for NetCube Systems Nagami SoM NetCube Systems Nagami SoM is a module based around the Allwinner T113s SoC. It includes the following features and interfaces: - 128MB DDR3 included in SoC - 10/100 Mbps Ethernet using LAN8720A phy - One USB-OTG interface - One USB-Host interface - One I2S interface with in and output support - Two CAN interfaces - ESP32 over SDIO - One SPI interface - I2C EEPROM for MAC address - One QWIIC I2C Interface with dedicated interrupt pin shared with EEPROM - One external I2C interface - SD interface for external SD-Card Signed-off-by: Lukas Schmid Link: https://patch.msgid.link/20250831162536.2380589-4-lukas.schmid@netcube.li [wens@csie.org: fix up pinctrl names for i2c* and i2s_d*; fix indentation for gpio-line-names and rmii_pe_pins; fix "pre-magnetics" typo in comment] Signed-off-by: Chen-Yu Tsai --- .../allwinner/sun8i-t113s-netcube-nagami.dtsi | 250 ++++++++++++++++++ 1 file changed, 250 insertions(+) create mode 100644 arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami.dtsi diff --git a/arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami.dtsi b/arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami.dtsi new file mode 100644 index 000000000000..544d60cfc32e --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami.dtsi @@ -0,0 +1,250 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2025 Lukas Schmid + */ + +/dts-v1/; +#include "sun8i-t113s.dtsi" + +#include +#include + +/ { + model = "NetCube Systems Nagami SoM"; + compatible = "netcube,nagami", "allwinner,sun8i-t113s"; + + aliases { + serial1 = &uart1; // ESP32 Bootloader UART + serial3 = &uart3; // Console UART on Card Edge + ethernet0 = &emac; + }; + + chosen { + stdout-path = "serial3:115200n8"; + }; + + /* module wide 3.3V supply directly from the card edge */ + reg_vcc3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + /* SY8008 DC/DC regulator on the board, also supplying VDD-SYS */ + reg_vcc_core: regulator-core { + compatible = "regulator-fixed"; + regulator-name = "vcc-core"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + vin-supply = <®_vcc3v3>; + }; + + /* USB0 MUX to switch connect to Card-Edge only after BootROM */ + usb0_sec_mux: mux-controller{ + compatible = "gpio-mux"; + #mux-control-cells = <0>; + mux-gpios = <&pio 3 9 GPIO_ACTIVE_HIGH>; /* PD9 */ + idle-state = <1>; /* USB connected to Card-Edge by default */ + }; + + /* Reset of ESP32 */ + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pio 6 9 GPIO_ACTIVE_LOW>; /* PG9 */ + post-power-on-delay-ms = <1500>; + power-off-delay-us = <200>; + }; +}; + +&cpu0 { + cpu-supply = <®_vcc_core>; +}; + +&cpu1 { + cpu-supply = <®_vcc_core>; +}; + +&dcxo { + clock-frequency = <24000000>; +}; + +&emac { + nvmem-cells = <ð0_macaddress>; + nvmem-cell-names = "mac-address"; + phy-handle = <&lan8720a>; + phy-mode = "rmii"; + pinctrl-0 = <&rmii_pe_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* Default I2C Interface on Card-Edge */ +&i2c2 { + pinctrl-0 = <&i2c2_pd_pins>; + pinctrl-names = "default"; + status = "disabled"; +}; + +/* Exposed as the QWIIC connector and used by the internal EEPROM */ +&i2c3 { + pinctrl-0 = <&i2c3_pg_pins>; + pinctrl-names = "default"; + status = "okay"; + + eeprom0: eeprom@50 { + compatible = "atmel,24c02"; /* actually it's a 24AA02E48 */ + reg = <0x50>; + pagesize = <16>; + read-only; + vcc-supply = <®_vcc3v3>; + + #address-cells = <1>; + #size-cells = <1>; + + eth0_macaddress: macaddress@fa { + reg = <0xfa 0x06>; + }; + }; +}; + +/* Default I2S Interface on Card-Edge */ +&i2s1 { + pinctrl-0 = <&i2s1_pins>, <&i2s1_din0_pin>, <&i2s1_dout0_pin>; + pinctrl-names = "default"; + status = "disabled"; +}; + +/* Phy is on SoM. MDI signals pre-magnetics are on the card edge */ +&mdio { + lan8720a: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + +/* Default SD Interface on Card-Edge */ +&mmc0 { + pinctrl-0 = <&mmc0_pins>; + pinctrl-names = "default"; + status = "disabled"; +}; + +/* Connected to the on-board ESP32 */ +&mmc1 { + pinctrl-0 = <&mmc1_pins>; + pinctrl-names = "default"; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + non-removable; + mmc-pwrseq = <&wifi_pwrseq>; + status = "okay"; +}; + +/* Connected to the on-board eMMC */ +&mmc2 { + pinctrl-0 = <&mmc2_pins>; + pinctrl-names = "default"; + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&pio { + vcc-pb-supply = <®_vcc3v3>; + vcc-pc-supply = <®_vcc3v3>; + vcc-pd-supply = <®_vcc3v3>; + vcc-pe-supply = <®_vcc3v3>; + vcc-pf-supply = <®_vcc3v3>; + vcc-pg-supply = <®_vcc3v3>; + + gpio-line-names = "", "", "", "", // PA + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "CAN0_TX", "CAN0_RX", // PB + "CAN1_TX", "CAN1_RX", "UART3_TX", "UART3_RX", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "eMMC_CLK", "eMMC_CMD", // PC + "eMMC_D2", "eMMC_D1", "eMMC_D0", "eMMC_D3", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", // PD + "", "", "", "", + "", "USB_SEC_EN", "SPI1_CS", "SPI1_CLK", + "SPI1_MOSI", "SPI1_MISO", "SPI1_HOLD", "SPI1_WP", + "PD16", "", "", "", + "I2C2_SCL", "I2C2_SDA", "PD22", "", + "", "", "", "", + "", "", "", "", + "ETH_CRSDV", "ETH_RXD0", "ETH_RXD1", "ETH_TXCK", // PE + "ETH_TXD0", "ETH_TXD1", "ETH_TXEN", "", + "ETH_MDC", "ETH_MDIO", "QWIIC_nINT", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "SD_D1", "SD_D0", "SD_CLK", "SD_CLK", // PF + "SD_D3", "SD_D2", "PF6", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "ESP_CLK", "ESP_CMD", "ESP_D0", "ESP_D1", // PG + "ESP_D2", "ESP_D3", "UART1_TXD", "UART1_RXD", + "ESP_nBOOT", "ESP_nRST", "I2C3_SCL", "I2C3_SDA", + "I2S1_WS", "I2S1_CLK", "I2S1_DIN0", "I2S1_DOUT0", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +/* Remove the unused CK pin from the pinctl as it is unconnected */ +&rmii_pe_pins { + pins = "PE0", "PE1", "PE2", "PE3", "PE4", + "PE5", "PE6", "PE8", "PE9"; +}; + +/* Default SPI Interface on Card-Edge */ +&spi1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&spi1_pins>, <&spi1_hold_pin>, <&spi1_wp_pin>; + pinctrl-names = "default"; + cs-gpios = <0>; + status = "disabled"; +}; + +/* Connected to the Bootloader/Console of the ESP32 */ +&uart1 { + pinctrl-0 = <&uart1_pg6_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* Console/Debug UART on Card-Edge */ +&uart3 { + pinctrl-0 = <&uart3_pb_pins>; + pinctrl-names = "default"; + status = "okay"; +}; From e36d4d54eefb60144666b27754007e1c0dd0a581 Mon Sep 17 00:00:00 2001 From: Lukas Schmid Date: Sun, 31 Aug 2025 18:25:33 +0200 Subject: [PATCH 14/20] ARM: dts: sunxi: add support for NetCube Systems Nagami Basic Carrier The NetCube Systems Nagami Basic Carrier is a Carrier for the Nagami SoM It provides an ethernet port for the phy on the SoM and some USB-Ports. All other interfaces and gpios are available on pinheader, except for the SD-Interface which is available on a micro-sd slot. Signed-off-by: Lukas Schmid Link: https://patch.msgid.link/20250831162536.2380589-5-lukas.schmid@netcube.li [wens@csie.org: fix indentation for board level compatible string fallback] Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/allwinner/Makefile | 2 + ...n8i-t113s-netcube-nagami-basic-carrier.dts | 67 +++++++++++++++++++ 2 files changed, 69 insertions(+) create mode 100644 arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami-basic-carrier.dts diff --git a/arch/arm/boot/dts/allwinner/Makefile b/arch/arm/boot/dts/allwinner/Makefile index 97d0a205493f..865fd8c9d137 100644 --- a/arch/arm/boot/dts/allwinner/Makefile +++ b/arch/arm/boot/dts/allwinner/Makefile @@ -200,6 +200,7 @@ DTC_FLAGS_sun8i-h3-nanopi-r1 := -@ DTC_FLAGS_sun8i-h3-orangepi-pc := -@ DTC_FLAGS_sun8i-h3-bananapi-m2-plus-v1.2 := -@ DTC_FLAGS_sun8i-h3-orangepi-pc-plus := -@ +DTC_FLAGS_sun8i-t113s-netcube-nagami-basic-carrier := -@ DTC_FLAGS_sun8i-v3s-netcube-kumquat := -@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-a23-evb.dtb \ @@ -260,6 +261,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-s3-lichee-zero-plus.dtb \ sun8i-s3-pinecube.dtb \ sun8i-t113s-mangopi-mq-r-t113.dtb \ + sun8i-t113s-netcube-nagami-basic-carrier.dtb \ sun8i-t3-cqa3t-bv3.dtb \ sun8i-v3-sl631-imx179.dtb \ sun8i-v3s-anbernic-rg-nano.dtb \ diff --git a/arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami-basic-carrier.dts b/arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami-basic-carrier.dts new file mode 100644 index 000000000000..5262102a85f6 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami-basic-carrier.dts @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2025 Lukas Schmid + */ + +/dts-v1/; +#include "sun8i-t113s-netcube-nagami.dtsi" + +/ { + model = "NetCube Systems Nagami Basic Carrier Board"; + compatible = "netcube,nagami-basic-carrier", "netcube,nagami", + "allwinner,sun8i-t113s"; +}; + +&can0 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2s1 { + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + broken-cd; + disable-wp; + bus-width = <4>; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&spi1 { + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + status = "okay"; +}; From caffed0800ef4dd29cc29ee17a89d015e867e03a Mon Sep 17 00:00:00 2001 From: Lukas Schmid Date: Sun, 31 Aug 2025 18:25:34 +0200 Subject: [PATCH 15/20] ARM: dts: sunxi: add support for NetCube Systems Nagami Keypad Carrier The NetCube Systems Nagami Keypad Carrier uses the Nagami SoM and contains a TCA8418 connected to a 4x4 matrix keypad. The I2C2 interface is connected to said TCA8418 and also a header for an PN532 NFC-Module. It also provides a pin-header for a bi-color status led. Ethernet with PoE support is available on a screwterminal after magnetics. Signed-off-by: Lukas Schmid Link: https://patch.msgid.link/20250831162536.2380589-6-lukas.schmid@netcube.li [wens@csie.org: fix indentation for board level compatible fallback, gpio-line-names and keypad matrix.] Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/allwinner/Makefile | 1 + ...8i-t113s-netcube-nagami-keypad-carrier.dts | 129 ++++++++++++++++++ 2 files changed, 130 insertions(+) create mode 100644 arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami-keypad-carrier.dts diff --git a/arch/arm/boot/dts/allwinner/Makefile b/arch/arm/boot/dts/allwinner/Makefile index 865fd8c9d137..f71392a55df8 100644 --- a/arch/arm/boot/dts/allwinner/Makefile +++ b/arch/arm/boot/dts/allwinner/Makefile @@ -262,6 +262,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-s3-pinecube.dtb \ sun8i-t113s-mangopi-mq-r-t113.dtb \ sun8i-t113s-netcube-nagami-basic-carrier.dtb \ + sun8i-t113s-netcube-nagami-keypad-carrier.dtb \ sun8i-t3-cqa3t-bv3.dtb \ sun8i-v3-sl631-imx179.dtb \ sun8i-v3s-anbernic-rg-nano.dtb \ diff --git a/arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami-keypad-carrier.dts b/arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami-keypad-carrier.dts new file mode 100644 index 000000000000..4ffa6a0216d8 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami-keypad-carrier.dts @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2025 Lukas Schmid + */ + +/dts-v1/; +#include "sun8i-t113s-netcube-nagami.dtsi" + +#include +#include + +/ { + model = "NetCube Systems Nagami Keypad Carrier Board"; + compatible = "netcube,nagami-keypad-carrier", "netcube,nagami", + "allwinner,sun8i-t113s"; + + leds { + compatible = "gpio-leds"; + + led_status_red: led-status-red { + gpios = <&pio 3 16 GPIO_ACTIVE_HIGH>; /* PD16 */ + color = ; + function = LED_FUNCTION_STATUS; + }; + + led_status_green: led-status-green { + gpios = <&pio 3 22 GPIO_ACTIVE_HIGH>; /* PD22 */ + color = ; + function = LED_FUNCTION_STATUS; + }; + }; +}; + +&i2c2 { + status = "okay"; + + tca8418: keypad@34 { + compatible = "ti,tca8418"; + reg = <0x34>; + interrupts-extended = <&pio 5 6 IRQ_TYPE_EDGE_FALLING>; /* PF6 */ + linux,keymap = ; + keypad,num-rows = <4>; + keypad,num-columns = <4>; + }; +}; + +&pio { + gpio-line-names = "", "", "", "", // PA + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", // PB + "", "", "UART3_TX", "UART3_RX", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "eMMC_CLK", "eMMC_CMD", // PC + "eMMC_D2", "eMMC_D1", "eMMC_D0", "eMMC_D3", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", // PD + "", "", "", "", + "", "USB_SEC_EN", "", "", + "", "", "", "", + "LED_STATUS_RED", "", "", "", + "I2C2_SCL", "I2C2_SDA", "LED_STATUS_GREEN", "", + "", "", "", "", + "", "", "", "", + "ETH_CRSDV", "ETH_RXD0", "ETH_RXD1", "ETH_TXCK", // PE + "ETH_TXD0", "ETH_TXD1", "ETH_TXEN", "", + "ETH_MDC", "ETH_MDIO", "QWIIC_nINT", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", // PF + "", "", "KEY_nINT", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "ESP_CLK", "ESP_CMD", "ESP_D0", "ESP_D1", // PG + "ESP_D2", "ESP_D3", "UART1_TXD", "UART1_RXD", + "ESP_nBOOT", "ESP_nRST", "I2C3_SCL", "I2C3_SDA", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&usb_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; From e6fad4960fc67b7225255b10b080765b451a7bc7 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sat, 13 Sep 2025 18:16:00 +0800 Subject: [PATCH 16/20] arm64: dts: sun55i: a523: Assign standard clock rates to PRCM bus clocks At least in the initial version of U-boot support landed upstream, the PRCM bus clocks were not configured, and left at their reset default 24 MHz clock rate. This is quite slow for the peripherals on them. The recommended rates from the manual are: - AHBS: 200 MHz - APBS0: 100 MHz - APBS1: 24 MHz Since 24 MHz is the hardware default, just assign rates for the first two. Reviewed-by: Jernej Skrabec Link: https://patch.msgid.link/20250913101600.3932762-1-wens@kernel.org Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi index d00da1cd744e..7b36c47a3a13 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -626,6 +626,8 @@ "pll-audio"; #clock-cells = <1>; #reset-cells = <1>; + assigned-clocks = <&r_ccu CLK_R_AHB>, <&r_ccu CLK_R_APB0>; + assigned-clock-rates = <200000000>, <100000000>; }; nmi_intc: interrupt-controller@7010320 { From 9f01e1e14e71defefcb4d6823b8476a15f3cf04a Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sat, 13 Sep 2025 18:24:48 +0800 Subject: [PATCH 17/20] arm64: dts: allwinner: a527: cubie-a5e: Drop external 32.768 KHz crystal The Radxa Cubie A5E has empty pads for a 32.768 KHz crystal, but it is left unpopulated, as per the schematics and seen on board images. A dead give away is the RTC's LOSC auto switch register showing the external OSC to be abnormal. Drop the external crystal from the device tree. It was not referenced anyway. Fixes: c2520cd032ae ("arm64: dts: allwinner: a523: add Radxa A5E support") Reviewed-by: Jernej Skrabec Link: https://patch.msgid.link/20250913102450.3935943-1-wens@kernel.org Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts | 7 ------- 1 file changed, 7 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts index d4cee2222104..514c221a7a86 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts @@ -21,13 +21,6 @@ stdout-path = "serial0:115200n8"; }; - ext_osc32k: ext-osc32k-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "ext_osc32k"; - }; - leds { compatible = "gpio-leds"; From 3d5e1ba00af8dd34ae1e573c2c07e00b5ec65267 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sat, 13 Sep 2025 18:24:49 +0800 Subject: [PATCH 18/20] arm64: dts: allwinner: t527: avaota-a1: hook up external 32k crystal When the board was added, its external 32.768 KHz crystal was described but not hooked up correctly. This meant the device had to fall back to the SoC's internal oscillator or divide a 32 KHz clock from the main oscillator, neither of which are accurate for the RTC. As a result the RTC clock will drift badly. Hook the crystal up to the RTC block and request the correct clock rate. Fixes: dbe54efa32af ("arm64: dts: allwinner: a523: add Avaota-A1 router support") Acked-by: Jernej Skrabec Link: https://patch.msgid.link/20250913102450.3935943-2-wens@kernel.org Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts index e7713678208d..4e71055fbd15 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts @@ -309,6 +309,14 @@ vcc-pm-supply = <®_aldo3>; }; +&rtc { + clocks = <&r_ccu CLK_BUS_R_RTC>, <&osc24M>, + <&r_ccu CLK_R_AHB>, <&ext_osc32k>; + clock-names = "bus", "hosc", "ahb", "ext-osc32k"; + assigned-clocks = <&rtc CLK_OSC32K>; + assigned-clock-rates = <32768>; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pb_pins>; From bd1ce7ef6aef4ee7349eb3124166e712693650ce Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sat, 13 Sep 2025 18:24:50 +0800 Subject: [PATCH 19/20] arm64: dts: allwinner: t527: orangepi-4a: hook up external 32k crystal When the board was added, its external 32.768 KHz crystal was described but not hooked up correctly. This meant the device had to fall back to the SoC's internal oscillator or divide a 32 KHz clock from the main oscillator, neither of which are accurate for the RTC. As a result the RTC clock will drift badly. Hook the crystal up to the RTC block and request the correct clock rate. Fixes: de713ccb9934 ("arm64: dts: allwinner: t527: Add OrangePi 4A board") Acked-by: Jernej Skrabec Link: https://patch.msgid.link/20250913102450.3935943-3-wens@kernel.org Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts index d07bb9193b43..b5483bd7b8d5 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts @@ -346,6 +346,14 @@ vcc-pm-supply = <®_bldo2>; }; +&rtc { + clocks = <&r_ccu CLK_BUS_R_RTC>, <&osc24M>, + <&r_ccu CLK_R_AHB>, <&ext_osc32k>; + clock-names = "bus", "hosc", "ahb", "ext-osc32k"; + assigned-clocks = <&rtc CLK_OSC32K>; + assigned-clock-rates = <32768>; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pb_pins>; From cca07ac2b5f7838b8ff612b53b9f82ac8cb58312 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sun, 14 Sep 2025 01:35:11 +0800 Subject: [PATCH 20/20] arm64: dts: allwinner: sun55i: Complete AXP717A sub-functions When the AXP717A PMIC is missing nodes for the sub-functions, the kernel complains about not found nodes. Add all the remaining nodes corresponding to the defined functions for the dev boards, which have publicly available schematics to base this change on. The battery charger on all of them are disabled. Also add an "iio-hwmon" node to express some of the ADC channels as hwmon sensors. Acked-by: Jernej Skrabec Link: https://patch.msgid.link/20250913173511.4064176-1-wens@kernel.org Signed-off-by: Chen-Yu Tsai --- .../dts/allwinner/sun55i-a527-cubie-a5e.dts | 21 +++++++++++++++++ .../dts/allwinner/sun55i-t527-avaota-a1.dts | 23 +++++++++++++++++++ .../dts/allwinner/sun55i-t527-orangepi-4a.dts | 23 +++++++++++++++++++ 3 files changed, 67 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts index 514c221a7a86..f82a8d121697 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts @@ -39,6 +39,12 @@ }; }; + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&axp717_adc 3>, /* vsys_v */ + <&axp717_adc 4>; /* pmic_temp */ + }; + reg_vcc5v: vcc5v { /* board wide 5V supply from the USB-C connector */ compatible = "regulator-fixed"; @@ -140,6 +146,17 @@ bldoin-supply = <®_vcc5v>; cldoin-supply = <®_vcc5v>; + axp717_adc: adc { + compatible = "x-powers,axp717-adc"; + #io-channel-cells = <1>; + }; + + battery-power { + compatible = "x-powers,axp717-battery-power-supply"; + /* charger mode design but has no battery terminal */ + status = "disabled"; + }; + regulators { /* Supplies the "little" cluster (1.4 GHz cores) */ reg_dcdc1: dcdc1 { @@ -243,6 +260,10 @@ regulator-name = "vdd-cpus"; }; }; + + usb-power { + compatible = "x-powers,axp717-usb-power-supply"; + }; }; axp323: pmic@36 { diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts index 4e71055fbd15..1b054fa8ef74 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts @@ -27,6 +27,12 @@ clock-output-names = "ext_osc32k"; }; + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&axp717_adc 3>, /* vsys_v */ + <&axp717_adc 4>; /* pmic_temp */ + }; + reg_vcc12v: vcc12v { /* DC input jack */ compatible = "regulator-fixed"; @@ -149,6 +155,17 @@ bldoin-supply = <®_vcc5v>; cldoin-supply = <®_vcc5v>; + axp717_adc: adc { + compatible = "x-powers,axp717-adc"; + #io-channel-cells = <1>; + }; + + battery-power { + compatible = "x-powers,axp717-battery-power-supply"; + /* no battery; output used for dcdc4 instead */ + status = "disabled"; + }; + regulators { /* Supplies the "little" cluster (1.4 GHz cores) */ reg_dcdc1: dcdc1 { @@ -255,6 +272,12 @@ regulator-name = "vdd-cpus"; }; }; + + usb-power { + compatible = "x-powers,axp717-usb-power-supply"; + /* 12V-5V buck converter can supply up to 5A */ + input-current-limit-microamp = <3250000>; + }; }; axp323: pmic@36 { diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts index b5483bd7b8d5..39a4e194712a 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts @@ -40,6 +40,13 @@ }; }; + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&axp717_adc 3>, /* vsys_v */ + <&axp717_adc 4>, /* pmic_temp */ + <&axp717_adc 7>; /* bkup_batt_v */ + }; + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 1 1 GPIO_ACTIVE_LOW>; /* PM1 */ @@ -174,6 +181,17 @@ bldoin-supply = <®_vcc5v>; cldoin-supply = <®_vcc5v>; + axp717_adc: adc { + compatible = "x-powers,axp717-adc"; + #io-channel-cells = <1>; + }; + + battery-power { + compatible = "x-powers,axp717-battery-power-supply"; + /* no battery; output used for dcdc4 instead */ + status = "disabled"; + }; + regulators { /* Supplies the "little" cluster (1.4 GHz cores) */ reg_dcdc1: dcdc1 { @@ -288,6 +306,11 @@ regulator-name = "vdd-cpus-usb-0v9"; }; }; + + usb-power { + compatible = "x-powers,axp717-usb-power-supply"; + input-current-limit-microamp = <3000000>; + }; }; axp323: pmic@36 {