wireless-next patches for v6.2

First set of patches v6.2. mac80211 refactoring continues for Wi-Fi 7.
 All mac80211 driver are now converted to use internal TX queues, this
 might cause some regressions so we wanted to do this early in the
 cycle.
 
 Note: wireless tree was merged[1] to wireless-next to avoid some
 conflicts with mac80211 patches between the trees. Unfortunately there
 are still two smaller conflicts in net/mac80211/util.c which Stephen
 also reported[2]. In the first conflict initialise scratch_len to
 "params->scratch_len ?: 3 * params->len" (note number 3, not 2!) and
 in the second conflict take the version which uses elems->scratch_pos.
 
 Git diff output should like this:
 
 --- a/net/mac80211/util.c
 +++ b/net/mac80211/util.c
 @@@ -1506,7 -1648,7 +1650,7 @@@ ieee802_11_parse_elems_full(struct ieee
         const struct element *non_inherit = NULL;
         u8 *nontransmitted_profile;
         int nontransmitted_profile_len = 0;
 -       size_t scratch_len = params->len;
  -      size_t scratch_len = params->scratch_len ?: 2 * params->len;
 ++      size_t scratch_len = params->scratch_len ?: 3 * params->len;
 
         elems = kzalloc(sizeof(*elems) + scratch_len, GFP_ATOMIC);
         if (!elems)
 
 [1] https://git.kernel.org/pub/scm/linux/kernel/git/wireless/wireless-next.git/commit/?id=dfd2d876b3fda1790bc0239ba4c6967e25d16e91
 [2] https://lore.kernel.org/all/20221020032340.5cf101c0@canb.auug.org.au/
 
 Major changes:
 
 mac80211
 
 * preparation for Wi-Fi 7 Multi-Link Operation (MLO) continues
 
 * add API to show the link STAs in debugfs
 
 * all mac80211 drivers are now using mac80211 internal TX queues (iTXQs)
 
 rtw89
 
 * support 8852BE
 
 rtl8xxxu
 
 * support RTL8188FU
 
 brmfmac
 
 * support two station interfaces concurrently
 
 bcma
 
 * support SPROM rev 11
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Kalle Valo says:

====================
pull-request: wireless-next-2022-10-28

First set of patches v6.2. mac80211 refactoring continues for Wi-Fi 7.
All mac80211 driver are now converted to use internal TX queues, this
might cause some regressions so we wanted to do this early in the
cycle.

Note: wireless tree was merged[1] to wireless-next to avoid some
conflicts with mac80211 patches between the trees. Unfortunately there
are still two smaller conflicts in net/mac80211/util.c which Stephen
also reported[2]. In the first conflict initialise scratch_len to
"params->scratch_len ?: 3 * params->len" (note number 3, not 2!) and
in the second conflict take the version which uses elems->scratch_pos.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/wireless/wireless-next.git/commit/?id=dfd2d876b3fda1790bc0239ba4c6967e25d16e91
[2] https://lore.kernel.org/all/20221020032340.5cf101c0@canb.auug.org.au/

mac80211
 - preparation for Wi-Fi 7 Multi-Link Operation (MLO) continues
 - add API to show the link STAs in debugfs
 - all mac80211 drivers are now using mac80211 internal TX queues (iTXQs)

rtw89
 - support 8852BE

rtl8xxxu
 - support RTL8188FU

brmfmac
 - support two station interfaces concurrently

bcma
 - support SPROM rev 11
====================

Link: https://lore.kernel.org/r/20221028132943.304ECC433B5@smtp.kernel.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski 2022-10-28 18:31:39 -07:00
commit 196dd92a00
122 changed files with 35580 additions and 1105 deletions

View File

@ -82,6 +82,7 @@ static void bcma_gpio_irq_unmask(struct irq_data *d)
int gpio = irqd_to_hwirq(d); int gpio = irqd_to_hwirq(d);
u32 val = bcma_chipco_gpio_in(cc, BIT(gpio)); u32 val = bcma_chipco_gpio_in(cc, BIT(gpio));
gpiochip_enable_irq(gc, gpio);
bcma_chipco_gpio_polarity(cc, BIT(gpio), val); bcma_chipco_gpio_polarity(cc, BIT(gpio), val);
bcma_chipco_gpio_intmask(cc, BIT(gpio), BIT(gpio)); bcma_chipco_gpio_intmask(cc, BIT(gpio), BIT(gpio));
} }
@ -93,12 +94,15 @@ static void bcma_gpio_irq_mask(struct irq_data *d)
int gpio = irqd_to_hwirq(d); int gpio = irqd_to_hwirq(d);
bcma_chipco_gpio_intmask(cc, BIT(gpio), 0); bcma_chipco_gpio_intmask(cc, BIT(gpio), 0);
gpiochip_disable_irq(gc, gpio);
} }
static struct irq_chip bcma_gpio_irq_chip = { static const struct irq_chip bcma_gpio_irq_chip = {
.name = "BCMA-GPIO", .name = "BCMA-GPIO",
.irq_mask = bcma_gpio_irq_mask, .irq_mask = bcma_gpio_irq_mask,
.irq_unmask = bcma_gpio_irq_unmask, .irq_unmask = bcma_gpio_irq_unmask,
.flags = IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
}; };
static irqreturn_t bcma_gpio_irq_handler(int irq, void *dev_id) static irqreturn_t bcma_gpio_irq_handler(int irq, void *dev_id)
@ -139,7 +143,7 @@ static int bcma_gpio_irq_init(struct bcma_drv_cc *cc)
bcma_chipco_gpio_intmask(cc, ~0, 0); bcma_chipco_gpio_intmask(cc, ~0, 0);
bcma_cc_set32(cc, BCMA_CC_IRQMASK, BCMA_CC_IRQ_GPIO); bcma_cc_set32(cc, BCMA_CC_IRQMASK, BCMA_CC_IRQ_GPIO);
girq->chip = &bcma_gpio_irq_chip; gpio_irq_chip_set_chip(girq, &bcma_gpio_irq_chip);
/* This will let us handle the parent IRQ in the driver */ /* This will let us handle the parent IRQ in the driver */
girq->parent_handler = NULL; girq->parent_handler = NULL;
girq->num_parents = 0; girq->num_parents = 0;

View File

@ -165,7 +165,7 @@ static int bcma_sprom_valid(struct bcma_bus *bus, const u16 *sprom,
return err; return err;
revision = sprom[words - 1] & SSB_SPROM_REVISION_REV; revision = sprom[words - 1] & SSB_SPROM_REVISION_REV;
if (revision != 8 && revision != 9 && revision != 10) { if (revision < 8 || revision > 11) {
pr_err("Unsupported SPROM revision: %d\n", revision); pr_err("Unsupported SPROM revision: %d\n", revision);
return -ENOENT; return -ENOENT;
} }

View File

@ -1760,6 +1760,7 @@ static int adm8211_alloc_rings(struct ieee80211_hw *dev)
static const struct ieee80211_ops adm8211_ops = { static const struct ieee80211_ops adm8211_ops = {
.tx = adm8211_tx, .tx = adm8211_tx,
.wake_tx_queue = ieee80211_handle_wake_tx_queue,
.start = adm8211_start, .start = adm8211_start,
.stop = adm8211_stop, .stop = adm8211_stop,
.add_interface = adm8211_add_interface, .add_interface = adm8211_add_interface,

View File

@ -1355,6 +1355,7 @@ static const struct ieee80211_ops ar5523_ops = {
.start = ar5523_start, .start = ar5523_start,
.stop = ar5523_stop, .stop = ar5523_stop,
.tx = ar5523_tx, .tx = ar5523_tx,
.wake_tx_queue = ieee80211_handle_wake_tx_queue,
.set_rts_threshold = ar5523_set_rts_threshold, .set_rts_threshold = ar5523_set_rts_threshold,
.add_interface = ar5523_add_interface, .add_interface = ar5523_add_interface,
.remove_interface = ar5523_remove_interface, .remove_interface = ar5523_remove_interface,

View File

@ -8539,6 +8539,7 @@ err_fallback:
static const struct ieee80211_ops ath11k_ops = { static const struct ieee80211_ops ath11k_ops = {
.tx = ath11k_mac_op_tx, .tx = ath11k_mac_op_tx,
.wake_tx_queue = ieee80211_handle_wake_tx_queue,
.start = ath11k_mac_op_start, .start = ath11k_mac_op_start,
.stop = ath11k_mac_op_stop, .stop = ath11k_mac_op_stop,
.reconfig_complete = ath11k_mac_op_reconfig_complete, .reconfig_complete = ath11k_mac_op_reconfig_complete,

View File

@ -781,6 +781,7 @@ static int ath5k_set_ringparam(struct ieee80211_hw *hw, u32 tx, u32 rx)
const struct ieee80211_ops ath5k_hw_ops = { const struct ieee80211_ops ath5k_hw_ops = {
.tx = ath5k_tx, .tx = ath5k_tx,
.wake_tx_queue = ieee80211_handle_wake_tx_queue,
.start = ath5k_start, .start = ath5k_start,
.stop = ath5k_stop, .stop = ath5k_stop,
.add_interface = ath5k_add_interface, .add_interface = ath5k_add_interface,

View File

@ -1870,6 +1870,7 @@ static void ath9k_htc_channel_switch_beacon(struct ieee80211_hw *hw,
struct ieee80211_ops ath9k_htc_ops = { struct ieee80211_ops ath9k_htc_ops = {
.tx = ath9k_htc_tx, .tx = ath9k_htc_tx,
.wake_tx_queue = ieee80211_handle_wake_tx_queue,
.start = ath9k_htc_start, .start = ath9k_htc_start,
.stop = ath9k_htc_stop, .stop = ath9k_htc_stop,
.add_interface = ath9k_htc_add_interface, .add_interface = ath9k_htc_add_interface,

View File

@ -1715,6 +1715,7 @@ static const struct ieee80211_ops carl9170_ops = {
.start = carl9170_op_start, .start = carl9170_op_start,
.stop = carl9170_op_stop, .stop = carl9170_op_stop,
.tx = carl9170_op_tx, .tx = carl9170_op_tx,
.wake_tx_queue = ieee80211_handle_wake_tx_queue,
.flush = carl9170_op_flush, .flush = carl9170_op_flush,
.add_interface = carl9170_op_add_interface, .add_interface = carl9170_op_add_interface,
.remove_interface = carl9170_op_remove_interface, .remove_interface = carl9170_op_remove_interface,

View File

@ -1361,6 +1361,7 @@ static const struct ieee80211_ops wcn36xx_ops = {
.prepare_multicast = wcn36xx_prepare_multicast, .prepare_multicast = wcn36xx_prepare_multicast,
.configure_filter = wcn36xx_configure_filter, .configure_filter = wcn36xx_configure_filter,
.tx = wcn36xx_tx, .tx = wcn36xx_tx,
.wake_tx_queue = ieee80211_handle_wake_tx_queue,
.set_key = wcn36xx_set_key, .set_key = wcn36xx_set_key,
.hw_scan = wcn36xx_hw_scan, .hw_scan = wcn36xx_hw_scan,
.cancel_hw_scan = wcn36xx_cancel_hw_scan, .cancel_hw_scan = wcn36xx_cancel_hw_scan,

View File

@ -2179,6 +2179,7 @@ static int at76_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
static const struct ieee80211_ops at76_ops = { static const struct ieee80211_ops at76_ops = {
.tx = at76_mac80211_tx, .tx = at76_mac80211_tx,
.wake_tx_queue = ieee80211_handle_wake_tx_queue,
.add_interface = at76_add_interface, .add_interface = at76_add_interface,
.remove_interface = at76_remove_interface, .remove_interface = at76_remove_interface,
.config = at76_config, .config = at76_config,

View File

@ -1643,9 +1643,10 @@ EXPORT_SYMBOL(stop_atmel_card);
static int atmel_set_essid(struct net_device *dev, static int atmel_set_essid(struct net_device *dev,
struct iw_request_info *info, struct iw_request_info *info,
struct iw_point *dwrq, union iwreq_data *wrqu,
char *extra) char *extra)
{ {
struct iw_point *dwrq = &wrqu->essid;
struct atmel_private *priv = netdev_priv(dev); struct atmel_private *priv = netdev_priv(dev);
/* Check if we asked for `any' */ /* Check if we asked for `any' */
@ -1671,9 +1672,10 @@ static int atmel_set_essid(struct net_device *dev,
static int atmel_get_essid(struct net_device *dev, static int atmel_get_essid(struct net_device *dev,
struct iw_request_info *info, struct iw_request_info *info,
struct iw_point *dwrq, union iwreq_data *wrqu,
char *extra) char *extra)
{ {
struct iw_point *dwrq = &wrqu->essid;
struct atmel_private *priv = netdev_priv(dev); struct atmel_private *priv = netdev_priv(dev);
/* Get the current SSID */ /* Get the current SSID */
@ -1692,9 +1694,10 @@ static int atmel_get_essid(struct net_device *dev,
static int atmel_get_wap(struct net_device *dev, static int atmel_get_wap(struct net_device *dev,
struct iw_request_info *info, struct iw_request_info *info,
struct sockaddr *awrq, union iwreq_data *wrqu,
char *extra) char *extra)
{ {
struct sockaddr *awrq = &wrqu->ap_addr;
struct atmel_private *priv = netdev_priv(dev); struct atmel_private *priv = netdev_priv(dev);
memcpy(awrq->sa_data, priv->CurrentBSSID, ETH_ALEN); memcpy(awrq->sa_data, priv->CurrentBSSID, ETH_ALEN);
awrq->sa_family = ARPHRD_ETHER; awrq->sa_family = ARPHRD_ETHER;
@ -1704,9 +1707,10 @@ static int atmel_get_wap(struct net_device *dev,
static int atmel_set_encode(struct net_device *dev, static int atmel_set_encode(struct net_device *dev,
struct iw_request_info *info, struct iw_request_info *info,
struct iw_point *dwrq, union iwreq_data *wrqu,
char *extra) char *extra)
{ {
struct iw_point *dwrq = &wrqu->encoding;
struct atmel_private *priv = netdev_priv(dev); struct atmel_private *priv = netdev_priv(dev);
/* Basic checking: do we have a key to set ? /* Basic checking: do we have a key to set ?
@ -1793,9 +1797,10 @@ static int atmel_set_encode(struct net_device *dev,
static int atmel_get_encode(struct net_device *dev, static int atmel_get_encode(struct net_device *dev,
struct iw_request_info *info, struct iw_request_info *info,
struct iw_point *dwrq, union iwreq_data *wrqu,
char *extra) char *extra)
{ {
struct iw_point *dwrq = &wrqu->encoding;
struct atmel_private *priv = netdev_priv(dev); struct atmel_private *priv = netdev_priv(dev);
int index = (dwrq->flags & IW_ENCODE_INDEX) - 1; int index = (dwrq->flags & IW_ENCODE_INDEX) - 1;
@ -2003,18 +2008,19 @@ static int atmel_get_auth(struct net_device *dev,
static int atmel_get_name(struct net_device *dev, static int atmel_get_name(struct net_device *dev,
struct iw_request_info *info, struct iw_request_info *info,
char *cwrq, union iwreq_data *wrqu,
char *extra) char *extra)
{ {
strcpy(cwrq, "IEEE 802.11-DS"); strcpy(wrqu->name, "IEEE 802.11-DS");
return 0; return 0;
} }
static int atmel_set_rate(struct net_device *dev, static int atmel_set_rate(struct net_device *dev,
struct iw_request_info *info, struct iw_request_info *info,
struct iw_param *vwrq, union iwreq_data *wrqu,
char *extra) char *extra)
{ {
struct iw_param *vwrq = &wrqu->bitrate;
struct atmel_private *priv = netdev_priv(dev); struct atmel_private *priv = netdev_priv(dev);
if (vwrq->fixed == 0) { if (vwrq->fixed == 0) {
@ -2053,9 +2059,10 @@ static int atmel_set_rate(struct net_device *dev,
static int atmel_set_mode(struct net_device *dev, static int atmel_set_mode(struct net_device *dev,
struct iw_request_info *info, struct iw_request_info *info,
__u32 *uwrq, union iwreq_data *wrqu,
char *extra) char *extra)
{ {
__u32 *uwrq = &wrqu->mode;
struct atmel_private *priv = netdev_priv(dev); struct atmel_private *priv = netdev_priv(dev);
if (*uwrq != IW_MODE_ADHOC && *uwrq != IW_MODE_INFRA) if (*uwrq != IW_MODE_ADHOC && *uwrq != IW_MODE_INFRA)
@ -2067,9 +2074,10 @@ static int atmel_set_mode(struct net_device *dev,
static int atmel_get_mode(struct net_device *dev, static int atmel_get_mode(struct net_device *dev,
struct iw_request_info *info, struct iw_request_info *info,
__u32 *uwrq, union iwreq_data *wrqu,
char *extra) char *extra)
{ {
__u32 *uwrq = &wrqu->mode;
struct atmel_private *priv = netdev_priv(dev); struct atmel_private *priv = netdev_priv(dev);
*uwrq = priv->operating_mode; *uwrq = priv->operating_mode;
@ -2078,9 +2086,10 @@ static int atmel_get_mode(struct net_device *dev,
static int atmel_get_rate(struct net_device *dev, static int atmel_get_rate(struct net_device *dev,
struct iw_request_info *info, struct iw_request_info *info,
struct iw_param *vwrq, union iwreq_data *wrqu,
char *extra) char *extra)
{ {
struct iw_param *vwrq = &wrqu->bitrate;
struct atmel_private *priv = netdev_priv(dev); struct atmel_private *priv = netdev_priv(dev);
if (priv->auto_tx_rate) { if (priv->auto_tx_rate) {
@ -2108,9 +2117,10 @@ static int atmel_get_rate(struct net_device *dev,
static int atmel_set_power(struct net_device *dev, static int atmel_set_power(struct net_device *dev,
struct iw_request_info *info, struct iw_request_info *info,
struct iw_param *vwrq, union iwreq_data *wrqu,
char *extra) char *extra)
{ {
struct iw_param *vwrq = &wrqu->power;
struct atmel_private *priv = netdev_priv(dev); struct atmel_private *priv = netdev_priv(dev);
priv->power_mode = vwrq->disabled ? 0 : 1; priv->power_mode = vwrq->disabled ? 0 : 1;
return -EINPROGRESS; return -EINPROGRESS;
@ -2118,9 +2128,10 @@ static int atmel_set_power(struct net_device *dev,
static int atmel_get_power(struct net_device *dev, static int atmel_get_power(struct net_device *dev,
struct iw_request_info *info, struct iw_request_info *info,
struct iw_param *vwrq, union iwreq_data *wrqu,
char *extra) char *extra)
{ {
struct iw_param *vwrq = &wrqu->power;
struct atmel_private *priv = netdev_priv(dev); struct atmel_private *priv = netdev_priv(dev);
vwrq->disabled = priv->power_mode ? 0 : 1; vwrq->disabled = priv->power_mode ? 0 : 1;
vwrq->flags = IW_POWER_ON; vwrq->flags = IW_POWER_ON;
@ -2129,9 +2140,10 @@ static int atmel_get_power(struct net_device *dev,
static int atmel_set_retry(struct net_device *dev, static int atmel_set_retry(struct net_device *dev,
struct iw_request_info *info, struct iw_request_info *info,
struct iw_param *vwrq, union iwreq_data *wrqu,
char *extra) char *extra)
{ {
struct iw_param *vwrq = &wrqu->retry;
struct atmel_private *priv = netdev_priv(dev); struct atmel_private *priv = netdev_priv(dev);
if (!vwrq->disabled && (vwrq->flags & IW_RETRY_LIMIT)) { if (!vwrq->disabled && (vwrq->flags & IW_RETRY_LIMIT)) {
@ -2152,9 +2164,10 @@ static int atmel_set_retry(struct net_device *dev,
static int atmel_get_retry(struct net_device *dev, static int atmel_get_retry(struct net_device *dev,
struct iw_request_info *info, struct iw_request_info *info,
struct iw_param *vwrq, union iwreq_data *wrqu,
char *extra) char *extra)
{ {
struct iw_param *vwrq = &wrqu->retry;
struct atmel_private *priv = netdev_priv(dev); struct atmel_private *priv = netdev_priv(dev);
vwrq->disabled = 0; /* Can't be disabled */ vwrq->disabled = 0; /* Can't be disabled */
@ -2175,9 +2188,10 @@ static int atmel_get_retry(struct net_device *dev,
static int atmel_set_rts(struct net_device *dev, static int atmel_set_rts(struct net_device *dev,
struct iw_request_info *info, struct iw_request_info *info,
struct iw_param *vwrq, union iwreq_data *wrqu,
char *extra) char *extra)
{ {
struct iw_param *vwrq = &wrqu->rts;
struct atmel_private *priv = netdev_priv(dev); struct atmel_private *priv = netdev_priv(dev);
int rthr = vwrq->value; int rthr = vwrq->value;
@ -2193,9 +2207,10 @@ static int atmel_set_rts(struct net_device *dev,
static int atmel_get_rts(struct net_device *dev, static int atmel_get_rts(struct net_device *dev,
struct iw_request_info *info, struct iw_request_info *info,
struct iw_param *vwrq, union iwreq_data *wrqu,
char *extra) char *extra)
{ {
struct iw_param *vwrq = &wrqu->rts;
struct atmel_private *priv = netdev_priv(dev); struct atmel_private *priv = netdev_priv(dev);
vwrq->value = priv->rts_threshold; vwrq->value = priv->rts_threshold;
@ -2207,9 +2222,10 @@ static int atmel_get_rts(struct net_device *dev,
static int atmel_set_frag(struct net_device *dev, static int atmel_set_frag(struct net_device *dev,
struct iw_request_info *info, struct iw_request_info *info,
struct iw_param *vwrq, union iwreq_data *wrqu,
char *extra) char *extra)
{ {
struct iw_param *vwrq = &wrqu->frag;
struct atmel_private *priv = netdev_priv(dev); struct atmel_private *priv = netdev_priv(dev);
int fthr = vwrq->value; int fthr = vwrq->value;
@ -2226,9 +2242,10 @@ static int atmel_set_frag(struct net_device *dev,
static int atmel_get_frag(struct net_device *dev, static int atmel_get_frag(struct net_device *dev,
struct iw_request_info *info, struct iw_request_info *info,
struct iw_param *vwrq, union iwreq_data *wrqu,
char *extra) char *extra)
{ {
struct iw_param *vwrq = &wrqu->frag;
struct atmel_private *priv = netdev_priv(dev); struct atmel_private *priv = netdev_priv(dev);
vwrq->value = priv->frag_threshold; vwrq->value = priv->frag_threshold;
@ -2240,9 +2257,10 @@ static int atmel_get_frag(struct net_device *dev,
static int atmel_set_freq(struct net_device *dev, static int atmel_set_freq(struct net_device *dev,
struct iw_request_info *info, struct iw_request_info *info,
struct iw_freq *fwrq, union iwreq_data *wrqu,
char *extra) char *extra)
{ {
struct iw_freq *fwrq = &wrqu->freq;
struct atmel_private *priv = netdev_priv(dev); struct atmel_private *priv = netdev_priv(dev);
int rc = -EINPROGRESS; /* Call commit handler */ int rc = -EINPROGRESS; /* Call commit handler */
@ -2270,9 +2288,10 @@ static int atmel_set_freq(struct net_device *dev,
static int atmel_get_freq(struct net_device *dev, static int atmel_get_freq(struct net_device *dev,
struct iw_request_info *info, struct iw_request_info *info,
struct iw_freq *fwrq, union iwreq_data *wrqu,
char *extra) char *extra)
{ {
struct iw_freq *fwrq = &wrqu->freq;
struct atmel_private *priv = netdev_priv(dev); struct atmel_private *priv = netdev_priv(dev);
fwrq->m = priv->channel; fwrq->m = priv->channel;
@ -2282,7 +2301,7 @@ static int atmel_get_freq(struct net_device *dev,
static int atmel_set_scan(struct net_device *dev, static int atmel_set_scan(struct net_device *dev,
struct iw_request_info *info, struct iw_request_info *info,
struct iw_point *dwrq, union iwreq_data *dwrq,
char *extra) char *extra)
{ {
struct atmel_private *priv = netdev_priv(dev); struct atmel_private *priv = netdev_priv(dev);
@ -2320,9 +2339,10 @@ static int atmel_set_scan(struct net_device *dev,
static int atmel_get_scan(struct net_device *dev, static int atmel_get_scan(struct net_device *dev,
struct iw_request_info *info, struct iw_request_info *info,
struct iw_point *dwrq, union iwreq_data *wrqu,
char *extra) char *extra)
{ {
struct iw_point *dwrq = &wrqu->data;
struct atmel_private *priv = netdev_priv(dev); struct atmel_private *priv = netdev_priv(dev);
int i; int i;
char *current_ev = extra; char *current_ev = extra;
@ -2391,9 +2411,10 @@ static int atmel_get_scan(struct net_device *dev,
static int atmel_get_range(struct net_device *dev, static int atmel_get_range(struct net_device *dev,
struct iw_request_info *info, struct iw_request_info *info,
struct iw_point *dwrq, union iwreq_data *wrqu,
char *extra) char *extra)
{ {
struct iw_point *dwrq = &wrqu->data;
struct atmel_private *priv = netdev_priv(dev); struct atmel_private *priv = netdev_priv(dev);
struct iw_range *range = (struct iw_range *) extra; struct iw_range *range = (struct iw_range *) extra;
int k, i, j; int k, i, j;
@ -2465,9 +2486,10 @@ static int atmel_get_range(struct net_device *dev,
static int atmel_set_wap(struct net_device *dev, static int atmel_set_wap(struct net_device *dev,
struct iw_request_info *info, struct iw_request_info *info,
struct sockaddr *awrq, union iwreq_data *wrqu,
char *extra) char *extra)
{ {
struct sockaddr *awrq = &wrqu->ap_addr;
struct atmel_private *priv = netdev_priv(dev); struct atmel_private *priv = netdev_priv(dev);
int i; int i;
static const u8 any[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; static const u8 any[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
@ -2507,7 +2529,7 @@ static int atmel_set_wap(struct net_device *dev,
static int atmel_config_commit(struct net_device *dev, static int atmel_config_commit(struct net_device *dev,
struct iw_request_info *info, /* NULL */ struct iw_request_info *info, /* NULL */
void *zwrq, /* NULL */ union iwreq_data *zwrq, /* NULL */
char *extra) /* NULL */ char *extra) /* NULL */
{ {
return atmel_open(dev); return atmel_open(dev);
@ -2515,66 +2537,40 @@ static int atmel_config_commit(struct net_device *dev,
static const iw_handler atmel_handler[] = static const iw_handler atmel_handler[] =
{ {
(iw_handler) atmel_config_commit, /* SIOCSIWCOMMIT */ IW_HANDLER(SIOCSIWCOMMIT, atmel_config_commit),
(iw_handler) atmel_get_name, /* SIOCGIWNAME */ IW_HANDLER(SIOCGIWNAME, atmel_get_name),
(iw_handler) NULL, /* SIOCSIWNWID */ IW_HANDLER(SIOCSIWFREQ, atmel_set_freq),
(iw_handler) NULL, /* SIOCGIWNWID */ IW_HANDLER(SIOCGIWFREQ, atmel_get_freq),
(iw_handler) atmel_set_freq, /* SIOCSIWFREQ */ IW_HANDLER(SIOCSIWMODE, atmel_set_mode),
(iw_handler) atmel_get_freq, /* SIOCGIWFREQ */ IW_HANDLER(SIOCGIWMODE, atmel_get_mode),
(iw_handler) atmel_set_mode, /* SIOCSIWMODE */ IW_HANDLER(SIOCGIWRANGE, atmel_get_range),
(iw_handler) atmel_get_mode, /* SIOCGIWMODE */ IW_HANDLER(SIOCSIWAP, atmel_set_wap),
(iw_handler) NULL, /* SIOCSIWSENS */ IW_HANDLER(SIOCGIWAP, atmel_get_wap),
(iw_handler) NULL, /* SIOCGIWSENS */ IW_HANDLER(SIOCSIWSCAN, atmel_set_scan),
(iw_handler) NULL, /* SIOCSIWRANGE */ IW_HANDLER(SIOCGIWSCAN, atmel_get_scan),
(iw_handler) atmel_get_range, /* SIOCGIWRANGE */ IW_HANDLER(SIOCSIWESSID, atmel_set_essid),
(iw_handler) NULL, /* SIOCSIWPRIV */ IW_HANDLER(SIOCGIWESSID, atmel_get_essid),
(iw_handler) NULL, /* SIOCGIWPRIV */ IW_HANDLER(SIOCSIWRATE, atmel_set_rate),
(iw_handler) NULL, /* SIOCSIWSTATS */ IW_HANDLER(SIOCGIWRATE, atmel_get_rate),
(iw_handler) NULL, /* SIOCGIWSTATS */ IW_HANDLER(SIOCSIWRTS, atmel_set_rts),
(iw_handler) NULL, /* SIOCSIWSPY */ IW_HANDLER(SIOCGIWRTS, atmel_get_rts),
(iw_handler) NULL, /* SIOCGIWSPY */ IW_HANDLER(SIOCSIWFRAG, atmel_set_frag),
(iw_handler) NULL, /* -- hole -- */ IW_HANDLER(SIOCGIWFRAG, atmel_get_frag),
(iw_handler) NULL, /* -- hole -- */ IW_HANDLER(SIOCSIWRETRY, atmel_set_retry),
(iw_handler) atmel_set_wap, /* SIOCSIWAP */ IW_HANDLER(SIOCGIWRETRY, atmel_get_retry),
(iw_handler) atmel_get_wap, /* SIOCGIWAP */ IW_HANDLER(SIOCSIWENCODE, atmel_set_encode),
(iw_handler) NULL, /* -- hole -- */ IW_HANDLER(SIOCGIWENCODE, atmel_get_encode),
(iw_handler) NULL, /* SIOCGIWAPLIST */ IW_HANDLER(SIOCSIWPOWER, atmel_set_power),
(iw_handler) atmel_set_scan, /* SIOCSIWSCAN */ IW_HANDLER(SIOCGIWPOWER, atmel_get_power),
(iw_handler) atmel_get_scan, /* SIOCGIWSCAN */ IW_HANDLER(SIOCSIWAUTH, atmel_set_auth),
(iw_handler) atmel_set_essid, /* SIOCSIWESSID */ IW_HANDLER(SIOCGIWAUTH, atmel_get_auth),
(iw_handler) atmel_get_essid, /* SIOCGIWESSID */ IW_HANDLER(SIOCSIWENCODEEXT, atmel_set_encodeext),
(iw_handler) NULL, /* SIOCSIWNICKN */ IW_HANDLER(SIOCGIWENCODEEXT, atmel_get_encodeext),
(iw_handler) NULL, /* SIOCGIWNICKN */
(iw_handler) NULL, /* -- hole -- */
(iw_handler) NULL, /* -- hole -- */
(iw_handler) atmel_set_rate, /* SIOCSIWRATE */
(iw_handler) atmel_get_rate, /* SIOCGIWRATE */
(iw_handler) atmel_set_rts, /* SIOCSIWRTS */
(iw_handler) atmel_get_rts, /* SIOCGIWRTS */
(iw_handler) atmel_set_frag, /* SIOCSIWFRAG */
(iw_handler) atmel_get_frag, /* SIOCGIWFRAG */
(iw_handler) NULL, /* SIOCSIWTXPOW */
(iw_handler) NULL, /* SIOCGIWTXPOW */
(iw_handler) atmel_set_retry, /* SIOCSIWRETRY */
(iw_handler) atmel_get_retry, /* SIOCGIWRETRY */
(iw_handler) atmel_set_encode, /* SIOCSIWENCODE */
(iw_handler) atmel_get_encode, /* SIOCGIWENCODE */
(iw_handler) atmel_set_power, /* SIOCSIWPOWER */
(iw_handler) atmel_get_power, /* SIOCGIWPOWER */
(iw_handler) NULL, /* -- hole -- */
(iw_handler) NULL, /* -- hole -- */
(iw_handler) NULL, /* SIOCSIWGENIE */
(iw_handler) NULL, /* SIOCGIWGENIE */
(iw_handler) atmel_set_auth, /* SIOCSIWAUTH */
(iw_handler) atmel_get_auth, /* SIOCGIWAUTH */
(iw_handler) atmel_set_encodeext, /* SIOCSIWENCODEEXT */
(iw_handler) atmel_get_encodeext, /* SIOCGIWENCODEEXT */
(iw_handler) NULL, /* SIOCSIWPMKSA */
}; };
static const iw_handler atmel_private_handler[] = static const iw_handler atmel_private_handler[] =
{ {
NULL, /* SIOCIWFIRSTPRIV */ IW_HANDLER(SIOCIWFIRSTPRIV, NULL),
}; };
struct atmel_priv_ioctl { struct atmel_priv_ioctl {
@ -2614,8 +2610,8 @@ static const struct iw_handler_def atmel_handler_def = {
.num_standard = ARRAY_SIZE(atmel_handler), .num_standard = ARRAY_SIZE(atmel_handler),
.num_private = ARRAY_SIZE(atmel_private_handler), .num_private = ARRAY_SIZE(atmel_private_handler),
.num_private_args = ARRAY_SIZE(atmel_private_args), .num_private_args = ARRAY_SIZE(atmel_private_args),
.standard = (iw_handler *) atmel_handler, .standard = atmel_handler,
.private = (iw_handler *) atmel_private_handler, .private = atmel_private_handler,
.private_args = (struct iw_priv_args *) atmel_private_args, .private_args = (struct iw_priv_args *) atmel_private_args,
.get_wireless_stats = atmel_get_wireless_stats .get_wireless_stats = atmel_get_wireless_stats
}; };

View File

@ -5171,6 +5171,7 @@ static int b43_op_get_survey(struct ieee80211_hw *hw, int idx,
static const struct ieee80211_ops b43_hw_ops = { static const struct ieee80211_ops b43_hw_ops = {
.tx = b43_op_tx, .tx = b43_op_tx,
.wake_tx_queue = ieee80211_handle_wake_tx_queue,
.conf_tx = b43_op_conf_tx, .conf_tx = b43_op_conf_tx,
.add_interface = b43_op_add_interface, .add_interface = b43_op_add_interface,
.remove_interface = b43_op_remove_interface, .remove_interface = b43_op_remove_interface,

View File

@ -3532,6 +3532,7 @@ static int b43legacy_op_get_survey(struct ieee80211_hw *hw, int idx,
static const struct ieee80211_ops b43legacy_hw_ops = { static const struct ieee80211_ops b43legacy_hw_ops = {
.tx = b43legacy_op_tx, .tx = b43legacy_op_tx,
.wake_tx_queue = ieee80211_handle_wake_tx_queue,
.conf_tx = b43legacy_op_conf_tx, .conf_tx = b43legacy_op_conf_tx,
.add_interface = b43legacy_op_add_interface, .add_interface = b43legacy_op_add_interface,
.remove_interface = b43legacy_op_remove_interface, .remove_interface = b43legacy_op_remove_interface,

View File

@ -24,6 +24,12 @@
#define BRCMF_NROF_COMMON_MSGRINGS (BRCMF_NROF_H2D_COMMON_MSGRINGS + \ #define BRCMF_NROF_COMMON_MSGRINGS (BRCMF_NROF_H2D_COMMON_MSGRINGS + \
BRCMF_NROF_D2H_COMMON_MSGRINGS) BRCMF_NROF_D2H_COMMON_MSGRINGS)
/* The interval to poll console */
#define BRCMF_CONSOLE 10
/* The maximum console interval value (5 mins) */
#define MAX_CONSOLE_INTERVAL (5 * 60)
/* The level of bus communication with the dongle */ /* The level of bus communication with the dongle */
enum brcmf_bus_state { enum brcmf_bus_state {
BRCMF_BUS_DOWN, /* Not ready for frame transfers */ BRCMF_BUS_DOWN, /* Not ready for frame transfers */

View File

@ -88,9 +88,39 @@
#define BRCMF_PS_MAX_TIMEOUT_MS 2000 #define BRCMF_PS_MAX_TIMEOUT_MS 2000
/* Dump obss definitions */
#define ACS_MSRMNT_DELAY 80
#define CHAN_NOISE_DUMMY (-80)
#define OBSS_TOKEN_IDX 15
#define IBSS_TOKEN_IDX 15
#define TX_TOKEN_IDX 14
#define CTG_TOKEN_IDX 13
#define PKT_TOKEN_IDX 15
#define IDLE_TOKEN_IDX 12
#define BRCMF_ASSOC_PARAMS_FIXED_SIZE \ #define BRCMF_ASSOC_PARAMS_FIXED_SIZE \
(sizeof(struct brcmf_assoc_params_le) - sizeof(u16)) (sizeof(struct brcmf_assoc_params_le) - sizeof(u16))
struct brcmf_dump_survey {
u32 obss;
u32 ibss;
u32 no_ctg;
u32 no_pckt;
u32 tx;
u32 idle;
};
struct cca_stats_n_flags {
u32 msrmnt_time; /* Time for Measurement (msec) */
u32 msrmnt_done; /* flag set when measurement complete */
char buf[1];
};
struct cca_msrmnt_query {
u32 msrmnt_query;
u32 time_req;
};
static bool check_vif_up(struct brcmf_cfg80211_vif *vif) static bool check_vif_up(struct brcmf_cfg80211_vif *vif)
{ {
if (!test_bit(BRCMF_VIF_STATUS_READY, &vif->sme_state)) { if (!test_bit(BRCMF_VIF_STATUS_READY, &vif->sme_state)) {
@ -234,6 +264,48 @@ struct parsed_vndr_ies {
struct parsed_vndr_ie_info ie_info[VNDR_IE_PARSE_LIMIT]; struct parsed_vndr_ie_info ie_info[VNDR_IE_PARSE_LIMIT];
}; };
#define WL_INTERFACE_CREATE_VER_1 1
#define WL_INTERFACE_CREATE_VER_2 2
#define WL_INTERFACE_CREATE_VER_3 3
#define WL_INTERFACE_CREATE_VER_MAX WL_INTERFACE_CREATE_VER_3
#define WL_INTERFACE_MAC_DONT_USE 0x0
#define WL_INTERFACE_MAC_USE 0x2
#define WL_INTERFACE_CREATE_STA 0x0
#define WL_INTERFACE_CREATE_AP 0x1
struct wl_interface_create_v1 {
u16 ver; /* structure version */
u32 flags; /* flags for operation */
u8 mac_addr[ETH_ALEN]; /* MAC address */
u32 wlc_index; /* optional for wlc index */
};
struct wl_interface_create_v2 {
u16 ver; /* structure version */
u8 pad1[2];
u32 flags; /* flags for operation */
u8 mac_addr[ETH_ALEN]; /* MAC address */
u8 iftype; /* type of interface created */
u8 pad2;
u32 wlc_index; /* optional for wlc index */
};
struct wl_interface_create_v3 {
u16 ver; /* structure version */
u16 len; /* length of structure + data */
u16 fixed_len; /* length of structure */
u8 iftype; /* type of interface created */
u8 wlc_index; /* optional for wlc index */
u32 flags; /* flags for operation */
u8 mac_addr[ETH_ALEN]; /* MAC address */
u8 bssid[ETH_ALEN]; /* optional for BSSID */
u8 if_index; /* interface index request */
u8 pad[3];
u8 data[]; /* Optional for specific data */
};
static u8 nl80211_band_to_fwil(enum nl80211_band band) static u8 nl80211_band_to_fwil(enum nl80211_band band)
{ {
switch (band) { switch (band) {
@ -521,40 +593,228 @@ static int brcmf_get_first_free_bsscfgidx(struct brcmf_pub *drvr)
return -ENOMEM; return -ENOMEM;
} }
static void brcmf_set_vif_sta_macaddr(struct brcmf_if *ifp, u8 *mac_addr)
{
u8 mac_idx = ifp->drvr->sta_mac_idx;
/* set difference MAC address with locally administered bit */
memcpy(mac_addr, ifp->mac_addr, ETH_ALEN);
mac_addr[0] |= 0x02;
mac_addr[3] ^= mac_idx ? 0xC0 : 0xA0;
mac_idx++;
mac_idx = mac_idx % 2;
ifp->drvr->sta_mac_idx = mac_idx;
}
static int brcmf_cfg80211_request_sta_if(struct brcmf_if *ifp, u8 *macaddr)
{
struct wl_interface_create_v1 iface_v1;
struct wl_interface_create_v2 iface_v2;
struct wl_interface_create_v3 iface_v3;
u32 iface_create_ver;
int err;
/* interface_create version 1 */
memset(&iface_v1, 0, sizeof(iface_v1));
iface_v1.ver = WL_INTERFACE_CREATE_VER_1;
iface_v1.flags = WL_INTERFACE_CREATE_STA |
WL_INTERFACE_MAC_USE;
if (!is_zero_ether_addr(macaddr))
memcpy(iface_v1.mac_addr, macaddr, ETH_ALEN);
else
brcmf_set_vif_sta_macaddr(ifp, iface_v1.mac_addr);
err = brcmf_fil_iovar_data_get(ifp, "interface_create",
&iface_v1,
sizeof(iface_v1));
if (err) {
brcmf_info("failed to create interface(v1), err=%d\n",
err);
} else {
brcmf_dbg(INFO, "interface created(v1)\n");
return 0;
}
/* interface_create version 2 */
memset(&iface_v2, 0, sizeof(iface_v2));
iface_v2.ver = WL_INTERFACE_CREATE_VER_2;
iface_v2.flags = WL_INTERFACE_MAC_USE;
iface_v2.iftype = WL_INTERFACE_CREATE_STA;
if (!is_zero_ether_addr(macaddr))
memcpy(iface_v2.mac_addr, macaddr, ETH_ALEN);
else
brcmf_set_vif_sta_macaddr(ifp, iface_v2.mac_addr);
err = brcmf_fil_iovar_data_get(ifp, "interface_create",
&iface_v2,
sizeof(iface_v2));
if (err) {
brcmf_info("failed to create interface(v2), err=%d\n",
err);
} else {
brcmf_dbg(INFO, "interface created(v2)\n");
return 0;
}
/* interface_create version 3+ */
/* get supported version from firmware side */
iface_create_ver = 0;
err = brcmf_fil_bsscfg_int_get(ifp, "interface_create",
&iface_create_ver);
if (err) {
brcmf_err("fail to get supported version, err=%d\n", err);
return -EOPNOTSUPP;
}
switch (iface_create_ver) {
case WL_INTERFACE_CREATE_VER_3:
memset(&iface_v3, 0, sizeof(iface_v3));
iface_v3.ver = WL_INTERFACE_CREATE_VER_3;
iface_v3.flags = WL_INTERFACE_MAC_USE;
iface_v3.iftype = WL_INTERFACE_CREATE_STA;
if (!is_zero_ether_addr(macaddr))
memcpy(iface_v3.mac_addr, macaddr, ETH_ALEN);
else
brcmf_set_vif_sta_macaddr(ifp, iface_v3.mac_addr);
err = brcmf_fil_iovar_data_get(ifp, "interface_create",
&iface_v3,
sizeof(iface_v3));
if (!err)
brcmf_dbg(INFO, "interface created(v3)\n");
break;
default:
brcmf_err("not support interface create(v%d)\n",
iface_create_ver);
err = -EOPNOTSUPP;
break;
}
if (err) {
brcmf_info("station interface creation failed (%d)\n",
err);
return -EIO;
}
return 0;
}
static int brcmf_cfg80211_request_ap_if(struct brcmf_if *ifp) static int brcmf_cfg80211_request_ap_if(struct brcmf_if *ifp)
{ {
struct wl_interface_create_v1 iface_v1;
struct wl_interface_create_v2 iface_v2;
struct wl_interface_create_v3 iface_v3;
u32 iface_create_ver;
struct brcmf_pub *drvr = ifp->drvr; struct brcmf_pub *drvr = ifp->drvr;
struct brcmf_mbss_ssid_le mbss_ssid_le; struct brcmf_mbss_ssid_le mbss_ssid_le;
int bsscfgidx; int bsscfgidx;
int err; int err;
memset(&mbss_ssid_le, 0, sizeof(mbss_ssid_le)); /* interface_create version 1 */
bsscfgidx = brcmf_get_first_free_bsscfgidx(ifp->drvr); memset(&iface_v1, 0, sizeof(iface_v1));
if (bsscfgidx < 0) iface_v1.ver = WL_INTERFACE_CREATE_VER_1;
return bsscfgidx; iface_v1.flags = WL_INTERFACE_CREATE_AP |
WL_INTERFACE_MAC_USE;
mbss_ssid_le.bsscfgidx = cpu_to_le32(bsscfgidx); brcmf_set_vif_sta_macaddr(ifp, iface_v1.mac_addr);
mbss_ssid_le.SSID_len = cpu_to_le32(5);
sprintf(mbss_ssid_le.SSID, "ssid%d" , bsscfgidx);
err = brcmf_fil_bsscfg_data_set(ifp, "bsscfg:ssid", &mbss_ssid_le, err = brcmf_fil_iovar_data_get(ifp, "interface_create",
sizeof(mbss_ssid_le)); &iface_v1,
if (err < 0) sizeof(iface_v1));
bphy_err(drvr, "setting ssid failed %d\n", err); if (err) {
brcmf_info("failed to create interface(v1), err=%d\n",
err);
} else {
brcmf_dbg(INFO, "interface created(v1)\n");
return 0;
}
/* interface_create version 2 */
memset(&iface_v2, 0, sizeof(iface_v2));
iface_v2.ver = WL_INTERFACE_CREATE_VER_2;
iface_v2.flags = WL_INTERFACE_MAC_USE;
iface_v2.iftype = WL_INTERFACE_CREATE_AP;
brcmf_set_vif_sta_macaddr(ifp, iface_v2.mac_addr);
err = brcmf_fil_iovar_data_get(ifp, "interface_create",
&iface_v2,
sizeof(iface_v2));
if (err) {
brcmf_info("failed to create interface(v2), err=%d\n",
err);
} else {
brcmf_dbg(INFO, "interface created(v2)\n");
return 0;
}
/* interface_create version 3+ */
/* get supported version from firmware side */
iface_create_ver = 0;
err = brcmf_fil_bsscfg_int_get(ifp, "interface_create",
&iface_create_ver);
if (err) {
brcmf_err("fail to get supported version, err=%d\n", err);
return -EOPNOTSUPP;
}
switch (iface_create_ver) {
case WL_INTERFACE_CREATE_VER_3:
memset(&iface_v3, 0, sizeof(iface_v3));
iface_v3.ver = WL_INTERFACE_CREATE_VER_3;
iface_v3.flags = WL_INTERFACE_MAC_USE;
iface_v3.iftype = WL_INTERFACE_CREATE_AP;
brcmf_set_vif_sta_macaddr(ifp, iface_v3.mac_addr);
err = brcmf_fil_iovar_data_get(ifp, "interface_create",
&iface_v3,
sizeof(iface_v3));
if (!err)
brcmf_dbg(INFO, "interface created(v3)\n");
break;
default:
brcmf_err("not support interface create(v%d)\n",
iface_create_ver);
err = -EOPNOTSUPP;
break;
}
if (err) {
brcmf_info("Does not support interface_create (%d)\n",
err);
memset(&mbss_ssid_le, 0, sizeof(mbss_ssid_le));
bsscfgidx = brcmf_get_first_free_bsscfgidx(ifp->drvr);
if (bsscfgidx < 0)
return bsscfgidx;
mbss_ssid_le.bsscfgidx = cpu_to_le32(bsscfgidx);
mbss_ssid_le.SSID_len = cpu_to_le32(5);
sprintf(mbss_ssid_le.SSID, "ssid%d", bsscfgidx);
err = brcmf_fil_bsscfg_data_set(ifp, "bsscfg:ssid", &mbss_ssid_le,
sizeof(mbss_ssid_le));
if (err < 0)
bphy_err(drvr, "setting ssid failed %d\n", err);
}
return err; return err;
} }
/** /**
* brcmf_ap_add_vif() - create a new AP virtual interface for multiple BSS * brcmf_apsta_add_vif() - create a new AP or STA virtual interface
* *
* @wiphy: wiphy device of new interface. * @wiphy: wiphy device of new interface.
* @name: name of the new interface. * @name: name of the new interface.
* @params: contains mac address for AP device. * @params: contains mac address for AP or STA device.
* @type: interface type.
*/ */
static static
struct wireless_dev *brcmf_ap_add_vif(struct wiphy *wiphy, const char *name, struct wireless_dev *brcmf_apsta_add_vif(struct wiphy *wiphy, const char *name,
struct vif_params *params) struct vif_params *params,
enum nl80211_iftype type)
{ {
struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy); struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
struct brcmf_if *ifp = netdev_priv(cfg_to_ndev(cfg)); struct brcmf_if *ifp = netdev_priv(cfg_to_ndev(cfg));
@ -562,18 +822,24 @@ struct wireless_dev *brcmf_ap_add_vif(struct wiphy *wiphy, const char *name,
struct brcmf_cfg80211_vif *vif; struct brcmf_cfg80211_vif *vif;
int err; int err;
if (type != NL80211_IFTYPE_STATION && type != NL80211_IFTYPE_AP)
return ERR_PTR(-EINVAL);
if (brcmf_cfg80211_vif_event_armed(cfg)) if (brcmf_cfg80211_vif_event_armed(cfg))
return ERR_PTR(-EBUSY); return ERR_PTR(-EBUSY);
brcmf_dbg(INFO, "Adding vif \"%s\"\n", name); brcmf_dbg(INFO, "Adding vif \"%s\"\n", name);
vif = brcmf_alloc_vif(cfg, NL80211_IFTYPE_AP); vif = brcmf_alloc_vif(cfg, type);
if (IS_ERR(vif)) if (IS_ERR(vif))
return (struct wireless_dev *)vif; return (struct wireless_dev *)vif;
brcmf_cfg80211_arm_vif_event(cfg, vif); brcmf_cfg80211_arm_vif_event(cfg, vif);
err = brcmf_cfg80211_request_ap_if(ifp); if (type == NL80211_IFTYPE_STATION)
err = brcmf_cfg80211_request_sta_if(ifp, params->macaddr);
else
err = brcmf_cfg80211_request_ap_if(ifp);
if (err) { if (err) {
brcmf_cfg80211_arm_vif_event(cfg, NULL); brcmf_cfg80211_arm_vif_event(cfg, NULL);
goto fail; goto fail;
@ -720,15 +986,15 @@ static struct wireless_dev *brcmf_cfg80211_add_iface(struct wiphy *wiphy,
} }
switch (type) { switch (type) {
case NL80211_IFTYPE_ADHOC: case NL80211_IFTYPE_ADHOC:
case NL80211_IFTYPE_STATION:
case NL80211_IFTYPE_AP_VLAN: case NL80211_IFTYPE_AP_VLAN:
case NL80211_IFTYPE_WDS: case NL80211_IFTYPE_WDS:
case NL80211_IFTYPE_MESH_POINT: case NL80211_IFTYPE_MESH_POINT:
return ERR_PTR(-EOPNOTSUPP); return ERR_PTR(-EOPNOTSUPP);
case NL80211_IFTYPE_MONITOR: case NL80211_IFTYPE_MONITOR:
return brcmf_mon_add_vif(wiphy, name); return brcmf_mon_add_vif(wiphy, name);
case NL80211_IFTYPE_STATION:
case NL80211_IFTYPE_AP: case NL80211_IFTYPE_AP:
wdev = brcmf_ap_add_vif(wiphy, name, params); wdev = brcmf_apsta_add_vif(wiphy, name, params, type);
break; break;
case NL80211_IFTYPE_P2P_CLIENT: case NL80211_IFTYPE_P2P_CLIENT:
case NL80211_IFTYPE_P2P_GO: case NL80211_IFTYPE_P2P_GO:
@ -848,8 +1114,8 @@ s32 brcmf_notify_escan_complete(struct brcmf_cfg80211_info *cfg,
return err; return err;
} }
static int brcmf_cfg80211_del_ap_iface(struct wiphy *wiphy, static int brcmf_cfg80211_del_apsta_iface(struct wiphy *wiphy,
struct wireless_dev *wdev) struct wireless_dev *wdev)
{ {
struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy); struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
struct net_device *ndev = wdev->netdev; struct net_device *ndev = wdev->netdev;
@ -906,15 +1172,15 @@ int brcmf_cfg80211_del_iface(struct wiphy *wiphy, struct wireless_dev *wdev)
switch (wdev->iftype) { switch (wdev->iftype) {
case NL80211_IFTYPE_ADHOC: case NL80211_IFTYPE_ADHOC:
case NL80211_IFTYPE_STATION:
case NL80211_IFTYPE_AP_VLAN: case NL80211_IFTYPE_AP_VLAN:
case NL80211_IFTYPE_WDS: case NL80211_IFTYPE_WDS:
case NL80211_IFTYPE_MESH_POINT: case NL80211_IFTYPE_MESH_POINT:
return -EOPNOTSUPP; return -EOPNOTSUPP;
case NL80211_IFTYPE_MONITOR: case NL80211_IFTYPE_MONITOR:
return brcmf_mon_del_vif(wiphy, wdev); return brcmf_mon_del_vif(wiphy, wdev);
case NL80211_IFTYPE_STATION:
case NL80211_IFTYPE_AP: case NL80211_IFTYPE_AP:
return brcmf_cfg80211_del_ap_iface(wiphy, wdev); return brcmf_cfg80211_del_apsta_iface(wiphy, wdev);
case NL80211_IFTYPE_P2P_CLIENT: case NL80211_IFTYPE_P2P_CLIENT:
case NL80211_IFTYPE_P2P_GO: case NL80211_IFTYPE_P2P_GO:
case NL80211_IFTYPE_P2P_DEVICE: case NL80211_IFTYPE_P2P_DEVICE:
@ -6002,7 +6268,7 @@ done:
brcmf_dbg(CONN, "Report roaming result\n"); brcmf_dbg(CONN, "Report roaming result\n");
if (profile->use_fwsup == BRCMF_PROFILE_FWSUP_1X && profile->is_ft) { if (profile->use_fwsup == BRCMF_PROFILE_FWSUP_1X && profile->is_ft) {
cfg80211_port_authorized(ndev, profile->bssid, GFP_KERNEL); cfg80211_port_authorized(ndev, profile->bssid, NULL, 0, GFP_KERNEL);
brcmf_dbg(CONN, "Report port authorized\n"); brcmf_dbg(CONN, "Report port authorized\n");
} }
@ -6973,7 +7239,7 @@ brcmf_txrx_stypes[NUM_NL80211_IFTYPES] = {
* *
* p2p, mchan, and mbss: * p2p, mchan, and mbss:
* *
* #STA <= 1, #P2P-DEV <= 1, #{P2P-CL, P2P-GO} <= 1, channels = 2, 3 total * #STA <= 2, #P2P-DEV <= 1, #{P2P-CL, P2P-GO} <= 1, channels = 2, 3 total
* #STA <= 1, #P2P-DEV <= 1, #AP <= 1, #P2P-CL <= 1, channels = 1, 4 total * #STA <= 1, #P2P-DEV <= 1, #AP <= 1, #P2P-CL <= 1, channels = 1, 4 total
* #AP <= 4, matching BI, channels = 1, 4 total * #AP <= 4, matching BI, channels = 1, 4 total
* *
@ -7019,7 +7285,7 @@ static int brcmf_setup_ifmodes(struct wiphy *wiphy, struct brcmf_if *ifp)
goto err; goto err;
combo[c].num_different_channels = 1 + (rsdb || (p2p && mchan)); combo[c].num_different_channels = 1 + (rsdb || (p2p && mchan));
c0_limits[i].max = 1; c0_limits[i].max = 1 + (p2p && mchan);
c0_limits[i++].types = BIT(NL80211_IFTYPE_STATION); c0_limits[i++].types = BIT(NL80211_IFTYPE_STATION);
if (mon_flag) { if (mon_flag) {
c0_limits[i].max = 1; c0_limits[i].max = 1;
@ -7525,6 +7791,231 @@ static s32 brcmf_translate_country_code(struct brcmf_pub *drvr, char alpha2[2],
return 0; return 0;
} }
static int
brcmf_parse_dump_obss(char *buf, struct brcmf_dump_survey *survey)
{
int i;
char *token;
char delim[] = "\n ";
unsigned long val;
int err = 0;
token = strsep(&buf, delim);
while (token) {
if (!strcmp(token, "OBSS")) {
for (i = 0; i < OBSS_TOKEN_IDX; i++)
token = strsep(&buf, delim);
err = kstrtoul(token, 10, &val);
if (err)
break;
survey->obss = val;
}
if (!strcmp(token, "IBSS")) {
for (i = 0; i < IBSS_TOKEN_IDX; i++)
token = strsep(&buf, delim);
err = kstrtoul(token, 10, &val);
if (err)
break;
survey->ibss = val;
}
if (!strcmp(token, "TXDur")) {
for (i = 0; i < TX_TOKEN_IDX; i++)
token = strsep(&buf, delim);
err = kstrtoul(token, 10, &val);
if (err)
break;
survey->tx = val;
}
if (!strcmp(token, "Category")) {
for (i = 0; i < CTG_TOKEN_IDX; i++)
token = strsep(&buf, delim);
err = kstrtoul(token, 10, &val);
if (err)
break;
survey->no_ctg = val;
}
if (!strcmp(token, "Packet")) {
for (i = 0; i < PKT_TOKEN_IDX; i++)
token = strsep(&buf, delim);
err = kstrtoul(token, 10, &val);
if (err)
break;
survey->no_pckt = val;
}
if (!strcmp(token, "Opp(time):")) {
for (i = 0; i < IDLE_TOKEN_IDX; i++)
token = strsep(&buf, delim);
err = kstrtoul(token, 10, &val);
if (err)
break;
survey->idle = val;
}
token = strsep(&buf, delim);
}
return err;
}
static int
brcmf_dump_obss(struct brcmf_if *ifp, struct cca_msrmnt_query req,
struct brcmf_dump_survey *survey)
{
struct cca_stats_n_flags *results;
char *buf;
int err;
buf = kzalloc(sizeof(char) * BRCMF_DCMD_MEDLEN, GFP_KERNEL);
if (!buf)
return -ENOMEM;
memcpy(buf, &req, sizeof(struct cca_msrmnt_query));
err = brcmf_fil_iovar_data_get(ifp, "dump_obss",
buf, BRCMF_DCMD_MEDLEN);
if (err) {
brcmf_err("dump_obss error (%d)\n", err);
err = -EINVAL;
goto exit;
}
results = (struct cca_stats_n_flags *)(buf);
if (req.msrmnt_query)
brcmf_parse_dump_obss(results->buf, survey);
exit:
kfree(buf);
return err;
}
static s32
cfg80211_set_channel(struct wiphy *wiphy, struct net_device *dev,
struct ieee80211_channel *chan,
enum nl80211_channel_type channel_type)
{
u16 chspec = 0;
int err = 0;
struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
struct brcmf_if *ifp = netdev_priv(cfg_to_ndev(cfg));
/* set_channel */
chspec = channel_to_chanspec(&cfg->d11inf, chan);
if (chspec != INVCHANSPEC) {
err = brcmf_fil_iovar_int_set(ifp, "chanspec", chspec);
if (err) {
brcmf_err("set chanspec 0x%04x fail, reason %d\n", chspec, err);
err = -EINVAL;
}
} else {
brcmf_err("failed to convert host chanspec to fw chanspec\n");
err = -EINVAL;
}
return err;
}
static int
brcmf_cfg80211_dump_survey(struct wiphy *wiphy, struct net_device *ndev,
int idx, struct survey_info *info)
{
struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
struct brcmf_if *ifp = netdev_priv(cfg_to_ndev(cfg));
struct brcmf_dump_survey survey = {};
struct ieee80211_supported_band *band;
struct ieee80211_channel *chan;
struct cca_msrmnt_query req;
u32 noise;
int err;
brcmf_dbg(TRACE, "Enter: channel idx=%d\n", idx);
/* Do not run survey when VIF in CONNECTING / CONNECTED states */
if ((test_bit(BRCMF_VIF_STATUS_CONNECTING, &ifp->vif->sme_state)) ||
(test_bit(BRCMF_VIF_STATUS_CONNECTED, &ifp->vif->sme_state))) {
return -EBUSY;
}
band = wiphy->bands[NL80211_BAND_2GHZ];
if (band && idx >= band->n_channels) {
idx -= band->n_channels;
band = NULL;
}
if (!band || idx >= band->n_channels) {
band = wiphy->bands[NL80211_BAND_5GHZ];
if (idx >= band->n_channels)
return -ENOENT;
}
/* Setting current channel to the requested channel */
chan = &band->channels[idx];
err = cfg80211_set_channel(wiphy, ndev, chan, NL80211_CHAN_HT20);
if (err) {
info->channel = chan;
info->filled = 0;
return 0;
}
/* Disable mpc */
brcmf_set_mpc(ifp, 0);
/* Set interface up, explicitly. */
err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_UP, 1);
if (err) {
brcmf_err("set interface up failed, err = %d\n", err);
goto exit;
}
/* Get noise value */
err = brcmf_fil_cmd_int_get(ifp, BRCMF_C_GET_PHY_NOISE, &noise);
if (err) {
brcmf_err("Get Phy Noise failed, use dummy value\n");
noise = CHAN_NOISE_DUMMY;
}
/* Start Measurement for obss stats on current channel */
req.msrmnt_query = 0;
req.time_req = ACS_MSRMNT_DELAY;
err = brcmf_dump_obss(ifp, req, &survey);
if (err)
goto exit;
/* Add 10 ms for IOVAR completion */
msleep(ACS_MSRMNT_DELAY + 10);
/* Issue IOVAR to collect measurement results */
req.msrmnt_query = 1;
err = brcmf_dump_obss(ifp, req, &survey);
if (err)
goto exit;
info->channel = chan;
info->noise = noise;
info->time = ACS_MSRMNT_DELAY;
info->time_busy = ACS_MSRMNT_DELAY - survey.idle;
info->time_rx = survey.obss + survey.ibss + survey.no_ctg +
survey.no_pckt;
info->time_tx = survey.tx;
info->filled = SURVEY_INFO_NOISE_DBM | SURVEY_INFO_TIME |
SURVEY_INFO_TIME_BUSY | SURVEY_INFO_TIME_RX |
SURVEY_INFO_TIME_TX;
brcmf_dbg(INFO, "OBSS dump: channel %d: survey duration %d\n",
ieee80211_frequency_to_channel(chan->center_freq),
ACS_MSRMNT_DELAY);
brcmf_dbg(INFO, "noise(%d) busy(%llu) rx(%llu) tx(%llu)\n",
info->noise, info->time_busy, info->time_rx, info->time_tx);
exit:
if (!brcmf_is_apmode(ifp->vif))
brcmf_set_mpc(ifp, 1);
return err;
}
static void brcmf_cfg80211_reg_notifier(struct wiphy *wiphy, static void brcmf_cfg80211_reg_notifier(struct wiphy *wiphy,
struct regulatory_request *req) struct regulatory_request *req)
{ {
@ -7676,6 +8167,9 @@ struct brcmf_cfg80211_info *brcmf_cfg80211_attach(struct brcmf_pub *drvr,
if (brcmf_feat_is_enabled(ifp, BRCMF_FEAT_WOWL_GTK)) if (brcmf_feat_is_enabled(ifp, BRCMF_FEAT_WOWL_GTK))
ops->set_rekey_data = brcmf_cfg80211_set_rekey_data; ops->set_rekey_data = brcmf_cfg80211_set_rekey_data;
#endif #endif
if (brcmf_feat_is_enabled(ifp, BRCMF_FEAT_DUMP_OBSS))
ops->dump_survey = brcmf_cfg80211_dump_survey;
err = wiphy_register(wiphy); err = wiphy_register(wiphy);
if (err < 0) { if (err < 0) {
bphy_err(drvr, "Could not register wiphy device (%d)\n", err); bphy_err(drvr, "Could not register wiphy device (%d)\n", err);

View File

@ -1399,7 +1399,8 @@ void brcmf_fw_crashed(struct device *dev)
brcmf_dev_coredump(dev); brcmf_dev_coredump(dev);
schedule_work(&drvr->bus_reset); if (drvr->bus_reset.func)
schedule_work(&drvr->bus_reset);
} }
void brcmf_detach(struct device *dev) void brcmf_detach(struct device *dev)

View File

@ -136,6 +136,7 @@ struct brcmf_pub {
struct work_struct bus_reset; struct work_struct bus_reset;
u8 clmver[BRCMF_DCMD_SMLEN]; u8 clmver[BRCMF_DCMD_SMLEN];
u8 sta_mac_idx;
}; };
/* forward declarations */ /* forward declarations */

View File

@ -143,7 +143,7 @@ static void brcmf_feat_iovar_int_get(struct brcmf_if *ifp,
ifp->fwil_fwerr = true; ifp->fwil_fwerr = true;
err = brcmf_fil_iovar_int_get(ifp, name, &data); err = brcmf_fil_iovar_int_get(ifp, name, &data);
if (err == 0) { if (err != -BRCMF_FW_UNSUPPORTED) {
brcmf_dbg(INFO, "enabling feature: %s\n", brcmf_feat_names[id]); brcmf_dbg(INFO, "enabling feature: %s\n", brcmf_feat_names[id]);
ifp->drvr->feat_flags |= BIT(id); ifp->drvr->feat_flags |= BIT(id);
} else { } else {
@ -281,6 +281,7 @@ void brcmf_feat_attach(struct brcmf_pub *drvr)
brcmf_feat_iovar_int_get(ifp, BRCMF_FEAT_RSDB, "rsdb_mode"); brcmf_feat_iovar_int_get(ifp, BRCMF_FEAT_RSDB, "rsdb_mode");
brcmf_feat_iovar_int_get(ifp, BRCMF_FEAT_TDLS, "tdls_enable"); brcmf_feat_iovar_int_get(ifp, BRCMF_FEAT_TDLS, "tdls_enable");
brcmf_feat_iovar_int_get(ifp, BRCMF_FEAT_MFP, "mfp"); brcmf_feat_iovar_int_get(ifp, BRCMF_FEAT_MFP, "mfp");
brcmf_feat_iovar_int_get(ifp, BRCMF_FEAT_DUMP_OBSS, "dump_obss");
pfn_mac.version = BRCMF_PFN_MACADDR_CFG_VER; pfn_mac.version = BRCMF_PFN_MACADDR_CFG_VER;
err = brcmf_fil_iovar_data_get(ifp, "pfn_macaddr", &pfn_mac, err = brcmf_fil_iovar_data_get(ifp, "pfn_macaddr", &pfn_mac,

View File

@ -29,6 +29,7 @@
* DOT11H: firmware supports 802.11h * DOT11H: firmware supports 802.11h
* SAE: simultaneous authentication of equals * SAE: simultaneous authentication of equals
* FWAUTH: Firmware authenticator * FWAUTH: Firmware authenticator
* DUMP_OBSS: Firmware has capable to dump obss info to support ACS
*/ */
#define BRCMF_FEAT_LIST \ #define BRCMF_FEAT_LIST \
BRCMF_FEAT_DEF(MBSS) \ BRCMF_FEAT_DEF(MBSS) \
@ -51,7 +52,8 @@
BRCMF_FEAT_DEF(MONITOR_FMT_HW_RX_HDR) \ BRCMF_FEAT_DEF(MONITOR_FMT_HW_RX_HDR) \
BRCMF_FEAT_DEF(DOT11H) \ BRCMF_FEAT_DEF(DOT11H) \
BRCMF_FEAT_DEF(SAE) \ BRCMF_FEAT_DEF(SAE) \
BRCMF_FEAT_DEF(FWAUTH) BRCMF_FEAT_DEF(FWAUTH) \
BRCMF_FEAT_DEF(DUMP_OBSS)
/* /*
* Quirks: * Quirks:

View File

@ -12,6 +12,8 @@
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <linux/bcma/bcma.h> #include <linux/bcma/bcma.h>
#include <linux/sched.h> #include <linux/sched.h>
#include <linux/sched/signal.h>
#include <linux/kthread.h>
#include <linux/io.h> #include <linux/io.h>
#include <asm/unaligned.h> #include <asm/unaligned.h>
@ -340,6 +342,11 @@ struct brcmf_pciedev_info {
u16 value); u16 value);
struct brcmf_mp_device *settings; struct brcmf_mp_device *settings;
struct brcmf_otp_params otp; struct brcmf_otp_params otp;
#ifdef DEBUG
u32 console_interval;
bool console_active;
struct timer_list timer;
#endif
}; };
struct brcmf_pcie_ringbuf { struct brcmf_pcie_ringbuf {
@ -440,6 +447,9 @@ static void brcmf_pcie_setup(struct device *dev, int ret,
struct brcmf_fw_request *fwreq); struct brcmf_fw_request *fwreq);
static struct brcmf_fw_request * static struct brcmf_fw_request *
brcmf_pcie_prepare_fw_request(struct brcmf_pciedev_info *devinfo); brcmf_pcie_prepare_fw_request(struct brcmf_pciedev_info *devinfo);
static void
brcmf_pcie_fwcon_timer(struct brcmf_pciedev_info *devinfo, bool active);
static void brcmf_pcie_debugfs_create(struct device *dev);
static u16 static u16
brcmf_pcie_read_reg16(struct brcmf_pciedev_info *devinfo, u32 reg_offset) brcmf_pcie_read_reg16(struct brcmf_pciedev_info *devinfo, u32 reg_offset)
@ -1218,6 +1228,10 @@ static int brcmf_pcie_init_ringbuffers(struct brcmf_pciedev_info *devinfo)
BRCMF_NROF_H2D_COMMON_MSGRINGS; BRCMF_NROF_H2D_COMMON_MSGRINGS;
max_completionrings = BRCMF_NROF_D2H_COMMON_MSGRINGS; max_completionrings = BRCMF_NROF_D2H_COMMON_MSGRINGS;
} }
if (max_flowrings > 256) {
brcmf_err(bus, "invalid max_flowrings(%d)\n", max_flowrings);
return -EIO;
}
if (devinfo->dma_idx_sz != 0) { if (devinfo->dma_idx_sz != 0) {
bufsz = (max_submissionrings + max_completionrings) * bufsz = (max_submissionrings + max_completionrings) *
@ -1413,6 +1427,11 @@ fail:
static void brcmf_pcie_down(struct device *dev) static void brcmf_pcie_down(struct device *dev)
{ {
struct brcmf_bus *bus_if = dev_get_drvdata(dev);
struct brcmf_pciedev *pcie_bus_dev = bus_if->bus_priv.pcie;
struct brcmf_pciedev_info *devinfo = pcie_bus_dev->devinfo;
brcmf_pcie_fwcon_timer(devinfo, false);
} }
static int brcmf_pcie_preinit(struct device *dev) static int brcmf_pcie_preinit(struct device *dev)
@ -1547,6 +1566,7 @@ static const struct brcmf_bus_ops brcmf_pcie_bus_ops = {
.get_memdump = brcmf_pcie_get_memdump, .get_memdump = brcmf_pcie_get_memdump,
.get_blob = brcmf_pcie_get_blob, .get_blob = brcmf_pcie_get_blob,
.reset = brcmf_pcie_reset, .reset = brcmf_pcie_reset,
.debugfs_create = brcmf_pcie_debugfs_create,
}; };
@ -2048,13 +2068,14 @@ static void brcmf_pcie_setup(struct device *dev, int ret,
struct brcmf_commonring **flowrings; struct brcmf_commonring **flowrings;
u32 i, nvram_len; u32 i, nvram_len;
bus = dev_get_drvdata(dev);
pcie_bus_dev = bus->bus_priv.pcie;
devinfo = pcie_bus_dev->devinfo;
/* check firmware loading result */ /* check firmware loading result */
if (ret) if (ret)
goto fail; goto fail;
bus = dev_get_drvdata(dev);
pcie_bus_dev = bus->bus_priv.pcie;
devinfo = pcie_bus_dev->devinfo;
brcmf_pcie_attach(devinfo); brcmf_pcie_attach(devinfo);
fw = fwreq->items[BRCMF_PCIE_FW_CODE].binary; fw = fwreq->items[BRCMF_PCIE_FW_CODE].binary;
@ -2123,9 +2144,14 @@ static void brcmf_pcie_setup(struct device *dev, int ret,
brcmf_pcie_bus_console_read(devinfo, false); brcmf_pcie_bus_console_read(devinfo, false);
brcmf_pcie_fwcon_timer(devinfo, true);
return; return;
fail: fail:
brcmf_err(bus, "Dongle setup failed\n");
brcmf_pcie_bus_console_read(devinfo, true);
brcmf_fw_crashed(dev);
device_release_driver(dev); device_release_driver(dev);
} }
@ -2197,6 +2223,105 @@ brcmf_pcie_prepare_fw_request(struct brcmf_pciedev_info *devinfo)
return fwreq; return fwreq;
} }
#ifdef DEBUG
static void
brcmf_pcie_fwcon_timer(struct brcmf_pciedev_info *devinfo, bool active)
{
if (!active) {
if (devinfo->console_active) {
del_timer_sync(&devinfo->timer);
devinfo->console_active = false;
}
return;
}
/* don't start the timer */
if (devinfo->state != BRCMFMAC_PCIE_STATE_UP ||
!devinfo->console_interval || !BRCMF_FWCON_ON())
return;
if (!devinfo->console_active) {
devinfo->timer.expires = jiffies + devinfo->console_interval;
add_timer(&devinfo->timer);
devinfo->console_active = true;
} else {
/* Reschedule the timer */
mod_timer(&devinfo->timer, jiffies + devinfo->console_interval);
}
}
static void
brcmf_pcie_fwcon(struct timer_list *t)
{
struct brcmf_pciedev_info *devinfo = from_timer(devinfo, t, timer);
if (!devinfo->console_active)
return;
brcmf_pcie_bus_console_read(devinfo, false);
/* Reschedule the timer if console interval is not zero */
mod_timer(&devinfo->timer, jiffies + devinfo->console_interval);
}
static int brcmf_pcie_console_interval_get(void *data, u64 *val)
{
struct brcmf_pciedev_info *devinfo = data;
*val = devinfo->console_interval;
return 0;
}
static int brcmf_pcie_console_interval_set(void *data, u64 val)
{
struct brcmf_pciedev_info *devinfo = data;
if (val > MAX_CONSOLE_INTERVAL)
return -EINVAL;
devinfo->console_interval = val;
if (!val && devinfo->console_active)
brcmf_pcie_fwcon_timer(devinfo, false);
else if (val)
brcmf_pcie_fwcon_timer(devinfo, true);
return 0;
}
DEFINE_SIMPLE_ATTRIBUTE(brcmf_pcie_console_interval_fops,
brcmf_pcie_console_interval_get,
brcmf_pcie_console_interval_set,
"%llu\n");
static void brcmf_pcie_debugfs_create(struct device *dev)
{
struct brcmf_bus *bus_if = dev_get_drvdata(dev);
struct brcmf_pub *drvr = bus_if->drvr;
struct brcmf_pciedev *pcie_bus_dev = bus_if->bus_priv.pcie;
struct brcmf_pciedev_info *devinfo = pcie_bus_dev->devinfo;
struct dentry *dentry = brcmf_debugfs_get_devdir(drvr);
if (IS_ERR_OR_NULL(dentry))
return;
devinfo->console_interval = BRCMF_CONSOLE;
debugfs_create_file("console_interval", 0644, dentry, devinfo,
&brcmf_pcie_console_interval_fops);
}
#else
void brcmf_pcie_fwcon_timer(struct brcmf_pciedev_info *devinfo, bool active)
{
}
static void brcmf_pcie_debugfs_create(struct device *dev)
{
}
#endif
static int static int
brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id) brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{ {
@ -2278,6 +2403,11 @@ brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id)
goto fail_brcmf; goto fail_brcmf;
} }
#ifdef DEBUG
/* Set up the fwcon timer */
timer_setup(&devinfo->timer, brcmf_pcie_fwcon, 0);
#endif
fwreq = brcmf_pcie_prepare_fw_request(devinfo); fwreq = brcmf_pcie_prepare_fw_request(devinfo);
if (!fwreq) { if (!fwreq) {
ret = -ENOMEM; ret = -ENOMEM;
@ -2323,6 +2453,7 @@ brcmf_pcie_remove(struct pci_dev *pdev)
devinfo = bus->bus_priv.pcie->devinfo; devinfo = bus->bus_priv.pcie->devinfo;
brcmf_pcie_bus_console_read(devinfo, false); brcmf_pcie_bus_console_read(devinfo, false);
brcmf_pcie_fwcon_timer(devinfo, false);
devinfo->state = BRCMFMAC_PCIE_STATE_DOWN; devinfo->state = BRCMFMAC_PCIE_STATE_DOWN;
if (devinfo->ci) if (devinfo->ci)
@ -2366,6 +2497,7 @@ static int brcmf_pcie_pm_enter_D3(struct device *dev)
bus = dev_get_drvdata(dev); bus = dev_get_drvdata(dev);
devinfo = bus->bus_priv.pcie->devinfo; devinfo = bus->bus_priv.pcie->devinfo;
brcmf_pcie_fwcon_timer(devinfo, false);
brcmf_bus_change_state(bus, BRCMF_BUS_DOWN); brcmf_bus_change_state(bus, BRCMF_BUS_DOWN);
devinfo->mbdata_completed = false; devinfo->mbdata_completed = false;
@ -2409,6 +2541,7 @@ static int brcmf_pcie_pm_leave_D3(struct device *dev)
brcmf_bus_change_state(bus, BRCMF_BUS_UP); brcmf_bus_change_state(bus, BRCMF_BUS_UP);
brcmf_pcie_intr_enable(devinfo); brcmf_pcie_intr_enable(devinfo);
brcmf_pcie_hostready(devinfo); brcmf_pcie_hostready(devinfo);
brcmf_pcie_fwcon_timer(devinfo, true);
return 0; return 0;
} }

View File

@ -135,8 +135,6 @@ struct rte_console {
#define BRCMF_FIRSTREAD (1 << 6) #define BRCMF_FIRSTREAD (1 << 6)
#define BRCMF_CONSOLE 10 /* watchdog interval to poll console */
/* SBSDIO_DEVICE_CTL */ /* SBSDIO_DEVICE_CTL */
/* 1: device will assert busy signal when receiving CMD53 */ /* 1: device will assert busy signal when receiving CMD53 */

View File

@ -962,6 +962,7 @@ static int brcms_ops_beacon_set_tim(struct ieee80211_hw *hw,
static const struct ieee80211_ops brcms_ops = { static const struct ieee80211_ops brcms_ops = {
.tx = brcms_ops_tx, .tx = brcms_ops_tx,
.wake_tx_queue = ieee80211_handle_wake_tx_queue,
.start = brcms_ops_start, .start = brcms_ops_start,
.stop = brcms_ops_stop, .stop = brcms_ops_stop,
.add_interface = brcms_ops_add_interface, .add_interface = brcms_ops_add_interface,

View File

@ -3435,6 +3435,7 @@ static const struct attribute_group il3945_attribute_group = {
static struct ieee80211_ops il3945_mac_ops __ro_after_init = { static struct ieee80211_ops il3945_mac_ops __ro_after_init = {
.tx = il3945_mac_tx, .tx = il3945_mac_tx,
.wake_tx_queue = ieee80211_handle_wake_tx_queue,
.start = il3945_mac_start, .start = il3945_mac_start,
.stop = il3945_mac_stop, .stop = il3945_mac_stop,
.add_interface = il_mac_add_interface, .add_interface = il_mac_add_interface,

View File

@ -6304,6 +6304,7 @@ il4965_tx_queue_set_status(struct il_priv *il, struct il_tx_queue *txq,
static const struct ieee80211_ops il4965_mac_ops = { static const struct ieee80211_ops il4965_mac_ops = {
.tx = il4965_mac_tx, .tx = il4965_mac_tx,
.wake_tx_queue = ieee80211_handle_wake_tx_queue,
.start = il4965_mac_start, .start = il4965_mac_start,
.stop = il4965_mac_stop, .stop = il4965_mac_stop,
.add_interface = il_mac_add_interface, .add_interface = il_mac_add_interface,

View File

@ -1571,6 +1571,7 @@ static void iwlagn_mac_sta_notify(struct ieee80211_hw *hw,
const struct ieee80211_ops iwlagn_hw_ops = { const struct ieee80211_ops iwlagn_hw_ops = {
.tx = iwlagn_mac_tx, .tx = iwlagn_mac_tx,
.wake_tx_queue = ieee80211_handle_wake_tx_queue,
.start = iwlagn_mac_start, .start = iwlagn_mac_start,
.stop = iwlagn_mac_stop, .stop = iwlagn_mac_stop,
#ifdef CONFIG_PM_SLEEP #ifdef CONFIG_PM_SLEEP

View File

@ -705,6 +705,7 @@ static void p54_set_coverage_class(struct ieee80211_hw *dev,
static const struct ieee80211_ops p54_ops = { static const struct ieee80211_ops p54_ops = {
.tx = p54_tx_80211, .tx = p54_tx_80211,
.wake_tx_queue = ieee80211_handle_wake_tx_queue,
.start = p54_start, .start = p54_start,
.stop = p54_stop, .stop = p54_stop,
.add_interface = p54_add_interface, .add_interface = p54_add_interface,

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@ -3104,6 +3104,7 @@ static int mac80211_hwsim_change_sta_links(struct ieee80211_hw *hw,
#define HWSIM_COMMON_OPS \ #define HWSIM_COMMON_OPS \
.tx = mac80211_hwsim_tx, \ .tx = mac80211_hwsim_tx, \
.wake_tx_queue = ieee80211_handle_wake_tx_queue, \
.start = mac80211_hwsim_start, \ .start = mac80211_hwsim_start, \
.stop = mac80211_hwsim_stop, \ .stop = mac80211_hwsim_stop, \
.add_interface = mac80211_hwsim_add_interface, \ .add_interface = mac80211_hwsim_add_interface, \

View File

@ -474,6 +474,7 @@ static int lbtf_op_get_survey(struct ieee80211_hw *hw, int idx,
static const struct ieee80211_ops lbtf_ops = { static const struct ieee80211_ops lbtf_ops = {
.tx = lbtf_op_tx, .tx = lbtf_op_tx,
.wake_tx_queue = ieee80211_handle_wake_tx_queue,
.start = lbtf_op_start, .start = lbtf_op_start,
.stop = lbtf_op_stop, .stop = lbtf_op_stop,
.add_interface = lbtf_op_add_interface, .add_interface = lbtf_op_add_interface,

View File

@ -5611,6 +5611,7 @@ static void mwl8k_sw_scan_complete(struct ieee80211_hw *hw,
static const struct ieee80211_ops mwl8k_ops = { static const struct ieee80211_ops mwl8k_ops = {
.tx = mwl8k_tx, .tx = mwl8k_tx,
.wake_tx_queue = ieee80211_handle_wake_tx_queue,
.start = mwl8k_start, .start = mwl8k_start,
.stop = mwl8k_stop, .stop = mwl8k_stop,
.add_interface = mwl8k_add_interface, .add_interface = mwl8k_add_interface,

View File

@ -406,6 +406,7 @@ out:
const struct ieee80211_ops mt7601u_ops = { const struct ieee80211_ops mt7601u_ops = {
.tx = mt7601u_tx, .tx = mt7601u_tx,
.wake_tx_queue = ieee80211_handle_wake_tx_queue,
.start = mt7601u_start, .start = mt7601u_start,
.stop = mt7601u_stop, .stop = mt7601u_stop,
.add_interface = mt7601u_add_interface, .add_interface = mt7601u_add_interface,

View File

@ -686,6 +686,7 @@ static int plfxlc_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
static const struct ieee80211_ops plfxlc_ops = { static const struct ieee80211_ops plfxlc_ops = {
.tx = plfxlc_op_tx, .tx = plfxlc_op_tx,
.wake_tx_queue = ieee80211_handle_wake_tx_queue,
.start = plfxlc_op_start, .start = plfxlc_op_start,
.stop = plfxlc_op_stop, .stop = plfxlc_op_stop,
.add_interface = plfxlc_op_add_interface, .add_interface = plfxlc_op_add_interface,

View File

@ -1706,6 +1706,7 @@ static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
static const struct ieee80211_ops rt2400pci_mac80211_ops = { static const struct ieee80211_ops rt2400pci_mac80211_ops = {
.tx = rt2x00mac_tx, .tx = rt2x00mac_tx,
.wake_tx_queue = ieee80211_handle_wake_tx_queue,
.start = rt2x00mac_start, .start = rt2x00mac_start,
.stop = rt2x00mac_stop, .stop = rt2x00mac_stop,
.add_interface = rt2x00mac_add_interface, .add_interface = rt2x00mac_add_interface,

View File

@ -2004,6 +2004,7 @@ static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
static const struct ieee80211_ops rt2500pci_mac80211_ops = { static const struct ieee80211_ops rt2500pci_mac80211_ops = {
.tx = rt2x00mac_tx, .tx = rt2x00mac_tx,
.wake_tx_queue = ieee80211_handle_wake_tx_queue,
.start = rt2x00mac_start, .start = rt2x00mac_start,
.stop = rt2x00mac_stop, .stop = rt2x00mac_stop,
.add_interface = rt2x00mac_add_interface, .add_interface = rt2x00mac_add_interface,

View File

@ -1795,6 +1795,7 @@ static int rt2500usb_probe_hw(struct rt2x00_dev *rt2x00dev)
static const struct ieee80211_ops rt2500usb_mac80211_ops = { static const struct ieee80211_ops rt2500usb_mac80211_ops = {
.tx = rt2x00mac_tx, .tx = rt2x00mac_tx,
.wake_tx_queue = ieee80211_handle_wake_tx_queue,
.start = rt2x00mac_start, .start = rt2x00mac_start,
.stop = rt2x00mac_stop, .stop = rt2x00mac_stop,
.add_interface = rt2x00mac_add_interface, .add_interface = rt2x00mac_add_interface,

View File

@ -288,6 +288,7 @@ static int rt2800pci_read_eeprom(struct rt2x00_dev *rt2x00dev)
static const struct ieee80211_ops rt2800pci_mac80211_ops = { static const struct ieee80211_ops rt2800pci_mac80211_ops = {
.tx = rt2x00mac_tx, .tx = rt2x00mac_tx,
.wake_tx_queue = ieee80211_handle_wake_tx_queue,
.start = rt2x00mac_start, .start = rt2x00mac_start,
.stop = rt2x00mac_stop, .stop = rt2x00mac_stop,
.add_interface = rt2x00mac_add_interface, .add_interface = rt2x00mac_add_interface,

View File

@ -133,6 +133,7 @@ static int rt2800soc_write_firmware(struct rt2x00_dev *rt2x00dev,
static const struct ieee80211_ops rt2800soc_mac80211_ops = { static const struct ieee80211_ops rt2800soc_mac80211_ops = {
.tx = rt2x00mac_tx, .tx = rt2x00mac_tx,
.wake_tx_queue = ieee80211_handle_wake_tx_queue,
.start = rt2x00mac_start, .start = rt2x00mac_start,
.stop = rt2x00mac_stop, .stop = rt2x00mac_stop,
.add_interface = rt2x00mac_add_interface, .add_interface = rt2x00mac_add_interface,

View File

@ -630,6 +630,7 @@ static int rt2800usb_probe_hw(struct rt2x00_dev *rt2x00dev)
static const struct ieee80211_ops rt2800usb_mac80211_ops = { static const struct ieee80211_ops rt2800usb_mac80211_ops = {
.tx = rt2x00mac_tx, .tx = rt2x00mac_tx,
.wake_tx_queue = ieee80211_handle_wake_tx_queue,
.start = rt2x00mac_start, .start = rt2x00mac_start,
.stop = rt2x00mac_stop, .stop = rt2x00mac_stop,
.add_interface = rt2x00mac_add_interface, .add_interface = rt2x00mac_add_interface,

View File

@ -2873,6 +2873,7 @@ static u64 rt61pci_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
static const struct ieee80211_ops rt61pci_mac80211_ops = { static const struct ieee80211_ops rt61pci_mac80211_ops = {
.tx = rt2x00mac_tx, .tx = rt2x00mac_tx,
.wake_tx_queue = ieee80211_handle_wake_tx_queue,
.start = rt2x00mac_start, .start = rt2x00mac_start,
.stop = rt2x00mac_stop, .stop = rt2x00mac_stop,
.add_interface = rt2x00mac_add_interface, .add_interface = rt2x00mac_add_interface,

View File

@ -2292,6 +2292,7 @@ static u64 rt73usb_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
static const struct ieee80211_ops rt73usb_mac80211_ops = { static const struct ieee80211_ops rt73usb_mac80211_ops = {
.tx = rt2x00mac_tx, .tx = rt2x00mac_tx,
.wake_tx_queue = ieee80211_handle_wake_tx_queue,
.start = rt2x00mac_start, .start = rt2x00mac_start,
.stop = rt2x00mac_stop, .stop = rt2x00mac_stop,
.add_interface = rt2x00mac_add_interface, .add_interface = rt2x00mac_add_interface,

View File

@ -1608,6 +1608,7 @@ static void rtl8180_configure_filter(struct ieee80211_hw *dev,
static const struct ieee80211_ops rtl8180_ops = { static const struct ieee80211_ops rtl8180_ops = {
.tx = rtl8180_tx, .tx = rtl8180_tx,
.wake_tx_queue = ieee80211_handle_wake_tx_queue,
.start = rtl8180_start, .start = rtl8180_start,
.stop = rtl8180_stop, .stop = rtl8180_stop,
.add_interface = rtl8180_add_interface, .add_interface = rtl8180_add_interface,

View File

@ -1378,6 +1378,7 @@ static int rtl8187_conf_tx(struct ieee80211_hw *dev,
static const struct ieee80211_ops rtl8187_ops = { static const struct ieee80211_ops rtl8187_ops = {
.tx = rtl8187_tx, .tx = rtl8187_tx,
.wake_tx_queue = ieee80211_handle_wake_tx_queue,
.start = rtl8187_start, .start = rtl8187_start,
.stop = rtl8187_stop, .stop = rtl8187_stop,
.add_interface = rtl8187_add_interface, .add_interface = rtl8187_add_interface,

View File

@ -3,13 +3,14 @@
# RTL8XXXU Wireless LAN device configuration # RTL8XXXU Wireless LAN device configuration
# #
config RTL8XXXU config RTL8XXXU
tristate "RTL8723AU/RTL8188[CR]U/RTL819[12]CU (mac80211) support" tristate "Realtek 802.11n USB wireless chips support"
depends on MAC80211 && USB depends on MAC80211 && USB
help help
This is an alternative driver for various Realtek RTL8XXX This is an alternative driver for various Realtek RTL8XXX
parts written to utilize the Linux mac80211 stack. parts written to utilize the Linux mac80211 stack.
The driver is known to work with a number of RTL8723AU, The driver is known to work with a number of RTL8723AU,
RL8188CU, RTL8188RU, RTL8191CU, and RTL8192CU devices RL8188CU, RTL8188RU, RTL8191CU, RTL8192CU, RTL8723BU, RTL8192EU,
and RTL8188FU devices.
This driver is under development and has a limited feature This driver is under development and has a limited feature
set. In particular it does not yet support 40MHz channels set. In particular it does not yet support 40MHz channels
@ -22,7 +23,7 @@ config RTL8XXXU
but you will need to control which module you wish to load. but you will need to control which module you wish to load.
To compile this driver as a module, choose M here: the module will To compile this driver as a module, choose M here: the module will
be called r8xxxu. If unsure, say N. be called rtl8xxxu. If unsure, say N.
config RTL8XXXU_UNTESTED config RTL8XXXU_UNTESTED
bool "Include support for untested Realtek 8xxx USB devices (EXPERIMENTAL)" bool "Include support for untested Realtek 8xxx USB devices (EXPERIMENTAL)"

View File

@ -2,4 +2,4 @@
obj-$(CONFIG_RTL8XXXU) += rtl8xxxu.o obj-$(CONFIG_RTL8XXXU) += rtl8xxxu.o
rtl8xxxu-y := rtl8xxxu_core.o rtl8xxxu_8192e.o rtl8xxxu_8723b.o \ rtl8xxxu-y := rtl8xxxu_core.o rtl8xxxu_8192e.o rtl8xxxu_8723b.o \
rtl8xxxu_8723a.o rtl8xxxu_8192c.o rtl8xxxu_8723a.o rtl8xxxu_8192c.o rtl8xxxu_8188f.o

View File

@ -35,6 +35,7 @@
#define REALTEK_USB_CMD_IDX 0x00 #define REALTEK_USB_CMD_IDX 0x00
#define TX_TOTAL_PAGE_NUM 0xf8 #define TX_TOTAL_PAGE_NUM 0xf8
#define TX_TOTAL_PAGE_NUM_8188F 0xf7
#define TX_TOTAL_PAGE_NUM_8192E 0xf3 #define TX_TOTAL_PAGE_NUM_8192E 0xf3
#define TX_TOTAL_PAGE_NUM_8723B 0xf7 #define TX_TOTAL_PAGE_NUM_8723B 0xf7
/* (HPQ + LPQ + NPQ + PUBQ) = TX_TOTAL_PAGE_NUM */ /* (HPQ + LPQ + NPQ + PUBQ) = TX_TOTAL_PAGE_NUM */
@ -43,6 +44,11 @@
#define TX_PAGE_NUM_LO_PQ 0x02 #define TX_PAGE_NUM_LO_PQ 0x02
#define TX_PAGE_NUM_NORM_PQ 0x02 #define TX_PAGE_NUM_NORM_PQ 0x02
#define TX_PAGE_NUM_PUBQ_8188F 0xe5
#define TX_PAGE_NUM_HI_PQ_8188F 0x0c
#define TX_PAGE_NUM_LO_PQ_8188F 0x02
#define TX_PAGE_NUM_NORM_PQ_8188F 0x02
#define TX_PAGE_NUM_PUBQ_8192E 0xe7 #define TX_PAGE_NUM_PUBQ_8192E 0xe7
#define TX_PAGE_NUM_HI_PQ_8192E 0x08 #define TX_PAGE_NUM_HI_PQ_8192E 0x08
#define TX_PAGE_NUM_LO_PQ_8192E 0x0c #define TX_PAGE_NUM_LO_PQ_8192E 0x0c
@ -859,6 +865,50 @@ struct rtl8192eu_efuse {
u8 res12[0xc3]; u8 res12[0xc3];
}; };
struct rtl8188fu_efuse_tx_power {
u8 cck_base[6];
u8 ht40_base[5];
/* a: ofdm; b: ht20 */
struct rtl8723au_idx ht20_ofdm_1s_diff;
};
struct rtl8188fu_efuse {
__le16 rtl_id;
u8 res0[0x0e];
struct rtl8188fu_efuse_tx_power tx_power_index_A; /* 0x10 */
u8 res1[0x9c]; /* 0x1c */
u8 channel_plan; /* 0xb8 */
u8 xtal_k;
u8 thermal_meter;
u8 iqk_lck;
u8 res2[5];
u8 rf_board_option;
u8 rf_feature_option;
u8 rf_bt_setting;
u8 eeprom_version;
u8 eeprom_customer_id;
u8 res3[2];
u8 kfree_thermal_k_on;
u8 rf_antenna_option; /* 0xc9 */
u8 rfe_option;
u8 country_code;
u8 res4[4];
u8 vid; /* 0xd0 */
u8 res5[1];
u8 pid; /* 0xd2 */
u8 res6[1];
u8 usb_optional_function;
u8 res7[2];
u8 mac_addr[ETH_ALEN]; /* 0xd7 */
u8 res8[2];
u8 vendor_name[7];
u8 res9[2];
u8 device_name[7]; /* 0xe8 */
u8 res10[0x41];
u8 unknown[0x0d]; /* 0x130 */
u8 res11[0xc3];
};
struct rtl8xxxu_reg8val { struct rtl8xxxu_reg8val {
u16 reg; u16 reg;
u8 val; u8 val;
@ -1368,6 +1418,7 @@ struct rtl8xxxu_priv {
struct rtl8723bu_efuse efuse8723bu; struct rtl8723bu_efuse efuse8723bu;
struct rtl8192cu_efuse efuse8192; struct rtl8192cu_efuse efuse8192;
struct rtl8192eu_efuse efuse8192eu; struct rtl8192eu_efuse efuse8192eu;
struct rtl8188fu_efuse efuse8188fu;
} efuse_wifi; } efuse_wifi;
u32 adda_backup[RTL8XXXU_ADDA_REGS]; u32 adda_backup[RTL8XXXU_ADDA_REGS];
u32 mac_backup[RTL8XXXU_MAC_REGS]; u32 mac_backup[RTL8XXXU_MAC_REGS];
@ -1414,6 +1465,7 @@ struct rtl8xxxu_fileops {
void (*init_phy_bb) (struct rtl8xxxu_priv *priv); void (*init_phy_bb) (struct rtl8xxxu_priv *priv);
int (*init_phy_rf) (struct rtl8xxxu_priv *priv); int (*init_phy_rf) (struct rtl8xxxu_priv *priv);
void (*phy_init_antenna_selection) (struct rtl8xxxu_priv *priv); void (*phy_init_antenna_selection) (struct rtl8xxxu_priv *priv);
void (*phy_lc_calibrate) (struct rtl8xxxu_priv *priv);
void (*phy_iq_calibrate) (struct rtl8xxxu_priv *priv); void (*phy_iq_calibrate) (struct rtl8xxxu_priv *priv);
void (*config_channel) (struct ieee80211_hw *hw); void (*config_channel) (struct ieee80211_hw *hw);
int (*parse_rx_desc) (struct rtl8xxxu_priv *priv, struct sk_buff *skb); int (*parse_rx_desc) (struct rtl8xxxu_priv *priv, struct sk_buff *skb);
@ -1448,7 +1500,7 @@ struct rtl8xxxu_fileops {
u16 trxff_boundary; u16 trxff_boundary;
u8 pbp_rx; u8 pbp_rx;
u8 pbp_tx; u8 pbp_tx;
struct rtl8xxxu_reg8val *mactable; const struct rtl8xxxu_reg8val *mactable;
u8 total_page_num; u8 total_page_num;
u8 page_num_hi; u8 page_num_hi;
u8 page_num_lo; u8 page_num_lo;
@ -1457,7 +1509,7 @@ struct rtl8xxxu_fileops {
extern int rtl8xxxu_debug; extern int rtl8xxxu_debug;
extern struct rtl8xxxu_reg8val rtl8xxxu_gen1_mac_init_table[]; extern const struct rtl8xxxu_reg8val rtl8xxxu_gen1_mac_init_table[];
extern const u32 rtl8xxxu_iqk_phy_iq_bb_reg[]; extern const u32 rtl8xxxu_iqk_phy_iq_bb_reg[];
u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr); u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr);
u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr); u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr);
@ -1486,16 +1538,18 @@ void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv, bool iqk_ok,
void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv, bool iqk_ok, void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv, bool iqk_ok,
int result[][8], int candidate, bool tx_only); int result[][8], int candidate, bool tx_only);
int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv, int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv,
struct rtl8xxxu_rfregval *table, const struct rtl8xxxu_rfregval *table,
enum rtl8xxxu_rfpath path); enum rtl8xxxu_rfpath path);
int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv, int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,
struct rtl8xxxu_reg32val *array); const struct rtl8xxxu_reg32val *array);
int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name); int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name);
void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv); void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv);
void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv); void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv);
int rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data);
void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv); void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv);
int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv); int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv);
void rtl8xxxu_gen2_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start); void rtl8xxxu_gen2_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start);
void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv);
int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv); int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv);
int rtl8xxxu_gen2_h2c_cmd(struct rtl8xxxu_priv *priv, int rtl8xxxu_gen2_h2c_cmd(struct rtl8xxxu_priv *priv,
struct h2c_cmd *h2c, int len); struct h2c_cmd *h2c, int len);
@ -1539,7 +1593,9 @@ void rtl8xxxu_fill_txdesc_v2(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr,
u32 rts_rate); u32 rts_rate);
void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv, void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv,
u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5); u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5);
void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv);
extern struct rtl8xxxu_fileops rtl8188fu_fops;
extern struct rtl8xxxu_fileops rtl8192cu_fops; extern struct rtl8xxxu_fileops rtl8192cu_fops;
extern struct rtl8xxxu_fileops rtl8192eu_fops; extern struct rtl8xxxu_fileops rtl8192eu_fops;
extern struct rtl8xxxu_fileops rtl8723au_fops; extern struct rtl8xxxu_fileops rtl8723au_fops;

File diff suppressed because it is too large Load Diff

View File

@ -77,7 +77,7 @@ static struct rtl8xxxu_power_base rtl8188r_power_base = {
.reg_0868 = 0x00020204, .reg_0868 = 0x00020204,
}; };
static struct rtl8xxxu_rfregval rtl8192cu_radioa_2t_init_table[] = { static const struct rtl8xxxu_rfregval rtl8192cu_radioa_2t_init_table[] = {
{0x00, 0x00030159}, {0x01, 0x00031284}, {0x00, 0x00030159}, {0x01, 0x00031284},
{0x02, 0x00098000}, {0x03, 0x00018c63}, {0x02, 0x00098000}, {0x03, 0x00018c63},
{0x04, 0x000210e7}, {0x09, 0x0002044f}, {0x04, 0x000210e7}, {0x09, 0x0002044f},
@ -152,7 +152,7 @@ static struct rtl8xxxu_rfregval rtl8192cu_radioa_2t_init_table[] = {
{0xff, 0xffffffff} {0xff, 0xffffffff}
}; };
static struct rtl8xxxu_rfregval rtl8192cu_radiob_2t_init_table[] = { static const struct rtl8xxxu_rfregval rtl8192cu_radiob_2t_init_table[] = {
{0x00, 0x00030159}, {0x01, 0x00031284}, {0x00, 0x00030159}, {0x01, 0x00031284},
{0x02, 0x00098000}, {0x03, 0x00018c63}, {0x02, 0x00098000}, {0x03, 0x00018c63},
{0x04, 0x000210e7}, {0x09, 0x0002044f}, {0x04, 0x000210e7}, {0x09, 0x0002044f},
@ -176,7 +176,7 @@ static struct rtl8xxxu_rfregval rtl8192cu_radiob_2t_init_table[] = {
{0xff, 0xffffffff} {0xff, 0xffffffff}
}; };
static struct rtl8xxxu_rfregval rtl8192cu_radioa_1t_init_table[] = { static const struct rtl8xxxu_rfregval rtl8192cu_radioa_1t_init_table[] = {
{0x00, 0x00030159}, {0x01, 0x00031284}, {0x00, 0x00030159}, {0x01, 0x00031284},
{0x02, 0x00098000}, {0x03, 0x00018c63}, {0x02, 0x00098000}, {0x03, 0x00018c63},
{0x04, 0x000210e7}, {0x09, 0x0002044f}, {0x04, 0x000210e7}, {0x09, 0x0002044f},
@ -251,7 +251,7 @@ static struct rtl8xxxu_rfregval rtl8192cu_radioa_1t_init_table[] = {
{0xff, 0xffffffff} {0xff, 0xffffffff}
}; };
static struct rtl8xxxu_rfregval rtl8188ru_radioa_1t_highpa_table[] = { static const struct rtl8xxxu_rfregval rtl8188ru_radioa_1t_highpa_table[] = {
{0x00, 0x00030159}, {0x01, 0x00031284}, {0x00, 0x00030159}, {0x01, 0x00031284},
{0x02, 0x00098000}, {0x03, 0x00018c63}, {0x02, 0x00098000}, {0x03, 0x00018c63},
{0x04, 0x000210e7}, {0x09, 0x0002044f}, {0x04, 0x000210e7}, {0x09, 0x0002044f},
@ -413,7 +413,7 @@ static int rtl8192cu_parse_efuse(struct rtl8xxxu_priv *priv)
static int rtl8192cu_init_phy_rf(struct rtl8xxxu_priv *priv) static int rtl8192cu_init_phy_rf(struct rtl8xxxu_priv *priv)
{ {
struct rtl8xxxu_rfregval *rftable; const struct rtl8xxxu_rfregval *rftable;
int ret; int ret;
if (priv->rtl_chip == RTL8188R) { if (priv->rtl_chip == RTL8188R) {
@ -549,6 +549,7 @@ struct rtl8xxxu_fileops rtl8192cu_fops = {
.llt_init = rtl8xxxu_init_llt_table, .llt_init = rtl8xxxu_init_llt_table,
.init_phy_bb = rtl8xxxu_gen1_init_phy_bb, .init_phy_bb = rtl8xxxu_gen1_init_phy_bb,
.init_phy_rf = rtl8192cu_init_phy_rf, .init_phy_rf = rtl8192cu_init_phy_rf,
.phy_lc_calibrate = rtl8723a_phy_lc_calibrate,
.phy_iq_calibrate = rtl8xxxu_gen1_phy_iq_calibrate, .phy_iq_calibrate = rtl8xxxu_gen1_phy_iq_calibrate,
.config_channel = rtl8xxxu_gen1_config_channel, .config_channel = rtl8xxxu_gen1_config_channel,
.parse_rx_desc = rtl8xxxu_parse_rxdesc16, .parse_rx_desc = rtl8xxxu_parse_rxdesc16,

View File

@ -32,7 +32,7 @@
#include "rtl8xxxu.h" #include "rtl8xxxu.h"
#include "rtl8xxxu_regs.h" #include "rtl8xxxu_regs.h"
static struct rtl8xxxu_reg8val rtl8192e_mac_init_table[] = { static const struct rtl8xxxu_reg8val rtl8192e_mac_init_table[] = {
{0x011, 0xeb}, {0x012, 0x07}, {0x014, 0x75}, {0x303, 0xa7}, {0x011, 0xeb}, {0x012, 0x07}, {0x014, 0x75}, {0x303, 0xa7},
{0x428, 0x0a}, {0x429, 0x10}, {0x430, 0x00}, {0x431, 0x00}, {0x428, 0x0a}, {0x429, 0x10}, {0x430, 0x00}, {0x431, 0x00},
{0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05}, {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
@ -62,7 +62,7 @@ static struct rtl8xxxu_reg8val rtl8192e_mac_init_table[] = {
{0xffff, 0xff}, {0xffff, 0xff},
}; };
static struct rtl8xxxu_reg32val rtl8192eu_phy_init_table[] = { static const struct rtl8xxxu_reg32val rtl8192eu_phy_init_table[] = {
{0x800, 0x80040000}, {0x804, 0x00000003}, {0x800, 0x80040000}, {0x804, 0x00000003},
{0x808, 0x0000fc00}, {0x80c, 0x0000000a}, {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
{0x810, 0x10001331}, {0x814, 0x020c3d10}, {0x810, 0x10001331}, {0x814, 0x020c3d10},
@ -194,7 +194,7 @@ static struct rtl8xxxu_reg32val rtl8192eu_phy_init_table[] = {
{0xffff, 0xffffffff}, {0xffff, 0xffffffff},
}; };
static struct rtl8xxxu_reg32val rtl8xxx_agc_8192eu_std_table[] = { static const struct rtl8xxxu_reg32val rtl8xxx_agc_8192eu_std_table[] = {
{0xc78, 0xfb000001}, {0xc78, 0xfb010001}, {0xc78, 0xfb000001}, {0xc78, 0xfb010001},
{0xc78, 0xfb020001}, {0xc78, 0xfb030001}, {0xc78, 0xfb020001}, {0xc78, 0xfb030001},
{0xc78, 0xfb040001}, {0xc78, 0xfb050001}, {0xc78, 0xfb040001}, {0xc78, 0xfb050001},
@ -263,7 +263,7 @@ static struct rtl8xxxu_reg32val rtl8xxx_agc_8192eu_std_table[] = {
{0xffff, 0xffffffff} {0xffff, 0xffffffff}
}; };
static struct rtl8xxxu_reg32val rtl8xxx_agc_8192eu_highpa_table[] = { static const struct rtl8xxxu_reg32val rtl8xxx_agc_8192eu_highpa_table[] = {
{0xc78, 0xfa000001}, {0xc78, 0xf9010001}, {0xc78, 0xfa000001}, {0xc78, 0xf9010001},
{0xc78, 0xf8020001}, {0xc78, 0xf7030001}, {0xc78, 0xf8020001}, {0xc78, 0xf7030001},
{0xc78, 0xf6040001}, {0xc78, 0xf5050001}, {0xc78, 0xf6040001}, {0xc78, 0xf5050001},
@ -332,7 +332,7 @@ static struct rtl8xxxu_reg32val rtl8xxx_agc_8192eu_highpa_table[] = {
{0xffff, 0xffffffff} {0xffff, 0xffffffff}
}; };
static struct rtl8xxxu_rfregval rtl8192eu_radioa_init_table[] = { static const struct rtl8xxxu_rfregval rtl8192eu_radioa_init_table[] = {
{0x7f, 0x00000082}, {0x81, 0x0003fc00}, {0x7f, 0x00000082}, {0x81, 0x0003fc00},
{0x00, 0x00030000}, {0x08, 0x00008400}, {0x00, 0x00030000}, {0x08, 0x00008400},
{0x18, 0x00000407}, {0x19, 0x00000012}, {0x18, 0x00000407}, {0x19, 0x00000012},
@ -412,7 +412,7 @@ static struct rtl8xxxu_rfregval rtl8192eu_radioa_init_table[] = {
{0xff, 0xffffffff} {0xff, 0xffffffff}
}; };
static struct rtl8xxxu_rfregval rtl8192eu_radiob_init_table[] = { static const struct rtl8xxxu_rfregval rtl8192eu_radiob_init_table[] = {
{0x7f, 0x00000082}, {0x81, 0x0003fc00}, {0x7f, 0x00000082}, {0x81, 0x0003fc00},
{0x00, 0x00030000}, {0x08, 0x00008400}, {0x00, 0x00030000}, {0x08, 0x00008400},
{0x18, 0x00000407}, {0x19, 0x00000012}, {0x18, 0x00000407}, {0x19, 0x00000012},
@ -1680,6 +1680,7 @@ struct rtl8xxxu_fileops rtl8192eu_fops = {
.llt_init = rtl8xxxu_auto_llt_table, .llt_init = rtl8xxxu_auto_llt_table,
.init_phy_bb = rtl8192eu_init_phy_bb, .init_phy_bb = rtl8192eu_init_phy_bb,
.init_phy_rf = rtl8192eu_init_phy_rf, .init_phy_rf = rtl8192eu_init_phy_rf,
.phy_lc_calibrate = rtl8723a_phy_lc_calibrate,
.phy_iq_calibrate = rtl8192eu_phy_iq_calibrate, .phy_iq_calibrate = rtl8192eu_phy_iq_calibrate,
.config_channel = rtl8xxxu_gen2_config_channel, .config_channel = rtl8xxxu_gen2_config_channel,
.parse_rx_desc = rtl8xxxu_parse_rxdesc24, .parse_rx_desc = rtl8xxxu_parse_rxdesc24,

View File

@ -54,7 +54,7 @@ static struct rtl8xxxu_power_base rtl8723a_power_base = {
.reg_0868 = 0x02040608, .reg_0868 = 0x02040608,
}; };
static struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table[] = { static const struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table[] = {
{0x00, 0x00030159}, {0x01, 0x00031284}, {0x00, 0x00030159}, {0x01, 0x00031284},
{0x02, 0x00098000}, {0x03, 0x00039c63}, {0x02, 0x00098000}, {0x03, 0x00039c63},
{0x04, 0x000210e7}, {0x09, 0x0002044f}, {0x04, 0x000210e7}, {0x09, 0x0002044f},
@ -366,6 +366,7 @@ struct rtl8xxxu_fileops rtl8723au_fops = {
.llt_init = rtl8xxxu_init_llt_table, .llt_init = rtl8xxxu_init_llt_table,
.init_phy_bb = rtl8xxxu_gen1_init_phy_bb, .init_phy_bb = rtl8xxxu_gen1_init_phy_bb,
.init_phy_rf = rtl8723au_init_phy_rf, .init_phy_rf = rtl8723au_init_phy_rf,
.phy_lc_calibrate = rtl8723a_phy_lc_calibrate,
.phy_iq_calibrate = rtl8xxxu_gen1_phy_iq_calibrate, .phy_iq_calibrate = rtl8xxxu_gen1_phy_iq_calibrate,
.config_channel = rtl8xxxu_gen1_config_channel, .config_channel = rtl8xxxu_gen1_config_channel,
.parse_rx_desc = rtl8xxxu_parse_rxdesc16, .parse_rx_desc = rtl8xxxu_parse_rxdesc16,

View File

@ -32,7 +32,7 @@
#include "rtl8xxxu.h" #include "rtl8xxxu.h"
#include "rtl8xxxu_regs.h" #include "rtl8xxxu_regs.h"
static struct rtl8xxxu_reg8val rtl8723b_mac_init_table[] = { static const struct rtl8xxxu_reg8val rtl8723b_mac_init_table[] = {
{0x02f, 0x30}, {0x035, 0x00}, {0x039, 0x08}, {0x04e, 0xe0}, {0x02f, 0x30}, {0x035, 0x00}, {0x039, 0x08}, {0x04e, 0xe0},
{0x064, 0x00}, {0x067, 0x20}, {0x428, 0x0a}, {0x429, 0x10}, {0x064, 0x00}, {0x067, 0x20}, {0x428, 0x0a}, {0x429, 0x10},
{0x430, 0x00}, {0x431, 0x00}, {0x430, 0x00}, {0x431, 0x00},
@ -63,7 +63,7 @@ static struct rtl8xxxu_reg8val rtl8723b_mac_init_table[] = {
{0xffff, 0xff}, {0xffff, 0xff},
}; };
static struct rtl8xxxu_reg32val rtl8723b_phy_1t_init_table[] = { static const struct rtl8xxxu_reg32val rtl8723b_phy_1t_init_table[] = {
{0x800, 0x80040000}, {0x804, 0x00000003}, {0x800, 0x80040000}, {0x804, 0x00000003},
{0x808, 0x0000fc00}, {0x80c, 0x0000000a}, {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
{0x810, 0x10001331}, {0x814, 0x020c3d10}, {0x810, 0x10001331}, {0x814, 0x020c3d10},
@ -164,7 +164,7 @@ static struct rtl8xxxu_reg32val rtl8723b_phy_1t_init_table[] = {
{0xffff, 0xffffffff}, {0xffff, 0xffffffff},
}; };
static struct rtl8xxxu_reg32val rtl8xxx_agc_8723bu_table[] = { static const struct rtl8xxxu_reg32val rtl8xxx_agc_8723bu_table[] = {
{0xc78, 0xfd000001}, {0xc78, 0xfc010001}, {0xc78, 0xfd000001}, {0xc78, 0xfc010001},
{0xc78, 0xfb020001}, {0xc78, 0xfa030001}, {0xc78, 0xfb020001}, {0xc78, 0xfa030001},
{0xc78, 0xf9040001}, {0xc78, 0xf8050001}, {0xc78, 0xf9040001}, {0xc78, 0xf8050001},
@ -235,7 +235,7 @@ static struct rtl8xxxu_reg32val rtl8xxx_agc_8723bu_table[] = {
{0xffff, 0xffffffff} {0xffff, 0xffffffff}
}; };
static struct rtl8xxxu_rfregval rtl8723bu_radioa_1t_init_table[] = { static const struct rtl8xxxu_rfregval rtl8723bu_radioa_1t_init_table[] = {
{0x00, 0x00010000}, {0xb0, 0x000dffe0}, {0x00, 0x00010000}, {0xb0, 0x000dffe0},
{0xfe, 0x00000000}, {0xfe, 0x00000000}, {0xfe, 0x00000000}, {0xfe, 0x00000000},
{0xfe, 0x00000000}, {0xb1, 0x00000018}, {0xfe, 0x00000000}, {0xb1, 0x00000018},
@ -518,7 +518,7 @@ static int rtl8723bu_init_phy_rf(struct rtl8xxxu_priv *priv)
return ret; return ret;
} }
static void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv) void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv)
{ {
u32 val32; u32 val32;
@ -1650,6 +1650,7 @@ struct rtl8xxxu_fileops rtl8723bu_fops = {
.init_phy_bb = rtl8723bu_init_phy_bb, .init_phy_bb = rtl8723bu_init_phy_bb,
.init_phy_rf = rtl8723bu_init_phy_rf, .init_phy_rf = rtl8723bu_init_phy_rf,
.phy_init_antenna_selection = rtl8723bu_phy_init_antenna_selection, .phy_init_antenna_selection = rtl8723bu_phy_init_antenna_selection,
.phy_lc_calibrate = rtl8723a_phy_lc_calibrate,
.phy_iq_calibrate = rtl8723bu_phy_iq_calibrate, .phy_iq_calibrate = rtl8723bu_phy_iq_calibrate,
.config_channel = rtl8xxxu_gen2_config_channel, .config_channel = rtl8xxxu_gen2_config_channel,
.parse_rx_desc = rtl8xxxu_parse_rxdesc24, .parse_rx_desc = rtl8xxxu_parse_rxdesc24,

View File

@ -52,6 +52,7 @@ MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin");
MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin"); MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin");
MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin"); MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin");
MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin"); MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin");
MODULE_FIRMWARE("rtlwifi/rtl8188fufw.bin");
module_param_named(debug, rtl8xxxu_debug, int, 0600); module_param_named(debug, rtl8xxxu_debug, int, 0600);
MODULE_PARM_DESC(debug, "Set debug mask"); MODULE_PARM_DESC(debug, "Set debug mask");
@ -127,7 +128,7 @@ static struct ieee80211_supported_band rtl8xxxu_supported_band = {
.n_bitrates = ARRAY_SIZE(rtl8xxxu_rates), .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates),
}; };
struct rtl8xxxu_reg8val rtl8xxxu_gen1_mac_init_table[] = { const struct rtl8xxxu_reg8val rtl8xxxu_gen1_mac_init_table[] = {
{0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00}, {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00},
{0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05}, {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
{0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00}, {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00},
@ -152,7 +153,7 @@ struct rtl8xxxu_reg8val rtl8xxxu_gen1_mac_init_table[] = {
{0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff}, {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff},
}; };
static struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = { static const struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = {
{0x800, 0x80040000}, {0x804, 0x00000003}, {0x800, 0x80040000}, {0x804, 0x00000003},
{0x808, 0x0000fc00}, {0x80c, 0x0000000a}, {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
{0x810, 0x10001331}, {0x814, 0x020c3d10}, {0x810, 0x10001331}, {0x814, 0x020c3d10},
@ -250,7 +251,7 @@ static struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = {
{0xffff, 0xffffffff}, {0xffff, 0xffffffff},
}; };
static struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = { static const struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = {
{0x024, 0x0011800f}, {0x028, 0x00ffdb83}, {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
{0x800, 0x80040002}, {0x804, 0x00000003}, {0x800, 0x80040002}, {0x804, 0x00000003},
{0x808, 0x0000fc00}, {0x80c, 0x0000000a}, {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
@ -348,7 +349,7 @@ static struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = {
{0xffff, 0xffffffff}, {0xffff, 0xffffffff},
}; };
static struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = { static const struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = {
{0x024, 0x0011800f}, {0x028, 0x00ffdb83}, {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
{0x040, 0x000c0004}, {0x800, 0x80040000}, {0x040, 0x000c0004}, {0x800, 0x80040000},
{0x804, 0x00000001}, {0x808, 0x0000fc00}, {0x804, 0x00000001}, {0x808, 0x0000fc00},
@ -447,7 +448,7 @@ static struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = {
{0xffff, 0xffffffff}, {0xffff, 0xffffffff},
}; };
static struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = { static const struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = {
{0xc78, 0x7b000001}, {0xc78, 0x7b010001}, {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
{0xc78, 0x7b020001}, {0xc78, 0x7b030001}, {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
{0xc78, 0x7b040001}, {0xc78, 0x7b050001}, {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
@ -531,7 +532,7 @@ static struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = {
{0xffff, 0xffffffff} {0xffff, 0xffffffff}
}; };
static struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = { static const struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = {
{0xc78, 0x7b000001}, {0xc78, 0x7b010001}, {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
{0xc78, 0x7b020001}, {0xc78, 0x7b030001}, {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
{0xc78, 0x7b040001}, {0xc78, 0x7b050001}, {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
@ -615,7 +616,7 @@ static struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = {
{0xffff, 0xffffffff} {0xffff, 0xffffffff}
}; };
static struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = { static const struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = {
{ /* RF_A */ { /* RF_A */
.hssiparm1 = REG_FPGA0_XA_HSSI_PARM1, .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1,
.hssiparm2 = REG_FPGA0_XA_HSSI_PARM2, .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2,
@ -1606,20 +1607,32 @@ static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv)
static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv) static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv)
{ {
const struct usb_device_descriptor *descriptor = &priv->udev->descriptor;
struct device *dev = &priv->udev->dev; struct device *dev = &priv->udev->dev;
struct ieee80211_hw *hw = priv->hw; struct ieee80211_hw *hw = priv->hw;
u32 val32, bonding; u32 val32, bonding, sys_cfg;
u16 val16; u16 val16;
val32 = rtl8xxxu_read32(priv, REG_SYS_CFG); sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG);
priv->chip_cut = (val32 & SYS_CFG_CHIP_VERSION_MASK) >> priv->chip_cut = (sys_cfg & SYS_CFG_CHIP_VERSION_MASK) >>
SYS_CFG_CHIP_VERSION_SHIFT; SYS_CFG_CHIP_VERSION_SHIFT;
if (val32 & SYS_CFG_TRP_VAUX_EN) { if (sys_cfg & SYS_CFG_TRP_VAUX_EN) {
dev_info(dev, "Unsupported test chip\n"); dev_info(dev, "Unsupported test chip\n");
return -ENOTSUPP; return -ENOTSUPP;
} }
if (val32 & SYS_CFG_BT_FUNC) { if (descriptor->idVendor == USB_VENDOR_ID_REALTEK &&
descriptor->idProduct == 0xf179) {
sprintf(priv->chip_name, "8188FU");
priv->rtl_chip = RTL8188F;
priv->rf_paths = 1;
priv->rx_paths = 1;
priv->tx_paths = 1;
priv->has_wifi = 1;
goto skip_complicated_chip_detection;
}
if (sys_cfg & SYS_CFG_BT_FUNC) {
if (priv->chip_cut >= 3) { if (priv->chip_cut >= 3) {
sprintf(priv->chip_name, "8723BU"); sprintf(priv->chip_name, "8723BU");
priv->rtl_chip = RTL8723B; priv->rtl_chip = RTL8723B;
@ -1641,7 +1654,7 @@ static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv)
if (val32 & MULTI_GPS_FUNC_EN) if (val32 & MULTI_GPS_FUNC_EN)
priv->has_gps = 1; priv->has_gps = 1;
priv->is_multi_func = 1; priv->is_multi_func = 1;
} else if (val32 & SYS_CFG_TYPE_ID) { } else if (sys_cfg & SYS_CFG_TYPE_ID) {
bonding = rtl8xxxu_read32(priv, REG_HPON_FSM); bonding = rtl8xxxu_read32(priv, REG_HPON_FSM);
bonding &= HPON_FSM_BONDING_MASK; bonding &= HPON_FSM_BONDING_MASK;
if (priv->fops->tx_desc_size == if (priv->fops->tx_desc_size ==
@ -1685,14 +1698,17 @@ static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv)
priv->has_wifi = 1; priv->has_wifi = 1;
} }
skip_complicated_chip_detection:
hw->wiphy->available_antennas_tx = BIT(priv->tx_paths) - 1; hw->wiphy->available_antennas_tx = BIT(priv->tx_paths) - 1;
hw->wiphy->available_antennas_rx = BIT(priv->rx_paths) - 1; hw->wiphy->available_antennas_rx = BIT(priv->rx_paths) - 1;
switch (priv->rtl_chip) { switch (priv->rtl_chip) {
case RTL8188E: case RTL8188E:
case RTL8188F:
case RTL8192E: case RTL8192E:
case RTL8723B: case RTL8723B:
switch (val32 & SYS_CFG_VENDOR_EXT_MASK) { switch (sys_cfg & SYS_CFG_VENDOR_EXT_MASK) {
case SYS_CFG_VENDOR_ID_TSMC: case SYS_CFG_VENDOR_ID_TSMC:
sprintf(priv->chip_vendor, "TSMC"); sprintf(priv->chip_vendor, "TSMC");
break; break;
@ -1709,7 +1725,7 @@ static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv)
} }
break; break;
default: default:
if (val32 & SYS_CFG_VENDOR_ID) { if (sys_cfg & SYS_CFG_VENDOR_ID) {
sprintf(priv->chip_vendor, "UMC"); sprintf(priv->chip_vendor, "UMC");
priv->vendor_umc = 1; priv->vendor_umc = 1;
} else { } else {
@ -1720,7 +1736,18 @@ static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv)
val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS); val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS);
priv->rom_rev = (val32 & GPIO_RF_RL_ID) >> 28; priv->rom_rev = (val32 & GPIO_RF_RL_ID) >> 28;
val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX); /*
* 8188FU vendor driver doesn't use REG_NORMAL_SIE_EP_TX,
* it just decides the queue mapping based on nr_out_eps.
* However, reading the register returns "0x321" which
* results in a wrong ep_tx_count of 3 and most frames
* not being transmitted.
*/
if (priv->rtl_chip == RTL8188F)
val16 = 0;
else
val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX);
if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) { if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) {
priv->ep_tx_high_queue = 1; priv->ep_tx_high_queue = 1;
priv->ep_tx_count++; priv->ep_tx_count++;
@ -1763,7 +1790,7 @@ static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv)
return 0; return 0;
} }
static int int
rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data) rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data)
{ {
int i; int i;
@ -1979,7 +2006,7 @@ static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv)
/* /*
* Init H2C command * Init H2C command
*/ */
if (priv->rtl_chip == RTL8723B) if (priv->rtl_chip == RTL8723B || priv->rtl_chip == RTL8188F)
rtl8xxxu_write8(priv, REG_HMTFR, 0x0f); rtl8xxxu_write8(priv, REG_HMTFR, 0x0f);
exit: exit:
return ret; return ret;
@ -2099,6 +2126,7 @@ int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name)
case 0x88c0: case 0x88c0:
case 0x5300: case 0x5300:
case 0x2300: case 0x2300:
case 0x88f0:
break; break;
default: default:
ret = -EINVAL; ret = -EINVAL;
@ -2145,7 +2173,7 @@ void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv)
static int static int
rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv) rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv)
{ {
struct rtl8xxxu_reg8val *array = priv->fops->mactable; const struct rtl8xxxu_reg8val *array = priv->fops->mactable;
int i, ret; int i, ret;
u16 reg; u16 reg;
u8 val; u8 val;
@ -2166,14 +2194,16 @@ rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv)
} }
} }
if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E) if (priv->rtl_chip != RTL8723B &&
priv->rtl_chip != RTL8192E &&
priv->rtl_chip != RTL8188F)
rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a); rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a);
return 0; return 0;
} }
int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv, int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,
struct rtl8xxxu_reg32val *array) const struct rtl8xxxu_reg32val *array)
{ {
int i, ret; int i, ret;
u16 reg; u16 reg;
@ -2338,7 +2368,7 @@ static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv)
} }
static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv, static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv,
struct rtl8xxxu_rfregval *array, const struct rtl8xxxu_rfregval *array,
enum rtl8xxxu_rfpath path) enum rtl8xxxu_rfpath path)
{ {
int i, ret; int i, ret;
@ -2386,7 +2416,7 @@ static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv,
} }
int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv, int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv,
struct rtl8xxxu_rfregval *table, const struct rtl8xxxu_rfregval *table,
enum rtl8xxxu_rfpath path) enum rtl8xxxu_rfpath path)
{ {
u32 val32; u32 val32;
@ -3427,7 +3457,7 @@ void rtl8xxxu_gen1_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
priv->bb_recovery_backup, RTL8XXXU_BB_REGS); priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
} }
static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv) void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv)
{ {
u32 val32; u32 val32;
u32 rf_amode, rf_bmode = 0, lstf; u32 rf_amode, rf_bmode = 0, lstf;
@ -4031,6 +4061,9 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
if (priv->rtl_chip == RTL8192E) { if (priv->rtl_chip == RTL8192E) {
rtl8xxxu_write32(priv, REG_HIMR0, 0x00); rtl8xxxu_write32(priv, REG_HIMR0, 0x00);
rtl8xxxu_write32(priv, REG_HIMR1, 0x00); rtl8xxxu_write32(priv, REG_HIMR1, 0x00);
} else if (priv->rtl_chip == RTL8188F) {
rtl8xxxu_write32(priv, REG_HISR0, 0xffffffff);
rtl8xxxu_write32(priv, REG_HISR1, 0xffffffff);
} else { } else {
/* /*
* Enable all interrupts - not obvious USB needs to do this * Enable all interrupts - not obvious USB needs to do this
@ -4050,11 +4083,25 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC; RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC;
rtl8xxxu_write32(priv, REG_RCR, val32); rtl8xxxu_write32(priv, REG_RCR, val32);
/* if (priv->rtl_chip == RTL8188F) {
* Accept all multicast /* Accept all data frames */
*/ rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);
rtl8xxxu_write32(priv, REG_MAR, 0xffffffff);
rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff); /*
* Since ADF is removed from RCR, ps-poll will not be indicate to driver,
* RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll.
*/
rtl8xxxu_write16(priv, REG_RXFLTMAP1, 0x400);
/* Accept all management frames */
rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);
} else {
/*
* Accept all multicast
*/
rtl8xxxu_write32(priv, REG_MAR, 0xffffffff);
rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff);
}
/* /*
* Init adaptive controls * Init adaptive controls
@ -4105,14 +4152,17 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8); val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8);
rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16); rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16);
rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404); rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404);
rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME); if (priv->rtl_chip != RTL8188F)
/* Firmware will control REG_DRVERLYINT when power saving is enable, */
/* so don't set this register on STA mode. */
rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME);
rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME); rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME);
rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F); rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F);
/* /*
* Initialize burst parameters * Initialize burst parameters
*/ */
if (priv->rtl_chip == RTL8723B) { if (priv->rtl_chip == RTL8723B || priv->rtl_chip == RTL8188F) {
/* /*
* For USB high speed set 512B packets * For USB high speed set 512B packets
*/ */
@ -4130,13 +4180,26 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
rtl8xxxu_write8(priv, REG_HT_SINGLE_AMPDU_8723B, val8); rtl8xxxu_write8(priv, REG_HT_SINGLE_AMPDU_8723B, val8);
rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, 0x0c14); rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, 0x0c14);
rtl8xxxu_write8(priv, REG_AMPDU_MAX_TIME_8723B, 0x5e); if (priv->rtl_chip == RTL8723B)
val8 = 0x5e;
else if (priv->rtl_chip == RTL8188F)
val8 = 0x70; /* 0x5e would make it very slow */
rtl8xxxu_write8(priv, REG_AMPDU_MAX_TIME_8723B, val8);
rtl8xxxu_write32(priv, REG_AGGLEN_LMT, 0xffffffff); rtl8xxxu_write32(priv, REG_AGGLEN_LMT, 0xffffffff);
rtl8xxxu_write8(priv, REG_RX_PKT_LIMIT, 0x18); rtl8xxxu_write8(priv, REG_RX_PKT_LIMIT, 0x18);
rtl8xxxu_write8(priv, REG_PIFS, 0x00); rtl8xxxu_write8(priv, REG_PIFS, 0x00);
rtl8xxxu_write8(priv, REG_USTIME_TSF_8723B, 0x50); if (priv->rtl_chip == RTL8188F) {
rtl8xxxu_write8(priv, REG_USTIME_EDCA, 0x50); rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, FWHW_TXQ_CTRL_AMPDU_RETRY);
rtl8xxxu_write32(priv, REG_FAST_EDCA_CTRL, 0x03086666);
}
if (priv->rtl_chip == RTL8723B)
val8 = 0x50;
else if (priv->rtl_chip == RTL8188F)
val8 = 0x28; /* 0x50 would make the upload slow */
rtl8xxxu_write8(priv, REG_USTIME_TSF_8723B, val8);
rtl8xxxu_write8(priv, REG_USTIME_EDCA, val8);
/* to prevent mac is reseted by bus. */
val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL); val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);
val8 |= BIT(5) | BIT(6); val8 |= BIT(5) | BIT(6);
rtl8xxxu_write8(priv, REG_RSV_CTRL, val8); rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
@ -4145,6 +4208,11 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
if (fops->init_aggregation) if (fops->init_aggregation)
fops->init_aggregation(priv); fops->init_aggregation(priv);
if (priv->rtl_chip == RTL8188F) {
rtl8xxxu_write16(priv, REG_PKT_VO_VI_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */
rtl8xxxu_write16(priv, REG_PKT_BE_BK_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */
}
/* /*
* Enable CCK and OFDM block * Enable CCK and OFDM block
*/ */
@ -4163,7 +4231,7 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
fops->set_tx_power(priv, 1, false); fops->set_tx_power(priv, 1, false);
/* Let the 8051 take control of antenna setting */ /* Let the 8051 take control of antenna setting */
if (priv->rtl_chip != RTL8192E) { if (priv->rtl_chip != RTL8192E && priv->rtl_chip != RTL8188F) {
val8 = rtl8xxxu_read8(priv, REG_LEDCFG2); val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
val8 |= LEDCFG2_DPDT_SELECT; val8 |= LEDCFG2_DPDT_SELECT;
rtl8xxxu_write8(priv, REG_LEDCFG2, val8); rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
@ -4174,7 +4242,8 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
/* Disable BAR - not sure if this has any effect on USB */ /* Disable BAR - not sure if this has any effect on USB */
rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff); rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff);
rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0); if (priv->rtl_chip != RTL8188F)
rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0);
if (fops->init_statistics) if (fops->init_statistics)
fops->init_statistics(priv); fops->init_statistics(priv);
@ -4191,20 +4260,38 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
* Reset USB mode switch setting * Reset USB mode switch setting
*/ */
rtl8xxxu_write8(priv, REG_ACLK_MON, 0x00); rtl8xxxu_write8(priv, REG_ACLK_MON, 0x00);
} else if (priv->rtl_chip == RTL8188F) {
/*
* Init GPIO settings for 8188f
*/
val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG);
val8 &= ~GPIO_MUXCFG_IO_SEL_ENBT;
rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8);
} }
rtl8723a_phy_lc_calibrate(priv); if (priv->rtl_chip == RTL8188F)
/* CCK PD */
rtl8xxxu_write8(priv, REG_CCK_PD_THRESH, CCK_PD_TYPE1_LV1_TH);
fops->phy_lc_calibrate(priv);
fops->phy_iq_calibrate(priv); fops->phy_iq_calibrate(priv);
/* /*
* This should enable thermal meter * This should enable thermal meter
*/ */
if (fops->gen2_thermal_meter) if (fops->gen2_thermal_meter) {
rtl8xxxu_write_rfreg(priv, if (priv->rtl_chip == RTL8188F) {
RF_A, RF6052_REG_T_METER_8723B, 0x37cf8); val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_T_METER_8723B);
else val32 |= 0x30000;
rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER_8723B, val32);
} else {
rtl8xxxu_write_rfreg(priv,
RF_A, RF6052_REG_T_METER_8723B, 0x37cf8);
}
} else {
rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60); rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60);
}
/* Set NAV_UPPER to 30000us */ /* Set NAV_UPPER to 30000us */
val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT); val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT);
@ -4389,12 +4476,9 @@ void rtl8xxxu_gen1_report_connect(struct rtl8xxxu_priv *priv,
void rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv *priv, void rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv *priv,
u8 macid, bool connect) u8 macid, bool connect)
{ {
#ifdef RTL8XXXU_GEN2_REPORT_CONNECT
/* /*
* Barry Day reports this causes issues with 8192eu and 8723bu * The firmware turns on the rate control when it knows it's
* devices reconnecting. The reason for this is unclear, but * connected to a network.
* until it is better understood, leave the code in place but
* disabled, so it is not lost.
*/ */
struct h2c_cmd h2c; struct h2c_cmd h2c;
@ -4407,7 +4491,6 @@ void rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv *priv,
h2c.media_status_rpt.parm &= ~BIT(0); h2c.media_status_rpt.parm &= ~BIT(0);
rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.media_status_rpt)); rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.media_status_rpt));
#endif
} }
void rtl8xxxu_gen1_init_aggregation(struct rtl8xxxu_priv *priv) void rtl8xxxu_gen1_init_aggregation(struct rtl8xxxu_priv *priv)
@ -6561,6 +6644,7 @@ static void rtl8xxxu_stop(struct ieee80211_hw *hw)
static const struct ieee80211_ops rtl8xxxu_ops = { static const struct ieee80211_ops rtl8xxxu_ops = {
.tx = rtl8xxxu_tx, .tx = rtl8xxxu_tx,
.wake_tx_queue = ieee80211_handle_wake_tx_queue,
.add_interface = rtl8xxxu_add_interface, .add_interface = rtl8xxxu_add_interface,
.remove_interface = rtl8xxxu_remove_interface, .remove_interface = rtl8xxxu_remove_interface,
.config = rtl8xxxu_config, .config = rtl8xxxu_config,
@ -6674,6 +6758,7 @@ static int rtl8xxxu_probe(struct usb_interface *interface,
case 0x8178: case 0x8178:
case 0x817f: case 0x817f:
case 0x818b: case 0x818b:
case 0xf179:
untested = 0; untested = 0;
break; break;
} }
@ -6886,6 +6971,9 @@ static const struct usb_device_id dev_table[] = {
.driver_info = (unsigned long)&rtl8723bu_fops}, .driver_info = (unsigned long)&rtl8723bu_fops},
{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xa611, 0xff, 0xff, 0xff), {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xa611, 0xff, 0xff, 0xff),
.driver_info = (unsigned long)&rtl8723bu_fops}, .driver_info = (unsigned long)&rtl8723bu_fops},
/* RTL8188FU */
{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xf179, 0xff, 0xff, 0xff),
.driver_info = (unsigned long)&rtl8188fu_fops},
#ifdef CONFIG_RTL8XXXU_UNTESTED #ifdef CONFIG_RTL8XXXU_UNTESTED
/* Still supported by rtlwifi */ /* Still supported by rtlwifi */
{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff), {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff),

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@ -135,6 +135,7 @@
#define REG_CAL_TIMER 0x003c #define REG_CAL_TIMER 0x003c
#define REG_ACLK_MON 0x003e #define REG_ACLK_MON 0x003e
#define REG_GPIO_MUXCFG 0x0040 #define REG_GPIO_MUXCFG 0x0040
#define GPIO_MUXCFG_IO_SEL_ENBT BIT(5)
#define REG_GPIO_IO_SEL 0x0042 #define REG_GPIO_IO_SEL 0x0042
#define REG_MAC_PINMUX_CFG 0x0043 #define REG_MAC_PINMUX_CFG 0x0043
#define REG_GPIO_PIN_CTRL 0x0044 #define REG_GPIO_PIN_CTRL 0x0044
@ -391,6 +392,7 @@
#define REG_CPWM 0x012f #define REG_CPWM 0x012f
#define REG_FWIMR 0x0130 #define REG_FWIMR 0x0130
#define REG_FWISR 0x0134 #define REG_FWISR 0x0134
#define REG_FTIMR 0x0138
#define REG_PKTBUF_DBG_CTRL 0x0140 #define REG_PKTBUF_DBG_CTRL 0x0140
#define REG_PKTBUF_DBG_DATA_L 0x0144 #define REG_PKTBUF_DBG_DATA_L 0x0144
#define REG_PKTBUF_DBG_DATA_H 0x0148 #define REG_PKTBUF_DBG_DATA_H 0x0148
@ -440,6 +442,9 @@
#define REG_FIFOPAGE 0x0204 #define REG_FIFOPAGE 0x0204
#define REG_TDECTRL 0x0208 #define REG_TDECTRL 0x0208
#define REG_DWBCN0_CTRL_8188F REG_TDECTRL
#define REG_TXDMA_OFFSET_CHK 0x020c #define REG_TXDMA_OFFSET_CHK 0x020c
#define TXDMA_OFFSET_DROP_DATA_EN BIT(9) #define TXDMA_OFFSET_DROP_DATA_EN BIT(9)
#define REG_TXDMA_STATUS 0x0210 #define REG_TXDMA_STATUS 0x0210
@ -925,6 +930,7 @@
#define REG_FPGA0_XA_LSSI_READBACK 0x08a0 /* Tranceiver LSSI Readback */ #define REG_FPGA0_XA_LSSI_READBACK 0x08a0 /* Tranceiver LSSI Readback */
#define REG_FPGA0_XB_LSSI_READBACK 0x08a4 #define REG_FPGA0_XB_LSSI_READBACK 0x08a4
#define REG_FPGA0_PSD_REPORT 0x08b4
#define REG_HSPI_XA_READBACK 0x08b8 /* Transceiver A HSPI read */ #define REG_HSPI_XA_READBACK 0x08b8 /* Transceiver A HSPI read */
#define REG_HSPI_XB_READBACK 0x08bc /* Transceiver B HSPI read */ #define REG_HSPI_XB_READBACK 0x08bc /* Transceiver B HSPI read */
@ -936,6 +942,7 @@
#define REG_RFE_PATH_SELECT 0x0940 /* 8723BU */ #define REG_RFE_PATH_SELECT 0x0940 /* 8723BU */
#define REG_RFE_BUFFER 0x0944 /* 8723BU */ #define REG_RFE_BUFFER 0x0944 /* 8723BU */
#define REG_S0S1_PATH_SWITCH 0x0948 /* 8723BU */ #define REG_S0S1_PATH_SWITCH 0x0948 /* 8723BU */
#define REG_OFDM_RX_DFIR 0x954
#define REG_CCK0_SYSTEM 0x0a00 #define REG_CCK0_SYSTEM 0x0a00
#define CCK0_SIDEBAND BIT(4) #define CCK0_SIDEBAND BIT(4)
@ -946,6 +953,13 @@
#define CCK0_AFE_RX_ANT_A 0 #define CCK0_AFE_RX_ANT_A 0
#define CCK0_AFE_RX_ANT_B (BIT(24) | BIT(26)) #define CCK0_AFE_RX_ANT_B (BIT(24) | BIT(26))
#define REG_CCK_PD_THRESH 0x0a0a
#define CCK_PD_TYPE1_LV0_TH 0x40
#define CCK_PD_TYPE1_LV1_TH 0x83
#define CCK_PD_TYPE1_LV2_TH 0xcd
#define CCK_PD_TYPE1_LV3_TH 0xdd
#define CCK_PD_TYPE1_LV4_TH 0xed
#define REG_CONFIG_ANT_A 0x0b68 #define REG_CONFIG_ANT_A 0x0b68
#define REG_CONFIG_ANT_B 0x0b6c #define REG_CONFIG_ANT_B 0x0b6c
@ -965,6 +979,7 @@
#define REG_OFDM0_FA_RSTC 0x0c0c #define REG_OFDM0_FA_RSTC 0x0c0c
#define REG_OFDM0_XA_RX_AFE 0x0c10
#define REG_OFDM0_XA_RX_IQ_IMBALANCE 0x0c14 #define REG_OFDM0_XA_RX_IQ_IMBALANCE 0x0c14
#define REG_OFDM0_XB_RX_IQ_IMBALANCE 0x0c1c #define REG_OFDM0_XB_RX_IQ_IMBALANCE 0x0c1c
@ -1011,6 +1026,9 @@
#define OFDM_LSTF_MASK 0x70000000 #define OFDM_LSTF_MASK 0x70000000
#define REG_OFDM1_TRX_PATH_ENABLE 0x0d04 #define REG_OFDM1_TRX_PATH_ENABLE 0x0d04
#define REG_OFDM1_CFO_TRACKING 0x0d2c
#define REG_OFDM1_CSI_FIX_MASK1 0x0d40
#define REG_OFDM1_CSI_FIX_MASK2 0x0d44
#define REG_TX_AGC_A_RATE18_06 0x0e00 #define REG_TX_AGC_A_RATE18_06 0x0e00
#define REG_TX_AGC_A_RATE54_24 0x0e04 #define REG_TX_AGC_A_RATE54_24 0x0e04
@ -1202,6 +1220,7 @@
#define RF6052_REG_UNKNOWN_43 0x43 #define RF6052_REG_UNKNOWN_43 0x43
#define RF6052_REG_UNKNOWN_55 0x55 #define RF6052_REG_UNKNOWN_55 0x55
#define RF6052_REG_UNKNOWN_56 0x56 #define RF6052_REG_UNKNOWN_56 0x56
#define RF6052_REG_RXG_MIX_SWBW 0x87
#define RF6052_REG_S0S1 0xb0 #define RF6052_REG_S0S1 0xb0
#define RF6052_REG_UNKNOWN_DF 0xdf #define RF6052_REG_UNKNOWN_DF 0xdf
#define RF6052_REG_UNKNOWN_ED 0xed #define RF6052_REG_UNKNOWN_ED 0xed

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@ -1912,6 +1912,7 @@ const struct ieee80211_ops rtl_ops = {
.start = rtl_op_start, .start = rtl_op_start,
.stop = rtl_op_stop, .stop = rtl_op_stop,
.tx = rtl_op_tx, .tx = rtl_op_tx,
.wake_tx_queue = ieee80211_handle_wake_tx_queue,
.add_interface = rtl_op_add_interface, .add_interface = rtl_op_add_interface,
.remove_interface = rtl_op_remove_interface, .remove_interface = rtl_op_remove_interface,
.change_interface = rtl_op_change_interface, .change_interface = rtl_op_change_interface,

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@ -19,6 +19,9 @@ config RTW89_PCI
config RTW89_8852A config RTW89_8852A
tristate tristate
config RTW89_8852B
tristate
config RTW89_8852C config RTW89_8852C
tristate tristate
@ -33,6 +36,17 @@ config RTW89_8852AE
802.11ax PCIe wireless network (Wi-Fi 6) adapter 802.11ax PCIe wireless network (Wi-Fi 6) adapter
config RTW89_8852BE
tristate "Realtek 8852BE PCI wireless network (Wi-Fi 6) adapter"
depends on PCI
select RTW89_CORE
select RTW89_PCI
select RTW89_8852B
help
Select this option will enable support for 8852BE chipset
802.11ax PCIe wireless network (Wi-Fi 6) adapter
config RTW89_8852CE config RTW89_8852CE
tristate "Realtek 8852CE PCI wireless network (Wi-Fi 6E) adapter" tristate "Realtek 8852CE PCI wireless network (Wi-Fi 6E) adapter"
depends on PCI depends on PCI

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@ -24,6 +24,15 @@ rtw89_8852a-objs := rtw8852a.o \
obj-$(CONFIG_RTW89_8852AE) += rtw89_8852ae.o obj-$(CONFIG_RTW89_8852AE) += rtw89_8852ae.o
rtw89_8852ae-objs := rtw8852ae.o rtw89_8852ae-objs := rtw8852ae.o
obj-$(CONFIG_RTW89_8852B) += rtw89_8852b.o
rtw89_8852b-objs := rtw8852b.o \
rtw8852b_table.o \
rtw8852b_rfk.o \
rtw8852b_rfk_table.o
obj-$(CONFIG_RTW89_8852BE) += rtw89_8852be.o
rtw89_8852be-objs := rtw8852be.o
obj-$(CONFIG_RTW89_8852C) += rtw89_8852c.o obj-$(CONFIG_RTW89_8852C) += rtw89_8852c.o
rtw89_8852c-objs := rtw8852c.o \ rtw89_8852c-objs := rtw8852c.o \
rtw8852c_table.o \ rtw8852c_table.o \

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@ -1809,13 +1809,18 @@ static void _set_rf_trx_para(struct rtw89_dev *rtwdev)
struct rtw89_btc_dm *dm = &btc->dm; struct rtw89_btc_dm *dm = &btc->dm;
struct rtw89_btc_wl_info *wl = &btc->cx.wl; struct rtw89_btc_wl_info *wl = &btc->cx.wl;
struct rtw89_btc_bt_info *bt = &btc->cx.bt; struct rtw89_btc_bt_info *bt = &btc->cx.bt;
struct rtw89_btc_bt_link_info *b = &bt->link_info;
struct rtw89_btc_rf_trx_para para; struct rtw89_btc_rf_trx_para para;
u32 wl_stb_chg = 0; u32 wl_stb_chg = 0;
u8 level_id = 0; u8 level_id = 0;
if (!dm->freerun) { if (!dm->freerun) {
dm->trx_para_level = 0; /* fix LNA2 = level-5 for BT ACI issue at BTG */
chip->ops->btc_bt_aci_imp(rtwdev); if ((btc->dm.wl_btg_rx && b->profile_cnt.now != 0) ||
dm->bt_only == 1)
dm->trx_para_level = 1;
else
dm->trx_para_level = 0;
} }
level_id = (u8)dm->trx_para_level; level_id = (u8)dm->trx_para_level;

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@ -1255,6 +1255,9 @@ static int rtw89_core_rx_parse_phy_sts(struct rtw89_dev *rtwdev,
if (phy_ppdu->ie < RTW89_CCK_PKT) if (phy_ppdu->ie < RTW89_CCK_PKT)
return -EINVAL; return -EINVAL;
if (!phy_ppdu->to_self)
return 0;
pos = (u8 *)phy_ppdu->buf + PHY_STS_HDR_LEN; pos = (u8 *)phy_ppdu->buf + PHY_STS_HDR_LEN;
end = (u8 *)phy_ppdu->buf + phy_ppdu->len; end = (u8 *)phy_ppdu->buf + phy_ppdu->len;
while (pos < end) { while (pos < end) {

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@ -84,6 +84,7 @@ enum rtw89_subband {
RTW89_CH_6G_BAND_IDX7, /* Ultra-high */ RTW89_CH_6G_BAND_IDX7, /* Ultra-high */
RTW89_SUBBAND_NR, RTW89_SUBBAND_NR,
RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1,
}; };
enum rtw89_gain_offset { enum rtw89_gain_offset {
@ -490,6 +491,8 @@ enum rtw89_bandwidth_section_num {
RTW89_BW80_SEC_NUM = 2, RTW89_BW80_SEC_NUM = 2,
}; };
#define RTW89_TXPWR_LMT_PAGE_SIZE 40
struct rtw89_txpwr_limit { struct rtw89_txpwr_limit {
s8 cck_20m[RTW89_BF_NUM]; s8 cck_20m[RTW89_BF_NUM];
s8 cck_40m[RTW89_BF_NUM]; s8 cck_40m[RTW89_BF_NUM];
@ -504,6 +507,8 @@ struct rtw89_txpwr_limit {
#define RTW89_RU_SEC_NUM 8 #define RTW89_RU_SEC_NUM 8
#define RTW89_TXPWR_LMT_RU_PAGE_SIZE 24
struct rtw89_txpwr_limit_ru { struct rtw89_txpwr_limit_ru {
s8 ru26[RTW89_RU_SEC_NUM]; s8 ru26[RTW89_RU_SEC_NUM];
s8 ru52[RTW89_RU_SEC_NUM]; s8 ru52[RTW89_RU_SEC_NUM];
@ -2192,6 +2197,7 @@ struct rtw89_sta {
struct rtw89_efuse { struct rtw89_efuse {
bool valid; bool valid;
bool power_k_valid;
u8 xtal_cap; u8 xtal_cap;
u8 addr[ETH_ALEN]; u8 addr[ETH_ALEN];
u8 rfe_type; u8 rfe_type;
@ -2357,7 +2363,6 @@ struct rtw89_chip_ops {
void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state);
void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val); void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val);
s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val);
void (*btc_bt_aci_imp)(struct rtw89_dev *rtwdev);
void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev);
void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state);
void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type); void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type);
@ -3044,6 +3049,7 @@ struct rtw89_dpk_bkup_para {
struct rtw89_dpk_info { struct rtw89_dpk_info {
bool is_dpk_enable; bool is_dpk_enable;
bool is_dpk_reload_en; bool is_dpk_reload_en;
u8 dpk_gs[RTW89_PHY_MAX];
u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
@ -3159,6 +3165,14 @@ struct rtw89_cfo_tracking_info {
u8 lock_cnt; u8 lock_cnt;
}; };
enum rtw89_tssi_alimk_band {
TSSI_ALIMK_2G = 0,
TSSI_ALIMK_5GL,
TSSI_ALIMK_5GM,
TSSI_ALIMK_5GH,
TSSI_ALIMK_MAX
};
/* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */
#define TSSI_TRIM_CH_GROUP_NUM 8 #define TSSI_TRIM_CH_GROUP_NUM 8
#define TSSI_TRIM_CH_GROUP_NUM_6G 16 #define TSSI_TRIM_CH_GROUP_NUM_6G 16
@ -3169,6 +3183,8 @@ struct rtw89_cfo_tracking_info {
#define TSSI_MCS_6G_CH_GROUP_NUM 32 #define TSSI_MCS_6G_CH_GROUP_NUM 32
#define TSSI_MCS_CH_GROUP_NUM \ #define TSSI_MCS_CH_GROUP_NUM \
(TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM) (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM)
#define TSSI_MAX_CH_NUM 67
#define TSSI_ALIMK_VALUE_NUM 8
struct rtw89_tssi_info { struct rtw89_tssi_info {
u8 thermal[RF_PATH_MAX]; u8 thermal[RF_PATH_MAX];
@ -3181,6 +3197,11 @@ struct rtw89_tssi_info {
bool tssi_tracking_check[RF_PATH_MAX]; bool tssi_tracking_check[RF_PATH_MAX];
u8 default_txagc_offset[RF_PATH_MAX]; u8 default_txagc_offset[RF_PATH_MAX];
u32 base_thermal[RF_PATH_MAX]; u32 base_thermal[RF_PATH_MAX];
bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM];
u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM];
u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM];
bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX];
u32 tssi_alimk_time;
}; };
struct rtw89_power_trim_info { struct rtw89_power_trim_info {
@ -3421,8 +3442,11 @@ struct rtw89_phy_bb_gain_info {
struct rtw89_phy_efuse_gain { struct rtw89_phy_efuse_gain {
bool offset_valid; bool offset_valid;
bool comp_valid;
s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */ s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */
s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */ s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */
s8 rssi_base[RTW89_PHY_MAX]; /* S(8, 4) */
s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */
}; };
struct rtw89_dev { struct rtw89_dev {

View File

@ -464,7 +464,7 @@ static const struct txpwr_map __txpwr_map_lmt_ru = {
}; };
static u8 __print_txpwr_ent(struct seq_file *m, const struct txpwr_ent *ent, static u8 __print_txpwr_ent(struct seq_file *m, const struct txpwr_ent *ent,
const u8 *buf, const u8 cur) const s8 *buf, const u8 cur)
{ {
char *fmt; char *fmt;
@ -493,8 +493,9 @@ static int __print_txpwr_map(struct seq_file *m, struct rtw89_dev *rtwdev,
const struct txpwr_map *map) const struct txpwr_map *map)
{ {
u8 fct = rtwdev->chip->txpwr_factor_mac; u8 fct = rtwdev->chip->txpwr_factor_mac;
u8 *buf, cur, i;
u32 val, addr; u32 val, addr;
s8 *buf, tmp;
u8 cur, i;
int ret; int ret;
buf = vzalloc(map->addr_to - map->addr_from + 4); buf = vzalloc(map->addr_to - map->addr_from + 4);
@ -507,8 +508,11 @@ static int __print_txpwr_map(struct seq_file *m, struct rtw89_dev *rtwdev,
val = MASKDWORD; val = MASKDWORD;
cur = addr - map->addr_from; cur = addr - map->addr_from;
for (i = 0; i < 4; i++, val >>= 8) for (i = 0; i < 4; i++, val >>= 8) {
buf[cur + i] = FIELD_GET(MASKBYTE0, val) >> fct; /* signed 7 bits, and reserved BIT(7) */
tmp = sign_extend32(val, 6);
buf[cur + i] = tmp >> fct;
}
} }
for (cur = 0, i = 0; i < map->size; i++) for (cur = 0, i = 0; i < map->size; i++)
@ -770,13 +774,34 @@ rtw89_debug_priv_mac_mem_dump_get(struct seq_file *m, void *v)
{ {
struct rtw89_debugfs_priv *debugfs_priv = m->private; struct rtw89_debugfs_priv *debugfs_priv = m->private;
struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
bool grant_read = false;
if (debugfs_priv->mac_mem.sel >= RTW89_MAC_MEM_NUM)
return -ENOENT;
if (rtwdev->chip->chip_id == RTL8852C) {
switch (debugfs_priv->mac_mem.sel) {
case RTW89_MAC_MEM_TXD_FIFO_0_V1:
case RTW89_MAC_MEM_TXD_FIFO_1_V1:
case RTW89_MAC_MEM_TXDATA_FIFO_0:
case RTW89_MAC_MEM_TXDATA_FIFO_1:
grant_read = true;
break;
default:
break;
}
}
mutex_lock(&rtwdev->mutex); mutex_lock(&rtwdev->mutex);
rtw89_leave_ps_mode(rtwdev); rtw89_leave_ps_mode(rtwdev);
if (grant_read)
rtw89_write32_set(rtwdev, R_AX_TCR1, B_AX_TCR_FORCE_READ_TXDFIFO);
rtw89_debug_dump_mac_mem(m, rtwdev, rtw89_debug_dump_mac_mem(m, rtwdev,
debugfs_priv->mac_mem.sel, debugfs_priv->mac_mem.sel,
debugfs_priv->mac_mem.start, debugfs_priv->mac_mem.start,
debugfs_priv->mac_mem.len); debugfs_priv->mac_mem.len);
if (grant_read)
rtw89_write32_clr(rtwdev, R_AX_TCR1, B_AX_TCR_FORCE_READ_TXDFIFO);
mutex_unlock(&rtwdev->mutex); mutex_unlock(&rtwdev->mutex);
return 0; return 0;

View File

@ -2565,6 +2565,9 @@ static void rtw89_hw_scan_add_chan(struct rtw89_dev *rtwdev, int chan_type,
struct rtw89_mac_chinfo *ch_info) struct rtw89_mac_chinfo *ch_info)
{ {
struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info; struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info;
struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif;
struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
struct cfg80211_scan_request *req = rtwvif->scan_req;
struct rtw89_pktofld_info *info; struct rtw89_pktofld_info *info;
u8 band, probe_count = 0; u8 band, probe_count = 0;
@ -2576,13 +2579,13 @@ static void rtw89_hw_scan_add_chan(struct rtw89_dev *rtwdev, int chan_type,
ch_info->tx_pwr_idx = 0; ch_info->tx_pwr_idx = 0;
ch_info->tx_null = false; ch_info->tx_null = false;
ch_info->pause_data = false; ch_info->pause_data = false;
ch_info->probe_id = RTW89_SCANOFLD_PKT_NONE;
if (ssid_num) { if (ssid_num) {
ch_info->num_pkt = ssid_num; ch_info->num_pkt = ssid_num;
band = rtw89_hw_to_nl80211_band(ch_info->ch_band); band = rtw89_hw_to_nl80211_band(ch_info->ch_band);
list_for_each_entry(info, &scan_info->pkt_list[band], list) { list_for_each_entry(info, &scan_info->pkt_list[band], list) {
ch_info->probe_id = info->id;
ch_info->pkt_id[probe_count] = info->id; ch_info->pkt_id[probe_count] = info->id;
if (++probe_count >= ssid_num) if (++probe_count >= ssid_num)
break; break;
@ -2591,9 +2594,16 @@ static void rtw89_hw_scan_add_chan(struct rtw89_dev *rtwdev, int chan_type,
rtw89_err(rtwdev, "SSID num differs from list len\n"); rtw89_err(rtwdev, "SSID num differs from list len\n");
} }
if (ch_info->ch_band == RTW89_BAND_6G) {
if (ssid_num == 1 && req->ssids[0].ssid_len == 0) {
ch_info->tx_pkt = false;
if (!req->duration_mandatory)
ch_info->period -= RTW89_DWELL_TIME;
}
}
switch (chan_type) { switch (chan_type) {
case RTW89_CHAN_OPERATE: case RTW89_CHAN_OPERATE:
ch_info->probe_id = RTW89_SCANOFLD_PKT_NONE;
ch_info->central_ch = scan_info->op_chan; ch_info->central_ch = scan_info->op_chan;
ch_info->pri_ch = scan_info->op_pri_ch; ch_info->pri_ch = scan_info->op_pri_ch;
ch_info->ch_band = scan_info->op_band; ch_info->ch_band = scan_info->op_band;
@ -2602,8 +2612,9 @@ static void rtw89_hw_scan_add_chan(struct rtw89_dev *rtwdev, int chan_type,
ch_info->num_pkt = 0; ch_info->num_pkt = 0;
break; break;
case RTW89_CHAN_DFS: case RTW89_CHAN_DFS:
ch_info->period = max_t(u8, ch_info->period, if (ch_info->ch_band != RTW89_BAND_6G)
RTW89_DFS_CHAN_TIME); ch_info->period = max_t(u8, ch_info->period,
RTW89_DFS_CHAN_TIME);
ch_info->dwell_time = RTW89_DWELL_TIME; ch_info->dwell_time = RTW89_DWELL_TIME;
break; break;
case RTW89_CHAN_ACTIVE: case RTW89_CHAN_ACTIVE:
@ -2637,8 +2648,13 @@ static int rtw89_hw_scan_add_chan_list(struct rtw89_dev *rtwdev,
goto out; goto out;
} }
ch_info->period = req->duration_mandatory ? if (req->duration_mandatory)
req->duration : RTW89_CHANNEL_TIME; ch_info->period = req->duration;
else if (channel->band == NL80211_BAND_6GHZ)
ch_info->period = RTW89_CHANNEL_TIME_6G + RTW89_DWELL_TIME;
else
ch_info->period = RTW89_CHANNEL_TIME;
ch_info->ch_band = rtw89_nl80211_to_hw_band(channel->band); ch_info->ch_band = rtw89_nl80211_to_hw_band(channel->band);
ch_info->central_ch = channel->hw_value; ch_info->central_ch = channel->hw_value;
ch_info->pri_ch = channel->hw_value; ch_info->pri_ch = channel->hw_value;
@ -2757,6 +2773,7 @@ void rtw89_hw_scan_complete(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
if (rtwvif->net_type != RTW89_NET_TYPE_NO_LINK) if (rtwvif->net_type != RTW89_NET_TYPE_NO_LINK)
rtw89_store_op_chan(rtwdev, false); rtw89_store_op_chan(rtwdev, false);
rtw89_set_channel(rtwdev);
} }
void rtw89_hw_scan_abort(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif) void rtw89_hw_scan_abort(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif)

View File

@ -197,6 +197,7 @@ struct rtw89_h2creg_sch_tx_en {
#define RTW89_H2C_MAX_SIZE 2048 #define RTW89_H2C_MAX_SIZE 2048
#define RTW89_CHANNEL_TIME 45 #define RTW89_CHANNEL_TIME 45
#define RTW89_CHANNEL_TIME_6G 20
#define RTW89_DFS_CHAN_TIME 105 #define RTW89_DFS_CHAN_TIME 105
#define RTW89_OFF_CHAN_TIME 100 #define RTW89_OFF_CHAN_TIME 100
#define RTW89_DWELL_TIME 20 #define RTW89_DWELL_TIME 20

View File

@ -31,6 +31,8 @@ const u32 rtw89_mac_mem_base_addrs[RTW89_MAC_MEM_NUM] = {
[RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR, [RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR,
[RTW89_MAC_MEM_CPU_LOCAL] = CPU_LOCAL_BASE_ADDR, [RTW89_MAC_MEM_CPU_LOCAL] = CPU_LOCAL_BASE_ADDR,
[RTW89_MAC_MEM_BSSID_CAM] = BSSID_CAM_BASE_ADDR, [RTW89_MAC_MEM_BSSID_CAM] = BSSID_CAM_BASE_ADDR,
[RTW89_MAC_MEM_TXD_FIFO_0_V1] = TXD_FIFO_0_BASE_ADDR_V1,
[RTW89_MAC_MEM_TXD_FIFO_1_V1] = TXD_FIFO_1_BASE_ADDR_V1,
}; };
static void rtw89_mac_mem_write(struct rtw89_dev *rtwdev, u32 offset, static void rtw89_mac_mem_write(struct rtw89_dev *rtwdev, u32 offset,
@ -4819,6 +4821,7 @@ int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val)
return 0; return 0;
} }
EXPORT_SYMBOL(rtw89_mac_read_xtal_si);
static static
void rtw89_mac_pkt_drop_sta(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta) void rtw89_mac_pkt_drop_sta(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta)

View File

@ -245,6 +245,8 @@ enum rtw89_mac_dbg_port_sel {
#define BCN_IE_CAM1_BASE_ADDR 0x188A0000 #define BCN_IE_CAM1_BASE_ADDR 0x188A0000
#define TXD_FIFO_0_BASE_ADDR 0x18856200 #define TXD_FIFO_0_BASE_ADDR 0x18856200
#define TXD_FIFO_1_BASE_ADDR 0x188A1080 #define TXD_FIFO_1_BASE_ADDR 0x188A1080
#define TXD_FIFO_0_BASE_ADDR_V1 0x18856400 /* for 8852C */
#define TXD_FIFO_1_BASE_ADDR_V1 0x188A1080 /* for 8852C */
#define TXDATA_FIFO_0_BASE_ADDR 0x18856000 #define TXDATA_FIFO_0_BASE_ADDR 0x18856000
#define TXDATA_FIFO_1_BASE_ADDR 0x188A1000 #define TXDATA_FIFO_1_BASE_ADDR 0x188A1000
#define CPU_LOCAL_BASE_ADDR 0x18003000 #define CPU_LOCAL_BASE_ADDR 0x18003000
@ -271,6 +273,8 @@ enum rtw89_mac_mem_sel {
RTW89_MAC_MEM_TXDATA_FIFO_1, RTW89_MAC_MEM_TXDATA_FIFO_1,
RTW89_MAC_MEM_CPU_LOCAL, RTW89_MAC_MEM_CPU_LOCAL,
RTW89_MAC_MEM_BSSID_CAM, RTW89_MAC_MEM_BSSID_CAM,
RTW89_MAC_MEM_TXD_FIFO_0_V1,
RTW89_MAC_MEM_TXD_FIFO_1_V1,
/* keep last */ /* keep last */
RTW89_MAC_MEM_NUM, RTW89_MAC_MEM_NUM,
@ -1010,6 +1014,7 @@ enum rtw89_mac_xtal_si_offset {
#define XTAL_SI_PON_EI BIT(1) #define XTAL_SI_PON_EI BIT(1)
#define XTAL_SI_PON_WEI BIT(0) #define XTAL_SI_PON_WEI BIT(0)
XTAL_SI_SRAM_CTRL = 0xA1, XTAL_SI_SRAM_CTRL = 0xA1,
#define XTAL_SI_SRAM_DIS BIT(1)
#define FULL_BIT_MASK GENMASK(7, 0) #define FULL_BIT_MASK GENMASK(7, 0)
}; };

View File

@ -1036,6 +1036,7 @@ static void rtw89_phy_config_bb_gain(struct rtw89_dev *rtwdev,
{ {
const struct rtw89_chip_info *chip = rtwdev->chip; const struct rtw89_chip_info *chip = rtwdev->chip;
union rtw89_phy_bb_gain_arg arg = { .addr = reg->addr }; union rtw89_phy_bb_gain_arg arg = { .addr = reg->addr };
struct rtw89_efuse *efuse = &rtwdev->efuse;
if (arg.gain_band >= RTW89_BB_GAIN_BAND_NR) if (arg.gain_band >= RTW89_BB_GAIN_BAND_NR)
return; return;
@ -1061,6 +1062,11 @@ static void rtw89_phy_config_bb_gain(struct rtw89_dev *rtwdev,
case 3: case 3:
rtw89_phy_cfg_bb_gain_op1db(rtwdev, arg, reg->data); rtw89_phy_cfg_bb_gain_op1db(rtwdev, arg, reg->data);
break; break;
case 4:
/* This cfg_type is only used by rfe_type >= 50 with eFEM */
if (efuse->rfe_type < 50)
break;
fallthrough;
default: default:
rtw89_warn(rtwdev, rtw89_warn(rtwdev,
"bb gain {0x%x:0x%x} with unknown cfg type: %d\n", "bb gain {0x%x:0x%x} with unknown cfg type: %d\n",
@ -1362,13 +1368,15 @@ static void rtw89_phy_init_rf_nctl(struct rtw89_dev *rtwdev)
int ret; int ret;
/* IQK/DPK clock & reset */ /* IQK/DPK clock & reset */
rtw89_phy_write32_set(rtwdev, 0x0c60, 0x3); rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x3);
rtw89_phy_write32_set(rtwdev, 0x0c6c, 0x1); rtw89_phy_write32_set(rtwdev, R_GNT_BT_WGT_EN, 0x1);
rtw89_phy_write32_set(rtwdev, 0x58ac, 0x8000000); rtw89_phy_write32_set(rtwdev, R_P0_PATH_RST, 0x8000000);
rtw89_phy_write32_set(rtwdev, 0x78ac, 0x8000000); rtw89_phy_write32_set(rtwdev, R_P1_PATH_RST, 0x8000000);
if (chip->chip_id == RTL8852B)
rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x2);
/* check 0x8080 */ /* check 0x8080 */
rtw89_phy_write32(rtwdev, 0x8000, 0x8); rtw89_phy_write32(rtwdev, R_NCTL_CFG, 0x8);
ret = read_poll_timeout(rtw89_phy_nctl_poll, val, val == 0x4, 10, ret = read_poll_timeout(rtw89_phy_nctl_poll, val, val == 0x4, 10,
1000, false, rtwdev); 1000, false, rtwdev);
@ -1419,6 +1427,15 @@ void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
} }
EXPORT_SYMBOL(rtw89_phy_write32_idx); EXPORT_SYMBOL(rtw89_phy_write32_idx);
u32 rtw89_phy_read32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
enum rtw89_phy_idx phy_idx)
{
if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1)
addr += rtw89_phy0_phy1_offset(rtwdev, addr);
return rtw89_phy_read32_mask(rtwdev, addr, mask);
}
EXPORT_SYMBOL(rtw89_phy_read32_idx);
void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask, void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
u32 val) u32 val)
{ {
@ -1443,23 +1460,21 @@ void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev,
} }
EXPORT_SYMBOL(rtw89_phy_write_reg3_tbl); EXPORT_SYMBOL(rtw89_phy_write_reg3_tbl);
const u8 rtw89_rs_idx_max[] = { static const u8 rtw89_rs_idx_max[] = {
[RTW89_RS_CCK] = RTW89_RATE_CCK_MAX, [RTW89_RS_CCK] = RTW89_RATE_CCK_MAX,
[RTW89_RS_OFDM] = RTW89_RATE_OFDM_MAX, [RTW89_RS_OFDM] = RTW89_RATE_OFDM_MAX,
[RTW89_RS_MCS] = RTW89_RATE_MCS_MAX, [RTW89_RS_MCS] = RTW89_RATE_MCS_MAX,
[RTW89_RS_HEDCM] = RTW89_RATE_HEDCM_MAX, [RTW89_RS_HEDCM] = RTW89_RATE_HEDCM_MAX,
[RTW89_RS_OFFSET] = RTW89_RATE_OFFSET_MAX, [RTW89_RS_OFFSET] = RTW89_RATE_OFFSET_MAX,
}; };
EXPORT_SYMBOL(rtw89_rs_idx_max);
const u8 rtw89_rs_nss_max[] = { static const u8 rtw89_rs_nss_max[] = {
[RTW89_RS_CCK] = 1, [RTW89_RS_CCK] = 1,
[RTW89_RS_OFDM] = 1, [RTW89_RS_OFDM] = 1,
[RTW89_RS_MCS] = RTW89_NSS_MAX, [RTW89_RS_MCS] = RTW89_NSS_MAX,
[RTW89_RS_HEDCM] = RTW89_NSS_HEDCM_MAX, [RTW89_RS_HEDCM] = RTW89_NSS_HEDCM_MAX,
[RTW89_RS_OFFSET] = 1, [RTW89_RS_OFFSET] = 1,
}; };
EXPORT_SYMBOL(rtw89_rs_nss_max);
static const u8 _byr_of_rs[] = { static const u8 _byr_of_rs[] = {
[RTW89_RS_CCK] = offsetof(struct rtw89_txpwr_byrate, cck), [RTW89_RS_CCK] = offsetof(struct rtw89_txpwr_byrate, cck),
@ -1501,6 +1516,7 @@ EXPORT_SYMBOL(rtw89_phy_load_txpwr_byrate);
(txpwr_rf) >> (__c->txpwr_factor_rf - __c->txpwr_factor_mac); \ (txpwr_rf) >> (__c->txpwr_factor_rf - __c->txpwr_factor_mac); \
}) })
static
s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band, s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band,
const struct rtw89_rate_desc *rate_desc) const struct rtw89_rate_desc *rate_desc)
{ {
@ -1523,7 +1539,6 @@ s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band,
return _phy_txpwr_rf_to_mac(rtwdev, byr[idx]); return _phy_txpwr_rf_to_mac(rtwdev, byr[idx]);
} }
EXPORT_SYMBOL(rtw89_phy_read_txpwr_byrate);
static u8 rtw89_channel_6g_to_idx(struct rtw89_dev *rtwdev, u8 channel_6g) static u8 rtw89_channel_6g_to_idx(struct rtw89_dev *rtwdev, u8 channel_6g)
{ {
@ -1783,6 +1798,7 @@ static void rtw89_phy_fill_txpwr_limit_160m(struct rtw89_dev *rtwdev,
lmt->mcs_40m_2p5[i] = min_t(s8, val_2p5_n[i], val_2p5_p[i]); lmt->mcs_40m_2p5[i] = min_t(s8, val_2p5_n[i], val_2p5_p[i]);
} }
static
void rtw89_phy_fill_txpwr_limit(struct rtw89_dev *rtwdev, void rtw89_phy_fill_txpwr_limit(struct rtw89_dev *rtwdev,
const struct rtw89_chan *chan, const struct rtw89_chan *chan,
struct rtw89_txpwr_limit *lmt, struct rtw89_txpwr_limit *lmt,
@ -1813,7 +1829,6 @@ void rtw89_phy_fill_txpwr_limit(struct rtw89_dev *rtwdev,
break; break;
} }
} }
EXPORT_SYMBOL(rtw89_phy_fill_txpwr_limit);
static s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band, static s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band,
u8 ru, u8 ntx, u8 ch) u8 ru, u8 ntx, u8 ch)
@ -1962,6 +1977,7 @@ rtw89_phy_fill_txpwr_limit_ru_160m(struct rtw89_dev *rtwdev,
} }
} }
static
void rtw89_phy_fill_txpwr_limit_ru(struct rtw89_dev *rtwdev, void rtw89_phy_fill_txpwr_limit_ru(struct rtw89_dev *rtwdev,
const struct rtw89_chan *chan, const struct rtw89_chan *chan,
struct rtw89_txpwr_limit_ru *lmt_ru, struct rtw89_txpwr_limit_ru *lmt_ru,
@ -1992,7 +2008,161 @@ void rtw89_phy_fill_txpwr_limit_ru(struct rtw89_dev *rtwdev,
break; break;
} }
} }
EXPORT_SYMBOL(rtw89_phy_fill_txpwr_limit_ru);
void rtw89_phy_set_txpwr_byrate(struct rtw89_dev *rtwdev,
const struct rtw89_chan *chan,
enum rtw89_phy_idx phy_idx)
{
static const u8 rs[] = {
RTW89_RS_CCK,
RTW89_RS_OFDM,
RTW89_RS_MCS,
RTW89_RS_HEDCM,
};
struct rtw89_rate_desc cur;
u8 band = chan->band_type;
u8 ch = chan->channel;
u32 addr, val;
s8 v[4] = {};
u8 i;
rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
"[TXPWR] set txpwr byrate with ch=%d\n", ch);
BUILD_BUG_ON(rtw89_rs_idx_max[RTW89_RS_CCK] % 4);
BUILD_BUG_ON(rtw89_rs_idx_max[RTW89_RS_OFDM] % 4);
BUILD_BUG_ON(rtw89_rs_idx_max[RTW89_RS_MCS] % 4);
BUILD_BUG_ON(rtw89_rs_idx_max[RTW89_RS_HEDCM] % 4);
addr = R_AX_PWR_BY_RATE;
for (cur.nss = 0; cur.nss <= RTW89_NSS_2; cur.nss++) {
for (i = 0; i < ARRAY_SIZE(rs); i++) {
if (cur.nss >= rtw89_rs_nss_max[rs[i]])
continue;
cur.rs = rs[i];
for (cur.idx = 0; cur.idx < rtw89_rs_idx_max[rs[i]];
cur.idx++) {
v[cur.idx % 4] =
rtw89_phy_read_txpwr_byrate(rtwdev,
band,
&cur);
if ((cur.idx + 1) % 4)
continue;
val = FIELD_PREP(GENMASK(7, 0), v[0]) |
FIELD_PREP(GENMASK(15, 8), v[1]) |
FIELD_PREP(GENMASK(23, 16), v[2]) |
FIELD_PREP(GENMASK(31, 24), v[3]);
rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr,
val);
addr += 4;
}
}
}
}
EXPORT_SYMBOL(rtw89_phy_set_txpwr_byrate);
void rtw89_phy_set_txpwr_offset(struct rtw89_dev *rtwdev,
const struct rtw89_chan *chan,
enum rtw89_phy_idx phy_idx)
{
struct rtw89_rate_desc desc = {
.nss = RTW89_NSS_1,
.rs = RTW89_RS_OFFSET,
};
u8 band = chan->band_type;
s8 v[RTW89_RATE_OFFSET_MAX] = {};
u32 val;
rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr offset\n");
for (desc.idx = 0; desc.idx < RTW89_RATE_OFFSET_MAX; desc.idx++)
v[desc.idx] = rtw89_phy_read_txpwr_byrate(rtwdev, band, &desc);
BUILD_BUG_ON(RTW89_RATE_OFFSET_MAX != 5);
val = FIELD_PREP(GENMASK(3, 0), v[0]) |
FIELD_PREP(GENMASK(7, 4), v[1]) |
FIELD_PREP(GENMASK(11, 8), v[2]) |
FIELD_PREP(GENMASK(15, 12), v[3]) |
FIELD_PREP(GENMASK(19, 16), v[4]);
rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_OFST_CTRL,
GENMASK(19, 0), val);
}
EXPORT_SYMBOL(rtw89_phy_set_txpwr_offset);
void rtw89_phy_set_txpwr_limit(struct rtw89_dev *rtwdev,
const struct rtw89_chan *chan,
enum rtw89_phy_idx phy_idx)
{
struct rtw89_txpwr_limit lmt;
u8 ch = chan->channel;
u8 bw = chan->band_width;
const s8 *ptr;
u32 addr, val;
u8 i, j;
rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
"[TXPWR] set txpwr limit with ch=%d bw=%d\n", ch, bw);
BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit) !=
RTW89_TXPWR_LMT_PAGE_SIZE);
addr = R_AX_PWR_LMT;
for (i = 0; i < RTW89_NTX_NUM; i++) {
rtw89_phy_fill_txpwr_limit(rtwdev, chan, &lmt, i);
ptr = (s8 *)&lmt;
for (j = 0; j < RTW89_TXPWR_LMT_PAGE_SIZE;
j += 4, addr += 4, ptr += 4) {
val = FIELD_PREP(GENMASK(7, 0), ptr[0]) |
FIELD_PREP(GENMASK(15, 8), ptr[1]) |
FIELD_PREP(GENMASK(23, 16), ptr[2]) |
FIELD_PREP(GENMASK(31, 24), ptr[3]);
rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
}
}
}
EXPORT_SYMBOL(rtw89_phy_set_txpwr_limit);
void rtw89_phy_set_txpwr_limit_ru(struct rtw89_dev *rtwdev,
const struct rtw89_chan *chan,
enum rtw89_phy_idx phy_idx)
{
struct rtw89_txpwr_limit_ru lmt_ru;
u8 ch = chan->channel;
u8 bw = chan->band_width;
const s8 *ptr;
u32 addr, val;
u8 i, j;
rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
"[TXPWR] set txpwr limit ru with ch=%d bw=%d\n", ch, bw);
BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit_ru) !=
RTW89_TXPWR_LMT_RU_PAGE_SIZE);
addr = R_AX_PWR_RU_LMT;
for (i = 0; i < RTW89_NTX_NUM; i++) {
rtw89_phy_fill_txpwr_limit_ru(rtwdev, chan, &lmt_ru, i);
ptr = (s8 *)&lmt_ru;
for (j = 0; j < RTW89_TXPWR_LMT_RU_PAGE_SIZE;
j += 4, addr += 4, ptr += 4) {
val = FIELD_PREP(GENMASK(7, 0), ptr[0]) |
FIELD_PREP(GENMASK(15, 8), ptr[1]) |
FIELD_PREP(GENMASK(23, 16), ptr[2]) |
FIELD_PREP(GENMASK(31, 24), ptr[3]);
rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
}
}
}
EXPORT_SYMBOL(rtw89_phy_set_txpwr_limit_ru);
struct rtw89_phy_iter_ra_data { struct rtw89_phy_iter_ra_data {
struct rtw89_dev *rtwdev; struct rtw89_dev *rtwdev;
@ -2106,6 +2276,10 @@ void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,
if (func < RTW89_PHY_C2H_FUNC_RA_MAX) if (func < RTW89_PHY_C2H_FUNC_RA_MAX)
handler = rtw89_phy_c2h_ra_handler[func]; handler = rtw89_phy_c2h_ra_handler[func];
break; break;
case RTW89_PHY_C2H_CLASS_DM:
if (func == RTW89_PHY_C2H_DM_FUNC_LOWRT_RTY)
return;
fallthrough;
default: default:
rtw89_info(rtwdev, "c2h class %d not support\n", class); rtw89_info(rtwdev, "c2h class %d not support\n", class);
return; return;

View File

@ -114,6 +114,15 @@ enum rtw89_phy_c2h_ra_func {
RTW89_PHY_C2H_FUNC_RA_MAX, RTW89_PHY_C2H_FUNC_RA_MAX,
}; };
enum rtw89_phy_c2h_dm_func {
RTW89_PHY_C2H_DM_FUNC_FW_TEST,
RTW89_PHY_C2H_DM_FUNC_FW_TRIG_TX_RPT,
RTW89_PHY_C2H_DM_FUNC_SIGB,
RTW89_PHY_C2H_DM_FUNC_LOWRT_RTY,
RTW89_PHY_C2H_DM_FUNC_MCC_DIG,
RTW89_PHY_C2H_DM_FUNC_NUM,
};
enum rtw89_phy_c2h_class { enum rtw89_phy_c2h_class {
RTW89_PHY_C2H_CLASS_RUA, RTW89_PHY_C2H_CLASS_RUA,
RTW89_PHY_C2H_CLASS_RA, RTW89_PHY_C2H_CLASS_RA,
@ -317,9 +326,6 @@ struct rtw89_nbi_reg_def {
struct rtw89_reg_def notch2_en; struct rtw89_reg_def notch2_en;
}; };
extern const u8 rtw89_rs_idx_max[RTW89_RS_MAX];
extern const u8 rtw89_rs_nss_max[RTW89_RS_MAX];
static inline void rtw89_phy_write8(struct rtw89_dev *rtwdev, static inline void rtw89_phy_write8(struct rtw89_dev *rtwdev,
u32 addr, u8 data) u32 addr, u8 data)
{ {
@ -377,6 +383,50 @@ static inline u32 rtw89_phy_read32_mask(struct rtw89_dev *rtwdev,
return rtw89_read32_mask(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, mask); return rtw89_read32_mask(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, mask);
} }
static inline
enum rtw89_gain_offset rtw89_subband_to_gain_offset_band_of_ofdm(enum rtw89_subband subband)
{
switch (subband) {
default:
case RTW89_CH_2G:
return RTW89_GAIN_OFFSET_2G_OFDM;
case RTW89_CH_5G_BAND_1:
return RTW89_GAIN_OFFSET_5G_LOW;
case RTW89_CH_5G_BAND_3:
return RTW89_GAIN_OFFSET_5G_MID;
case RTW89_CH_5G_BAND_4:
return RTW89_GAIN_OFFSET_5G_HIGH;
}
}
static inline
enum rtw89_phy_bb_gain_band rtw89_subband_to_bb_gain_band(enum rtw89_subband subband)
{
switch (subband) {
default:
case RTW89_CH_2G:
return RTW89_BB_GAIN_BAND_2G;
case RTW89_CH_5G_BAND_1:
return RTW89_BB_GAIN_BAND_5G_L;
case RTW89_CH_5G_BAND_3:
return RTW89_BB_GAIN_BAND_5G_M;
case RTW89_CH_5G_BAND_4:
return RTW89_BB_GAIN_BAND_5G_H;
case RTW89_CH_6G_BAND_IDX0:
case RTW89_CH_6G_BAND_IDX1:
return RTW89_BB_GAIN_BAND_6G_L;
case RTW89_CH_6G_BAND_IDX2:
case RTW89_CH_6G_BAND_IDX3:
return RTW89_BB_GAIN_BAND_6G_M;
case RTW89_CH_6G_BAND_IDX4:
case RTW89_CH_6G_BAND_IDX5:
return RTW89_BB_GAIN_BAND_6G_H;
case RTW89_CH_6G_BAND_IDX6:
case RTW89_CH_6G_BAND_IDX7:
return RTW89_BB_GAIN_BAND_6G_UH;
}
}
enum rtw89_rfk_flag { enum rtw89_rfk_flag {
RTW89_RFK_F_WRF = 0, RTW89_RFK_F_WRF = 0,
RTW89_RFK_F_WM = 1, RTW89_RFK_F_WM = 1,
@ -458,20 +508,24 @@ void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev,
void rtw89_phy_dm_init(struct rtw89_dev *rtwdev); void rtw89_phy_dm_init(struct rtw89_dev *rtwdev);
void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
u32 data, enum rtw89_phy_idx phy_idx); u32 data, enum rtw89_phy_idx phy_idx);
u32 rtw89_phy_read32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
enum rtw89_phy_idx phy_idx);
void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev, void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev,
const struct rtw89_txpwr_table *tbl); const struct rtw89_txpwr_table *tbl);
s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band,
const struct rtw89_rate_desc *rate_desc);
void rtw89_phy_fill_txpwr_limit(struct rtw89_dev *rtwdev,
const struct rtw89_chan *chan,
struct rtw89_txpwr_limit *lmt,
u8 ntx);
void rtw89_phy_fill_txpwr_limit_ru(struct rtw89_dev *rtwdev,
const struct rtw89_chan *chan,
struct rtw89_txpwr_limit_ru *lmt_ru,
u8 ntx);
s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band, s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band,
u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch); u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch);
void rtw89_phy_set_txpwr_byrate(struct rtw89_dev *rtwdev,
const struct rtw89_chan *chan,
enum rtw89_phy_idx phy_idx);
void rtw89_phy_set_txpwr_offset(struct rtw89_dev *rtwdev,
const struct rtw89_chan *chan,
enum rtw89_phy_idx phy_idx);
void rtw89_phy_set_txpwr_limit(struct rtw89_dev *rtwdev,
const struct rtw89_chan *chan,
enum rtw89_phy_idx phy_idx);
void rtw89_phy_set_txpwr_limit_ru(struct rtw89_dev *rtwdev,
const struct rtw89_chan *chan,
enum rtw89_phy_idx phy_idx);
void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta); void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta);
void rtw89_phy_ra_update(struct rtw89_dev *rtwdev); void rtw89_phy_ra_update(struct rtw89_dev *rtwdev);
void rtw89_phy_ra_updata_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta, void rtw89_phy_ra_updata_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta,

View File

@ -34,6 +34,9 @@
#define R_AX_SYS_CLK_CTRL 0x0008 #define R_AX_SYS_CLK_CTRL 0x0008
#define B_AX_CPU_CLK_EN BIT(14) #define B_AX_CPU_CLK_EN BIT(14)
#define R_AX_SYS_SWR_CTRL1 0x0010
#define B_AX_SYM_CTRL_SPS_PWMFREQ BIT(10)
#define R_AX_SYS_ADIE_PAD_PWR_CTRL 0x0018 #define R_AX_SYS_ADIE_PAD_PWR_CTRL 0x0018
#define B_AX_SYM_PADPDN_WL_PTA_1P3 BIT(6) #define B_AX_SYM_PADPDN_WL_PTA_1P3 BIT(6)
#define B_AX_SYM_PADPDN_WL_RFC_1P3 BIT(5) #define B_AX_SYM_PADPDN_WL_RFC_1P3 BIT(5)
@ -42,6 +45,9 @@
#define B_AX_R_DIS_PRST BIT(6) #define B_AX_R_DIS_PRST BIT(6)
#define B_AX_WLOCK_1C_BIT6 BIT(5) #define B_AX_WLOCK_1C_BIT6 BIT(5)
#define R_AX_AFE_LDO_CTRL 0x0020
#define B_AX_AON_OFF_PC_EN BIT(23)
#define R_AX_EFUSE_CTRL_1 0x0038 #define R_AX_EFUSE_CTRL_1 0x0038
#define B_AX_EF_PGPD_MASK GENMASK(30, 28) #define B_AX_EF_PGPD_MASK GENMASK(30, 28)
#define B_AX_EF_RDT BIT(27) #define B_AX_EF_RDT BIT(27)
@ -118,6 +124,9 @@
#define B_AX_R_AX_BG_LPF BIT(2) #define B_AX_R_AX_BG_LPF BIT(2)
#define B_AX_R_AX_BG GENMASK(1, 0) #define B_AX_R_AX_BG GENMASK(1, 0)
#define R_AX_HCI_LDO_CTRL 0x007A
#define B_AX_R_AX_VADJ_MASK GENMASK(3, 0)
#define R_AX_PLATFORM_ENABLE 0x0088 #define R_AX_PLATFORM_ENABLE 0x0088
#define B_AX_AXIDMA_EN BIT(3) #define B_AX_AXIDMA_EN BIT(3)
#define B_AX_WCPU_EN BIT(1) #define B_AX_WCPU_EN BIT(1)
@ -125,6 +134,7 @@
#define R_AX_WLLPS_CTRL 0x0090 #define R_AX_WLLPS_CTRL 0x0090
#define B_AX_DIS_WLBT_LPSEN_LOPC BIT(1) #define B_AX_DIS_WLBT_LPSEN_LOPC BIT(1)
#define SW_LPS_OPTION 0x0001A0B2
#define R_AX_SCOREBOARD 0x00AC #define R_AX_SCOREBOARD 0x00AC
#define B_AX_TOGGLE BIT(31) #define B_AX_TOGGLE BIT(31)
@ -229,6 +239,13 @@
#define R_AX_GPIO0_7_FUNC_SEL 0x02D0 #define R_AX_GPIO0_7_FUNC_SEL 0x02D0
#define R_AX_EECS_EESK_FUNC_SEL 0x02D8
#define B_AX_PINMUX_EESK_FUNC_SEL_MASK GENMASK(7, 4)
#define R_AX_LED1_FUNC_SEL 0x02DC
#define B_AX_PINMUX_EESK_FUNC_SEL_V1_MASK GENMASK(27, 24)
#define PINMUX_EESK_FUNC_SEL_BT_LOG 0x1
#define R_AX_GPIO0_15_EECS_EESK_LED1_PULL_LOW_EN 0x02E4 #define R_AX_GPIO0_15_EECS_EESK_LED1_PULL_LOW_EN 0x02E4
#define B_AX_LED1_PULL_LOW_EN BIT(18) #define B_AX_LED1_PULL_LOW_EN BIT(18)
#define B_AX_EESK_PULL_LOW_EN BIT(17) #define B_AX_EESK_PULL_LOW_EN BIT(17)
@ -249,6 +266,10 @@
#define B_AX_USB_HCISYS_PWR_STE_MASK GENMASK(3, 2) #define B_AX_USB_HCISYS_PWR_STE_MASK GENMASK(3, 2)
#define B_AX_PCIE_HCISYS_PWR_STE_MASK GENMASK(1, 0) #define B_AX_PCIE_HCISYS_PWR_STE_MASK GENMASK(1, 0)
#define R_AX_SPS_DIG_OFF_CTRL0 0x0400
#define B_AX_C3_L1_MASK GENMASK(5, 4)
#define B_AX_C1_L1_MASK GENMASK(1, 0)
#define R_AX_AFE_OFF_CTRL1 0x0444 #define R_AX_AFE_OFF_CTRL1 0x0444
#define B_AX_S1_LDO_VSEL_F_MASK GENMASK(25, 24) #define B_AX_S1_LDO_VSEL_F_MASK GENMASK(25, 24)
#define B_AX_S1_LDO2PWRCUT_F BIT(23) #define B_AX_S1_LDO2PWRCUT_F BIT(23)
@ -445,6 +466,7 @@
#define B_AX_DISPATCHER_EN BIT(18) #define B_AX_DISPATCHER_EN BIT(18)
#define B_AX_BBRPT_EN BIT(17) #define B_AX_BBRPT_EN BIT(17)
#define B_AX_MAC_SEC_EN BIT(16) #define B_AX_MAC_SEC_EN BIT(16)
#define B_AX_DMACREG_GCKEN BIT(15)
#define B_AX_MAC_UN_EN BIT(15) #define B_AX_MAC_UN_EN BIT(15)
#define B_AX_H_AXIDMA_EN BIT(14) #define B_AX_H_AXIDMA_EN BIT(14)
@ -2991,6 +3013,7 @@
#define R_AX_PWR_RATE_CTRL 0xD200 #define R_AX_PWR_RATE_CTRL 0xD200
#define R_AX_PWR_RATE_CTRL_C1 0xF200 #define R_AX_PWR_RATE_CTRL_C1 0xF200
#define B_AX_PWR_REF GENMASK(27, 10)
#define B_AX_FORCE_PWR_BY_RATE_EN BIT(9) #define B_AX_FORCE_PWR_BY_RATE_EN BIT(9)
#define B_AX_FORCE_PWR_BY_RATE_VALUE_MASK GENMASK(8, 0) #define B_AX_FORCE_PWR_BY_RATE_VALUE_MASK GENMASK(8, 0)
@ -3128,6 +3151,7 @@
#define BTC_BREAK_PARAM 0xf0ffffff #define BTC_BREAK_PARAM 0xf0ffffff
#define R_BTC_BT_COEX_MSK_TABLE 0xDA30 #define R_BTC_BT_COEX_MSK_TABLE 0xDA30
#define B_BTC_PRI_MASK_RXCCK_V1 BIT(28)
#define B_BTC_PRI_MASK_TX_RESP_V1 BIT(3) #define B_BTC_PRI_MASK_TX_RESP_V1 BIT(3)
#define R_AX_BT_COEX_CFG_2 0xDA34 #define R_AX_BT_COEX_CFG_2 0xDA34
@ -3271,8 +3295,10 @@
#define RR_MOD_IQK GENMASK(19, 4) #define RR_MOD_IQK GENMASK(19, 4)
#define RR_MOD_DPK GENMASK(19, 5) #define RR_MOD_DPK GENMASK(19, 5)
#define RR_MOD_MASK GENMASK(19, 16) #define RR_MOD_MASK GENMASK(19, 16)
#define RR_MOD_RGM GENMASK(13, 4)
#define RR_MOD_V_DOWN 0x0 #define RR_MOD_V_DOWN 0x0
#define RR_MOD_V_STANDBY 0x1 #define RR_MOD_V_STANDBY 0x1
#define RR_TXAGC 0x10001
#define RR_MOD_V_TX 0x2 #define RR_MOD_V_TX 0x2
#define RR_MOD_V_RX 0x3 #define RR_MOD_V_RX 0x3
#define RR_MOD_V_TXIQK 0x4 #define RR_MOD_V_TXIQK 0x4
@ -3308,6 +3334,10 @@
#define CFGCH_BAND1_2G 0 #define CFGCH_BAND1_2G 0
#define CFGCH_BAND1_5G 1 #define CFGCH_BAND1_5G 1
#define CFGCH_BAND1_6G 3 #define CFGCH_BAND1_6G 3
#define RR_CFGCH_POW_LCK BIT(15)
#define RR_CFGCH_TRX_AH BIT(14)
#define RR_CFGCH_BCN BIT(13)
#define RR_CFGCH_BW2 BIT(12)
#define RR_CFGCH_BAND0 GENMASK(9, 8) #define RR_CFGCH_BAND0 GENMASK(9, 8)
#define CFGCH_BAND0_2G 0 #define CFGCH_BAND0_2G 0
#define CFGCH_BAND0_5G 1 #define CFGCH_BAND0_5G 1
@ -3340,6 +3370,7 @@
#define RR_RXK_PLLEN BIT(5) #define RR_RXK_PLLEN BIT(5)
#define RR_LUTWA 0x33 #define RR_LUTWA 0x33
#define RR_LUTWA_MASK GENMASK(9, 0) #define RR_LUTWA_MASK GENMASK(9, 0)
#define RR_LUTWA_M1 GENMASK(7, 0)
#define RR_LUTWA_M2 GENMASK(4, 0) #define RR_LUTWA_M2 GENMASK(4, 0)
#define RR_LUTWD1 0x3e #define RR_LUTWD1 0x3e
#define RR_LUTWD0 0x3f #define RR_LUTWD0 0x3f
@ -3359,6 +3390,8 @@
#define RR_TXGA_TRK_EN BIT(7) #define RR_TXGA_TRK_EN BIT(7)
#define RR_TXGA_LOK_EXT GENMASK(4, 0) #define RR_TXGA_LOK_EXT GENMASK(4, 0)
#define RR_TXGA_LOK_EN BIT(0) #define RR_TXGA_LOK_EN BIT(0)
#define RR_TXGA_V1 0x10055
#define RR_TXGA_V1_TRK_EN BIT(7)
#define RR_GAINTX 0x56 #define RR_GAINTX 0x56
#define RR_GAINTX_ALL GENMASK(15, 0) #define RR_GAINTX_ALL GENMASK(15, 0)
#define RR_GAINTX_PAD GENMASK(9, 5) #define RR_GAINTX_PAD GENMASK(9, 5)
@ -3387,6 +3420,8 @@
#define RR_TXA2_LDO GENMASK(19, 16) #define RR_TXA2_LDO GENMASK(19, 16)
#define RR_TRXIQ 0x66 #define RR_TRXIQ 0x66
#define RR_RSV6 0x6d #define RR_RSV6 0x6d
#define RR_TXVBUF 0x7c
#define RR_TXVBUF_DACEN BIT(5)
#define RR_TXPOW 0x7f #define RR_TXPOW 0x7f
#define RR_TXPOW_TXA BIT(8) #define RR_TXPOW_TXA BIT(8)
#define RR_TXPOW_TXAS BIT(7) #define RR_TXPOW_TXAS BIT(7)
@ -3397,6 +3432,7 @@
#define RR_RXBB_VOBUF GENMASK(15, 12) #define RR_RXBB_VOBUF GENMASK(15, 12)
#define RR_RXBB_C2G GENMASK(16, 10) #define RR_RXBB_C2G GENMASK(16, 10)
#define RR_RXBB_C1G GENMASK(9, 8) #define RR_RXBB_C1G GENMASK(9, 8)
#define RR_RXBB_FATT GENMASK(7, 0)
#define RR_RXBB_ATTR GENMASK(7, 4) #define RR_RXBB_ATTR GENMASK(7, 4)
#define RR_RXBB_ATTC GENMASK(2, 0) #define RR_RXBB_ATTC GENMASK(2, 0)
#define RR_RXG 0x84 #define RR_RXG 0x84
@ -3407,10 +3443,14 @@
#define RR_RXAE_IQKMOD GENMASK(3, 0) #define RR_RXAE_IQKMOD GENMASK(3, 0)
#define RR_RXA 0x8a #define RR_RXA 0x8a
#define RR_RXA_DPK GENMASK(9, 8) #define RR_RXA_DPK GENMASK(9, 8)
#define RR_RXA_LNA 0x8b
#define RR_RXA2 0x8c #define RR_RXA2 0x8c
#define RR_RAA2_SWATT GENMASK(15, 9)
#define RR_RXA2_C1 GENMASK(12, 10) #define RR_RXA2_C1 GENMASK(12, 10)
#define RR_RXA2_C2 GENMASK(9, 3) #define RR_RXA2_C2 GENMASK(9, 3)
#define RR_RXA2_CC2 GENMASK(8, 7)
#define RR_RXA2_IATT GENMASK(7, 4) #define RR_RXA2_IATT GENMASK(7, 4)
#define RR_RXA2_HATT GENMASK(6, 0)
#define RR_RXA2_ATT GENMASK(3, 0) #define RR_RXA2_ATT GENMASK(3, 0)
#define RR_RXIQGEN 0x8d #define RR_RXIQGEN 0x8d
#define RR_RXIQGEN_ATTL GENMASK(12, 8) #define RR_RXIQGEN_ATTL GENMASK(12, 8)
@ -3422,6 +3462,7 @@
#define RR_RXBB2_IDAC GENMASK(11, 9) #define RR_RXBB2_IDAC GENMASK(11, 9)
#define RR_RXBB2_EBW GENMASK(6, 5) #define RR_RXBB2_EBW GENMASK(6, 5)
#define RR_XALNA2 0x90 #define RR_XALNA2 0x90
#define RR_XALNA2_SW2 GENMASK(9, 8)
#define RR_XALNA2_SW GENMASK(1, 0) #define RR_XALNA2_SW GENMASK(1, 0)
#define RR_DCK 0x92 #define RR_DCK 0x92
#define RR_DCK_DONE GENMASK(7, 5) #define RR_DCK_DONE GENMASK(7, 5)
@ -3439,18 +3480,36 @@
#define RR_IQGEN_BIAS GENMASK(11, 8) #define RR_IQGEN_BIAS GENMASK(11, 8)
#define RR_TXIQK 0x98 #define RR_TXIQK 0x98
#define RR_TXIQK_ATT2 GENMASK(15, 12) #define RR_TXIQK_ATT2 GENMASK(15, 12)
#define RR_TXIQK_ATT1 GENMASK(6, 0)
#define RR_TIA 0x9e #define RR_TIA 0x9e
#define RR_TIA_N6 BIT(8) #define RR_TIA_N6 BIT(8)
#define RR_MIXER 0x9f #define RR_MIXER 0x9f
#define RR_MIXER_GN GENMASK(4, 3) #define RR_MIXER_GN GENMASK(4, 3)
#define RR_POW 0xa0
#define RR_POW_SYN GENMASK(3, 2)
#define RR_LOGEN 0xa3 #define RR_LOGEN 0xa3
#define RR_LOGEN_RPT GENMASK(19, 16) #define RR_LOGEN_RPT GENMASK(19, 16)
#define RR_SX 0xaf
#define RR_LDO 0xb1
#define RR_LDO_SEL GENMASK(8, 6)
#define RR_VCO 0xb2
#define RR_LPF 0xb7
#define RR_LPF_BUSY BIT(8)
#define RR_XTALX2 0xb8 #define RR_XTALX2 0xb8
#define RR_MALSEL 0xbe #define RR_MALSEL 0xbe
#define RR_SYNFB 0xc5
#define RR_SYNFB_LK BIT(15)
#define RR_LCKST 0xcf
#define RR_LCKST_BIN BIT(0)
#define RR_LCK_TRG 0xd3 #define RR_LCK_TRG 0xd3
#define RR_LCK_TRGSEL BIT(8) #define RR_LCK_TRGSEL BIT(8)
#define RR_MMD 0xd5
#define RR_MMD_RST_EN BIT(8)
#define RR_MMD_RST_SYN BIT(6)
#define RR_IQKPLL 0xdc #define RR_IQKPLL 0xdc
#define RR_IQKPLL_MOD GENMASK(9, 8) #define RR_IQKPLL_MOD GENMASK(9, 8)
#define RR_SYNLUT 0xdd
#define RR_SYNLUT_MOD BIT(4)
#define RR_RCKD 0xde #define RR_RCKD 0xde
#define RR_RCKD_POW GENMASK(19, 13) #define RR_RCKD_POW GENMASK(19, 13)
#define RR_RCKD_BW BIT(2) #define RR_RCKD_BW BIT(2)
@ -3479,11 +3538,14 @@
#define B_ANAPAR_ADCCLK BIT(30) #define B_ANAPAR_ADCCLK BIT(30)
#define B_ANAPAR_FLTRST BIT(22) #define B_ANAPAR_FLTRST BIT(22)
#define B_ANAPAR_CRXBB GENMASK(18, 16) #define B_ANAPAR_CRXBB GENMASK(18, 16)
#define B_ANAPAR_EN BIT(16)
#define B_ANAPAR_14 GENMASK(15, 0) #define B_ANAPAR_14 GENMASK(15, 0)
#define R_RFE_E_A2 0x0334 #define R_RFE_E_A2 0x0334
#define R_RFE_O_SEL_A2 0x0338 #define R_RFE_O_SEL_A2 0x0338
#define R_RFE_SEL0_A2 0x033C #define R_RFE_SEL0_A2 0x033C
#define R_RFE_SEL32_A2 0x0340 #define R_RFE_SEL32_A2 0x0340
#define R_CIRST 0x035c
#define B_CIRST_SYN GENMASK(11, 10)
#define R_SWSI_DATA_V1 0x0370 #define R_SWSI_DATA_V1 0x0370
#define B_SWSI_DATA_VAL_V1 GENMASK(19, 0) #define B_SWSI_DATA_VAL_V1 GENMASK(19, 0)
#define B_SWSI_DATA_ADDR_V1 GENMASK(27, 20) #define B_SWSI_DATA_ADDR_V1 GENMASK(27, 20)
@ -3619,6 +3681,10 @@
#define R_P0_RFMODE 0x12AC #define R_P0_RFMODE 0x12AC
#define B_P0_RFMODE_ORI_TXRX_FTM_TX GENMASK(31, 4) #define B_P0_RFMODE_ORI_TXRX_FTM_TX GENMASK(31, 4)
#define B_P0_RFMODE_MUX GENMASK(11, 4) #define B_P0_RFMODE_MUX GENMASK(11, 4)
#define R_P0_RFMODE_ORI_RX 0x12AC
#define B_P0_RFMODE_ORI_RX_ALL GENMASK(23, 12)
#define R_P0_RFMODE_FTM_RX 0x12B0
#define B_P0_RFMODE_FTM_RX GENMASK(11, 0)
#define R_P0_NRBW 0x12B8 #define R_P0_NRBW 0x12B8
#define B_P0_NRBW_DBG BIT(30) #define B_P0_NRBW_DBG BIT(30)
#define R_S0_RXDC 0x12D4 #define R_S0_RXDC 0x12D4
@ -3671,6 +3737,9 @@
#define B_TXAGC_TP GENMASK(2, 0) #define B_TXAGC_TP GENMASK(2, 0)
#define R_TSSI_THER 0x1C10 #define R_TSSI_THER 0x1C10
#define B_TSSI_THER GENMASK(29, 24) #define B_TSSI_THER GENMASK(29, 24)
#define R_TSSI_CWRPT 0x1C18
#define B_TSSI_CWRPT_RDY BIT(16)
#define B_TSSI_CWRPT GENMASK(8, 0)
#define R_TXAGC_BTP 0x1CA0 #define R_TXAGC_BTP 0x1CA0
#define B_TXAGC_BTP GENMASK(31, 24) #define B_TXAGC_BTP GENMASK(31, 24)
#define R_TXAGC_BB 0x1C60 #define R_TXAGC_BB 0x1C60
@ -3712,6 +3781,8 @@
#define B_RXCCA_DIS_V1 BIT(0) #define B_RXCCA_DIS_V1 BIT(0)
#define R_RXSC 0x237C #define R_RXSC 0x237C
#define B_RXSC_EN BIT(0) #define B_RXSC_EN BIT(0)
#define R_RX_RPL_OFST 0x23AC
#define B_RX_RPL_OFST_CCK_MASK GENMASK(6, 0)
#define R_RXSCOBC 0x23B0 #define R_RXSCOBC 0x23B0
#define B_RXSCOBC_TH GENMASK(18, 0) #define B_RXSCOBC_TH GENMASK(18, 0)
#define R_RXSCOCCK 0x23B4 #define R_RXSCOCCK 0x23B4
@ -3725,9 +3796,18 @@
#define B_P1_EN_SOUND_WO_NDP BIT(1) #define B_P1_EN_SOUND_WO_NDP BIT(1)
#define R_S1_HW_SI_DIS 0x3200 #define R_S1_HW_SI_DIS 0x3200
#define B_S1_HW_SI_DIS_W_R_TRIG GENMASK(30, 28) #define B_S1_HW_SI_DIS_W_R_TRIG GENMASK(30, 28)
#define R_P1_RXCK 0x32A0
#define B_P1_RXCK_BW3 BIT(30)
#define B_P1_TXCK_ALL GENMASK(19, 12)
#define B_P1_RXCK_ON BIT(19)
#define B_P1_RXCK_VAL GENMASK(18, 16)
#define R_P1_RFMODE 0x32AC #define R_P1_RFMODE 0x32AC
#define B_P1_RFMODE_ORI_TXRX_FTM_TX GENMASK(31, 4) #define B_P1_RFMODE_ORI_TXRX_FTM_TX GENMASK(31, 4)
#define B_P1_RFMODE_MUX GENMASK(11, 4) #define B_P1_RFMODE_MUX GENMASK(11, 4)
#define R_P1_RFMODE_ORI_RX 0x32AC
#define B_P1_RFMODE_ORI_RX_ALL GENMASK(23, 12)
#define R_P1_RFMODE_FTM_RX 0x32B0
#define B_P1_RFMODE_FTM_RX GENMASK(11, 0)
#define R_P1_DBGMOD 0x32B8 #define R_P1_DBGMOD 0x32B8
#define B_P1_DBGMOD_ON BIT(30) #define B_P1_DBGMOD_ON BIT(30)
#define R_S1_RXDC 0x32D4 #define R_S1_RXDC 0x32D4
@ -3761,7 +3841,10 @@
#define R_T2F_GI_COMB 0x4424 #define R_T2F_GI_COMB 0x4424
#define B_T2F_GI_COMB_EN BIT(2) #define B_T2F_GI_COMB_EN BIT(2)
#define R_BT_DYN_DC_EST_EN 0x441C #define R_BT_DYN_DC_EST_EN 0x441C
#define R_BT_DYN_DC_EST_EN_V1 0x4420
#define B_BT_DYN_DC_EST_EN_MSK BIT(31) #define B_BT_DYN_DC_EST_EN_MSK BIT(31)
#define R_ASSIGN_SBD_OPT_V1 0x4440
#define B_ASSIGN_SBD_OPT_EN_V1 BIT(31)
#define R_ASSIGN_SBD_OPT 0x4450 #define R_ASSIGN_SBD_OPT 0x4450
#define B_ASSIGN_SBD_OPT_EN BIT(24) #define B_ASSIGN_SBD_OPT_EN BIT(24)
#define R_DCFO_COMP_S0 0x448C #define R_DCFO_COMP_S0 0x448C
@ -3770,8 +3853,12 @@
#define B_DCFO_WEIGHT_MSK GENMASK(27, 24) #define B_DCFO_WEIGHT_MSK GENMASK(27, 24)
#define R_DCFO_OPT 0x4494 #define R_DCFO_OPT 0x4494
#define B_DCFO_OPT_EN BIT(29) #define B_DCFO_OPT_EN BIT(29)
#define B_TXSHAPE_TRIANGULAR_CFG GENMASK(25, 24)
#define R_BANDEDGE 0x4498 #define R_BANDEDGE 0x4498
#define B_BANDEDGE_EN BIT(30) #define B_BANDEDGE_EN BIT(30)
#define R_DPD_BF 0x44a0
#define B_DPD_BF_OFDM GENMASK(16, 12)
#define B_DPD_BF_SCA GENMASK(6, 0)
#define R_TXPATH_SEL 0x458C #define R_TXPATH_SEL 0x458C
#define B_TXPATH_SEL_MSK GENMASK(31, 28) #define B_TXPATH_SEL_MSK GENMASK(31, 28)
#define R_TXPWR 0x4594 #define R_TXPWR 0x4594
@ -3910,20 +3997,42 @@
#define R_2P4G_BAND 0x4970 #define R_2P4G_BAND 0x4970
#define B_2P4G_BAND_SEL BIT(1) #define B_2P4G_BAND_SEL BIT(1)
#define R_FC0_BW 0x4974 #define R_FC0_BW 0x4974
#define B_FC0_BW_INV GENMASK(6, 0) #define R_FC0_BW_V1 0x49C0
#define B_FC0_BW_SET GENMASK(31, 30) #define B_FC0_BW_SET GENMASK(31, 30)
#define B_ANT_RX_BT_SEG0 GENMASK(25, 22) #define B_ANT_RX_BT_SEG0 GENMASK(25, 22)
#define B_ANT_RX_1RCCA_SEG1 GENMASK(21, 18) #define B_ANT_RX_1RCCA_SEG1 GENMASK(21, 18)
#define B_ANT_RX_1RCCA_SEG0 GENMASK(17, 14) #define B_ANT_RX_1RCCA_SEG0 GENMASK(17, 14)
#define B_FC0_BW_INV GENMASK(6, 0)
#define R_CHBW_MOD 0x4978 #define R_CHBW_MOD 0x4978
#define R_CHBW_MOD_V1 0x49C4
#define B_BT_SHARE BIT(14) #define B_BT_SHARE BIT(14)
#define B_CHBW_MOD_SBW GENMASK(13, 12) #define B_CHBW_MOD_SBW GENMASK(13, 12)
#define B_CHBW_MOD_PRICH GENMASK(11, 8) #define B_CHBW_MOD_PRICH GENMASK(11, 8)
#define B_ANT_RX_SEG0 GENMASK(3, 0) #define B_ANT_RX_SEG0 GENMASK(3, 0)
#define R_P0_RPL1 0x49B0
#define B_P0_RPL1_41_MASK GENMASK(31, 24)
#define B_P0_RPL1_40_MASK GENMASK(23, 16)
#define B_P0_RPL1_20_MASK GENMASK(15, 8)
#define B_P0_RPL1_MASK (B_P0_RPL1_41_MASK | B_P0_RPL1_40_MASK | B_P0_RPL1_20_MASK)
#define B_P0_RPL1_SHIFT 8
#define B_P0_RPL1_BIAS_MASK GENMASK(7, 0)
#define R_P0_RPL2 0x49B4
#define B_P0_RTL2_8A_MASK GENMASK(31, 24)
#define B_P0_RTL2_81_MASK GENMASK(23, 16)
#define B_P0_RTL2_80_MASK GENMASK(15, 8)
#define B_P0_RTL2_42_MASK GENMASK(7, 0)
#define R_P0_RPL3 0x49B8
#define B_P0_RTL3_89_MASK GENMASK(31, 24)
#define B_P0_RTL3_84_MASK GENMASK(23, 16)
#define B_P0_RTL3_83_MASK GENMASK(15, 8)
#define B_P0_RTL3_82_MASK GENMASK(7, 0)
#define R_PD_BOOST_EN 0x49E8 #define R_PD_BOOST_EN 0x49E8
#define B_PD_BOOST_EN BIT(7) #define B_PD_BOOST_EN BIT(7)
#define R_P1_BACKOFF_IBADC_V1 0x49F0 #define R_P1_BACKOFF_IBADC_V1 0x49F0
#define B_P1_BACKOFF_IBADC_V1 GENMASK(31, 26) #define B_P1_BACKOFF_IBADC_V1 GENMASK(31, 26)
#define R_P1_RPL1 0x4A00
#define R_P1_RPL2 0x4A04
#define R_P1_RPL3 0x4A08
#define R_BK_FC0_INV_V1 0x4A1C #define R_BK_FC0_INV_V1 0x4A1C
#define B_BK_FC0_INV_MSK_V1 GENMASK(18, 0) #define B_BK_FC0_INV_MSK_V1 GENMASK(18, 0)
#define R_CCK_FC0_INV_V1 0x4A20 #define R_CCK_FC0_INV_V1 0x4A20
@ -3934,8 +4043,10 @@
#define B_P1_AGC_EN BIT(31) #define B_P1_AGC_EN BIT(31)
#define R_PATH1_TIA_INIT_V1 0x4AA8 #define R_PATH1_TIA_INIT_V1 0x4AA8
#define B_PATH1_TIA_INIT_IDX_MSK_V1 BIT(9) #define B_PATH1_TIA_INIT_IDX_MSK_V1 BIT(9)
#define R_P0_AGC_RSVD 0x4ACC
#define R_PATH0_RXBB_V1 0x4AD4 #define R_PATH0_RXBB_V1 0x4AD4
#define B_PATH0_RXBB_MSK_V1 GENMASK(31, 0) #define B_PATH0_RXBB_MSK_V1 GENMASK(31, 0)
#define R_P1_AGC_RSVD 0x4AD8
#define R_PATH1_RXBB_V1 0x4AE0 #define R_PATH1_RXBB_V1 0x4AE0
#define B_PATH1_RXBB_MSK_V1 GENMASK(31, 0) #define B_PATH1_RXBB_MSK_V1 GENMASK(31, 0)
#define R_PATH0_BT_BACKOFF_V1 0x4AE4 #define R_PATH0_BT_BACKOFF_V1 0x4AE4
@ -3951,6 +4062,7 @@
#define B_PATH0_NOTCH2_EN BIT(12) #define B_PATH0_NOTCH2_EN BIT(12)
#define B_PATH0_NOTCH2_VAL GENMASK(11, 0) #define B_PATH0_NOTCH2_VAL GENMASK(11, 0)
#define R_PATH0_5MDET 0x4C4C #define R_PATH0_5MDET 0x4C4C
#define R_PATH0_5MDET_V1 0x46F8
#define B_PATH0_5MDET_EN BIT(12) #define B_PATH0_5MDET_EN BIT(12)
#define B_PATH0_5MDET_SB2 BIT(8) #define B_PATH0_5MDET_SB2 BIT(8)
#define B_PATH0_5MDET_SB0 BIT(6) #define B_PATH0_5MDET_SB0 BIT(6)
@ -3964,6 +4076,7 @@
#define B_PATH1_NOTCH2_EN BIT(12) #define B_PATH1_NOTCH2_EN BIT(12)
#define B_PATH1_NOTCH2_VAL GENMASK(11, 0) #define B_PATH1_NOTCH2_VAL GENMASK(11, 0)
#define R_PATH1_5MDET 0x4D10 #define R_PATH1_5MDET 0x4D10
#define R_PATH1_5MDET_V1 0x47B8
#define B_PATH1_5MDET_EN BIT(12) #define B_PATH1_5MDET_EN BIT(12)
#define B_PATH1_5MDET_SB2 BIT(8) #define B_PATH1_5MDET_SB2 BIT(8)
#define B_PATH1_5MDET_SB0 BIT(6) #define B_PATH1_5MDET_SB0 BIT(6)
@ -3992,6 +4105,20 @@
#define B_CFO_COMP_VALID_BIT BIT(29) #define B_CFO_COMP_VALID_BIT BIT(29)
#define B_CFO_COMP_WEIGHT_MSK GENMASK(27, 24) #define B_CFO_COMP_WEIGHT_MSK GENMASK(27, 24)
#define B_CFO_COMP_VAL_MSK GENMASK(11, 0) #define B_CFO_COMP_VAL_MSK GENMASK(11, 0)
#define R_TSSI_PA_K1 0x5600
#define R_TSSI_PA_K2 0x5604
#define R_P0_TSSI_ALIM1 0x5630
#define B_P0_TSSI_ALIM1 GENMASK(29, 0)
#define B_P0_TSSI_ALIM11 GENMASK(29, 20)
#define B_P0_TSSI_ALIM12 GENMASK(19, 10)
#define B_P0_TSSI_ALIM13 GENMASK(9, 0)
#define R_P0_TSSI_ALIM3 0x5634
#define B_P0_TSSI_ALIM31 GENMASK(9, 0)
#define R_TSSI_PA_K5 0x5638
#define R_P0_TSSI_ALIM2 0x563c
#define B_P0_TSSI_ALIM2 GENMASK(29, 0)
#define R_P0_TSSI_ALIM4 0x5640
#define R_TSSI_PA_K8 0x5644
#define R_UPD_CLK 0x5670 #define R_UPD_CLK 0x5670
#define B_DAC_VAL BIT(31) #define B_DAC_VAL BIT(31)
#define B_ACK_VAL GENMASK(30, 29) #define B_ACK_VAL GENMASK(30, 29)
@ -4003,6 +4130,11 @@
#define B_TXPWRB_VAL GENMASK(27, 19) #define B_TXPWRB_VAL GENMASK(27, 19)
#define R_DPD_OFT_EN 0x5800 #define R_DPD_OFT_EN 0x5800
#define B_DPD_OFT_EN BIT(28) #define B_DPD_OFT_EN BIT(28)
#define B_DPD_TSSI_CW GENMASK(26, 18)
#define B_DPD_PWR_CW GENMASK(17, 9)
#define B_DPD_REF GENMASK(8, 0)
#define R_P0_TSSIC 0x5814
#define B_P0_TSSIC_BYPASS BIT(11)
#define R_DPD_OFT_ADDR 0x5804 #define R_DPD_OFT_ADDR 0x5804
#define B_DPD_OFT_ADDR GENMASK(31, 27) #define B_DPD_OFT_ADDR GENMASK(31, 27)
#define R_TXPWRB_H 0x580c #define R_TXPWRB_H 0x580c
@ -4011,13 +4143,18 @@
#define B_P0_TMETER GENMASK(15, 10) #define B_P0_TMETER GENMASK(15, 10)
#define B_P0_TMETER_DIS BIT(16) #define B_P0_TMETER_DIS BIT(16)
#define B_P0_TMETER_TRK BIT(24) #define B_P0_TMETER_TRK BIT(24)
#define R_P1_TSSIC 0x7814
#define B_P1_TSSIC_BYPASS BIT(11)
#define R_P0_TSSI_TRK 0x5818 #define R_P0_TSSI_TRK 0x5818
#define B_P0_TSSI_TRK_EN BIT(30) #define B_P0_TSSI_TRK_EN BIT(30)
#define B_P0_TSSI_RFC GENMASK(28, 27)
#define B_P0_TSSI_OFT_EN BIT(28) #define B_P0_TSSI_OFT_EN BIT(28)
#define B_P0_TSSI_OFT GENMASK(7, 0) #define B_P0_TSSI_OFT GENMASK(7, 0)
#define R_P0_TSSI_AVG 0x5820 #define R_P0_TSSI_AVG 0x5820
#define B_P0_TSSI_EN BIT(31)
#define B_P0_TSSI_AVG GENMASK(15, 12) #define B_P0_TSSI_AVG GENMASK(15, 12)
#define R_P0_RFCTM 0x5864 #define R_P0_RFCTM 0x5864
#define B_P0_RFCTM_EN BIT(29)
#define B_P0_RFCTM_VAL GENMASK(25, 20) #define B_P0_RFCTM_VAL GENMASK(25, 20)
#define R_P0_RFCTM_RDY BIT(26) #define R_P0_RFCTM_RDY BIT(26)
#define R_P0_TRSW 0x5868 #define R_P0_TRSW 0x5868
@ -4030,13 +4167,16 @@
#define B_P0_RFM_TX_OPT BIT(6) #define B_P0_RFM_TX_OPT BIT(6)
#define B_P0_RFM_BT_EN BIT(5) #define B_P0_RFM_BT_EN BIT(5)
#define B_P0_RFM_OUT GENMASK(4, 0) #define B_P0_RFM_OUT GENMASK(4, 0)
#define R_P0_PATH_RST 0x58AC
#define R_P0_TXDPD 0x58D4 #define R_P0_TXDPD 0x58D4
#define B_P0_TXDPD GENMASK(31, 28) #define B_P0_TXDPD GENMASK(31, 28)
#define R_P0_TXPW_RSTB 0x58DC #define R_P0_TXPW_RSTB 0x58DC
#define B_P0_TXPW_RSTB_MANON BIT(30) #define B_P0_TXPW_RSTB_MANON BIT(30)
#define B_P0_TXPW_RSTB_TSSI BIT(31) #define B_P0_TXPW_RSTB_TSSI BIT(31)
#define R_P0_TSSI_MV_AVG 0x58E4 #define R_P0_TSSI_MV_AVG 0x58E4
#define B_P0_TSSI_MV_MIX GENMASK(19, 11)
#define B_P0_TSSI_MV_AVG GENMASK(13, 11) #define B_P0_TSSI_MV_AVG GENMASK(13, 11)
#define B_P0_TSSI_MV_CLR BIT(14)
#define R_TXGAIN_SCALE 0x58F0 #define R_TXGAIN_SCALE 0x58F0
#define B_TXGAIN_SCALE_EN BIT(19) #define B_TXGAIN_SCALE_EN BIT(19)
#define B_TXGAIN_SCALE_OFT GENMASK(31, 24) #define B_TXGAIN_SCALE_OFT GENMASK(31, 24)
@ -4061,24 +4201,41 @@
#define B_S0_DACKQ8_K GENMASK(15, 8) #define B_S0_DACKQ8_K GENMASK(15, 8)
#define R_RPL_BIAS_COMP1 0x6DF0 #define R_RPL_BIAS_COMP1 0x6DF0
#define B_RPL_BIAS_COMP1_MASK GENMASK(7, 0) #define B_RPL_BIAS_COMP1_MASK GENMASK(7, 0)
#define R_P1_TSSI_ALIM1 0x7630
#define B_P1_TSSI_ALIM1 GENMASK(29, 0)
#define B_P1_TSSI_ALIM11 GENMASK(29, 20)
#define B_P1_TSSI_ALIM12 GENMASK(19, 10)
#define B_P1_TSSI_ALIM13 GENMASK(9, 0)
#define R_P1_TSSI_ALIM3 0x7634
#define B_P1_TSSI_ALIM31 GENMASK(9, 0)
#define R_P1_TSSI_ALIM2 0x763c
#define B_P1_TSSI_ALIM2 GENMASK(29, 0)
#define R_P1_TSSIC 0x7814
#define B_P1_TSSIC_BYPASS BIT(11)
#define R_P1_TMETER 0x7810 #define R_P1_TMETER 0x7810
#define B_P1_TMETER GENMASK(15, 10) #define B_P1_TMETER GENMASK(15, 10)
#define B_P1_TMETER_DIS BIT(16) #define B_P1_TMETER_DIS BIT(16)
#define B_P1_TMETER_TRK BIT(24) #define B_P1_TMETER_TRK BIT(24)
#define R_P1_TSSI_TRK 0x7818 #define R_P1_TSSI_TRK 0x7818
#define B_P1_TSSI_TRK_EN BIT(30) #define B_P1_TSSI_TRK_EN BIT(30)
#define B_P1_TSSI_RFC GENMASK(28, 27)
#define B_P1_TSSI_OFT_EN BIT(28) #define B_P1_TSSI_OFT_EN BIT(28)
#define B_P1_TSSI_OFT GENMASK(7, 0) #define B_P1_TSSI_OFT GENMASK(7, 0)
#define R_P1_TSSI_AVG 0x7820 #define R_P1_TSSI_AVG 0x7820
#define B_P1_TSSI_EN BIT(31)
#define B_P1_TSSI_AVG GENMASK(15, 12) #define B_P1_TSSI_AVG GENMASK(15, 12)
#define R_P1_RFCTM 0x7864 #define R_P1_RFCTM 0x7864
#define R_P1_RFCTM_RDY BIT(26) #define R_P1_RFCTM_RDY BIT(26)
#define B_P1_RFCTM_VAL GENMASK(25, 20) #define B_P1_RFCTM_VAL GENMASK(25, 20)
#define B_P1_RFCTM_DEL GENMASK(19, 11)
#define R_P1_PATH_RST 0x78AC
#define R_P1_TXPW_RSTB 0x78DC #define R_P1_TXPW_RSTB 0x78DC
#define B_P1_TXPW_RSTB_MANON BIT(30) #define B_P1_TXPW_RSTB_MANON BIT(30)
#define B_P1_TXPW_RSTB_TSSI BIT(31) #define B_P1_TXPW_RSTB_TSSI BIT(31)
#define R_P1_TSSI_MV_AVG 0x78E4 #define R_P1_TSSI_MV_AVG 0x78E4
#define B_P1_TSSI_MV_MIX GENMASK(19, 11)
#define B_P1_TSSI_MV_AVG GENMASK(13, 11) #define B_P1_TSSI_MV_AVG GENMASK(13, 11)
#define B_P1_TSSI_MV_CLR BIT(14)
#define R_TSSI_THOF 0x7C00 #define R_TSSI_THOF 0x7C00
#define R_S1_DACKI 0x7E00 #define R_S1_DACKI 0x7E00
#define B_S1_DACKI_AR GENMASK(31, 28) #define B_S1_DACKI_AR GENMASK(31, 28)
@ -4148,6 +4305,7 @@
#define B_KPATH_CFG_ED GENMASK(21, 20) #define B_KPATH_CFG_ED GENMASK(21, 20)
#define R_KIP_RPT1 0x80D4 #define R_KIP_RPT1 0x80D4
#define B_KIP_RPT1_SEL GENMASK(21, 16) #define B_KIP_RPT1_SEL GENMASK(21, 16)
#define B_KIP_RPT1_SEL_V1 GENMASK(19, 16)
#define R_SRAM_IQRX 0x80D8 #define R_SRAM_IQRX 0x80D8
#define R_GAPK 0x80E0 #define R_GAPK 0x80E0
#define B_GAPK_ADR BIT(0) #define B_GAPK_ADR BIT(0)
@ -4169,12 +4327,14 @@
#define B_PRT_COM_GL GENMASK(7, 4) #define B_PRT_COM_GL GENMASK(7, 4)
#define B_PRT_COM_CORI GENMASK(7, 0) #define B_PRT_COM_CORI GENMASK(7, 0)
#define B_PRT_COM_RXBB GENMASK(5, 0) #define B_PRT_COM_RXBB GENMASK(5, 0)
#define B_PRT_COM_RXBB_V1 GENMASK(4, 0)
#define B_PRT_COM_DONE BIT(0) #define B_PRT_COM_DONE BIT(0)
#define R_COEF_SEL 0x8104 #define R_COEF_SEL 0x8104
#define B_COEF_SEL_IQC BIT(0) #define B_COEF_SEL_IQC BIT(0)
#define B_COEF_SEL_MDPD BIT(8) #define B_COEF_SEL_MDPD BIT(8)
#define R_CFIR_SYS 0x8120 #define R_CFIR_SYS 0x8120
#define R_IQK_RES 0x8124 #define R_IQK_RES 0x8124
#define B_IQK_RES_K BIT(28)
#define B_IQK_RES_TXCFIR GENMASK(11, 8) #define B_IQK_RES_TXCFIR GENMASK(11, 8)
#define B_IQK_RES_RXCFIR GENMASK(3, 0) #define B_IQK_RES_RXCFIR GENMASK(3, 0)
#define R_TXIQC 0x8138 #define R_TXIQC 0x8138
@ -4206,13 +4366,18 @@
#define B_DPD_LBK BIT(7) #define B_DPD_LBK BIT(7)
#define R_DPD_CH0 0x81AC #define R_DPD_CH0 0x81AC
#define R_DPD_BND 0x81B4 #define R_DPD_BND 0x81B4
#define B_DPD_BND_1 GENMASK(24, 16)
#define B_DPD_BND_0 GENMASK(8, 0)
#define R_DPD_CH0A 0x81BC #define R_DPD_CH0A 0x81BC
#define B_DPD_MEN GENMASK(31, 28) #define B_DPD_MEN GENMASK(31, 28)
#define B_DPD_ORDER GENMASK(26, 24) #define B_DPD_ORDER GENMASK(26, 24)
#define B_DPD_ORDER_V1 GENMASK(26, 25)
#define B_DPD_CFG GENMASK(22, 0)
#define B_DPD_SEL GENMASK(13, 8) #define B_DPD_SEL GENMASK(13, 8)
#define R_TXAGC_RFK 0x81C4 #define R_TXAGC_RFK 0x81C4
#define B_TXAGC_RFK_CH0 GENMASK(5, 0) #define B_TXAGC_RFK_CH0 GENMASK(5, 0)
#define R_DPD_COM 0x81C8 #define R_DPD_COM 0x81C8
#define B_DPD_COM_OF BIT(15)
#define R_KIP_IQP 0x81CC #define R_KIP_IQP 0x81CC
#define B_KIP_IQP_SW GENMASK(13, 12) #define B_KIP_IQP_SW GENMASK(13, 12)
#define B_KIP_IQP_IQSW GENMASK(5, 0) #define B_KIP_IQP_IQSW GENMASK(5, 0)
@ -4231,6 +4396,9 @@
#define B_RPT_PER_TSSI GENMASK(28, 16) #define B_RPT_PER_TSSI GENMASK(28, 16)
#define B_RPT_PER_OF GENMASK(15, 8) #define B_RPT_PER_OF GENMASK(15, 8)
#define B_RPT_PER_TH GENMASK(5, 0) #define B_RPT_PER_TH GENMASK(5, 0)
#define R_IQRSN 0x8220
#define B_IQRSN_K1 BIT(28)
#define B_IQRSN_K2 BIT(16)
#define R_RXCFIR_P0C0 0x8D40 #define R_RXCFIR_P0C0 0x8D40
#define R_RXCFIR_P0C1 0x8D84 #define R_RXCFIR_P0C1 0x8D84
#define R_RXCFIR_P0C2 0x8DC8 #define R_RXCFIR_P0C2 0x8DC8
@ -4288,6 +4456,8 @@
#define B_DACK_S0P3_OK BIT(2) #define B_DACK_S0P3_OK BIT(2)
#define R_DACK_DADCK01 0xC084 #define R_DACK_DADCK01 0xC084
#define B_DACK_DADCK01 GENMASK(31, 24) #define B_DACK_DADCK01 GENMASK(31, 24)
#define R_DRCK_FH 0xC094
#define B_DRCK_LAT BIT(9)
#define R_DRCK 0xC0C4 #define R_DRCK 0xC0C4
#define B_DRCK_IDLE BIT(9) #define B_DRCK_IDLE BIT(9)
#define B_DRCK_EN BIT(6) #define B_DRCK_EN BIT(6)
@ -4295,15 +4465,29 @@
#define R_DRCK_RES 0xC0C8 #define R_DRCK_RES 0xC0C8
#define B_DRCK_RES GENMASK(19, 15) #define B_DRCK_RES GENMASK(19, 15)
#define B_DRCK_POL BIT(3) #define B_DRCK_POL BIT(3)
#define R_DRCK_V1 0xC0CC
#define B_DRCK_V1_SEL BIT(9)
#define B_DRCK_V1_KICK BIT(6)
#define B_DRCK_V1_CV GENMASK(4, 0)
#define R_DRCK_RS 0xC0D0
#define B_DRCK_RS_LPS GENMASK(19, 15)
#define B_DRCK_RS_DONE BIT(3)
#define R_PATH0_SAMPL_DLY_T_V1 0xC0D4 #define R_PATH0_SAMPL_DLY_T_V1 0xC0D4
#define B_PATH0_SAMPL_DLY_T_MSK_V1 GENMASK(27, 26) #define B_PATH0_SAMPL_DLY_T_MSK_V1 GENMASK(27, 26)
#define R_P0_CFCH_BW0 0xC0D4 #define R_P0_CFCH_BW0 0xC0D4
#define B_P0_CFCH_BW0 GENMASK(27, 26) #define B_P0_CFCH_BW0 GENMASK(27, 26)
#define R_P0_CFCH_BW1 0xC0D8 #define R_P0_CFCH_BW1 0xC0D8
#define B_P0_CFCH_EX BIT(13)
#define B_P0_CFCH_BW1 GENMASK(8, 5) #define B_P0_CFCH_BW1 GENMASK(8, 5)
#define R_ADDCK0D 0xC0F0
#define B_ADDCK0D_VAL2 GENMASK(31, 26)
#define B_ADDCK0D_VAL GENMASK(25, 16)
#define R_ADDCK0 0xC0F4 #define R_ADDCK0 0xC0F4
#define B_ADDCK0_TRG BIT(11)
#define B_ADDCK0 GENMASK(9, 8) #define B_ADDCK0 GENMASK(9, 8)
#define B_ADDCK0_MAN GENMASK(5, 4)
#define B_ADDCK0_EN BIT(4) #define B_ADDCK0_EN BIT(4)
#define B_ADDCK0_VAL GENMASK(3, 0)
#define B_ADDCK0_RST BIT(2) #define B_ADDCK0_RST BIT(2)
#define R_ADDCK0_RL 0xC0F8 #define R_ADDCK0_RL 0xC0F8
#define B_ADDCK0_RLS GENMASK(29, 28) #define B_ADDCK0_RLS GENMASK(29, 28)
@ -4343,9 +4527,15 @@
#define R_PATH0_BW_SEL_V1 0xC0D8 #define R_PATH0_BW_SEL_V1 0xC0D8
#define B_PATH0_BW_SEL_MSK_V1 GENMASK(8, 5) #define B_PATH0_BW_SEL_MSK_V1 GENMASK(8, 5)
#define R_PATH1_BW_SEL_V1 0xC1D8 #define R_PATH1_BW_SEL_V1 0xC1D8
#define B_PATH1_BW_SEL_EX BIT(13)
#define B_PATH1_BW_SEL_MSK_V1 GENMASK(8, 5) #define B_PATH1_BW_SEL_MSK_V1 GENMASK(8, 5)
#define R_ADDCK1D 0xC1F0
#define B_ADDCK1D_VAL2 GENMASK(31, 26)
#define B_ADDCK1D_VAL GENMASK(25, 16)
#define R_ADDCK1 0xC1F4 #define R_ADDCK1 0xC1F4
#define B_ADDCK1_TRG BIT(11)
#define B_ADDCK1 GENMASK(9, 8) #define B_ADDCK1 GENMASK(9, 8)
#define B_ADDCK1_MAN GENMASK(5, 4)
#define B_ADDCK1_EN BIT(4) #define B_ADDCK1_EN BIT(4)
#define B_ADDCK1_RST BIT(2) #define B_ADDCK1_RST BIT(2)
#define R_ADDCK1_RL 0xC1F8 #define R_ADDCK1_RL 0xC1F8

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@ -1410,151 +1410,14 @@ static void rtw8852a_set_txpwr_ref(struct rtw89_dev *rtwdev,
phy_idx); phy_idx);
} }
static void rtw8852a_set_txpwr_byrate(struct rtw89_dev *rtwdev,
const struct rtw89_chan *chan,
enum rtw89_phy_idx phy_idx)
{
u8 band = chan->band_type;
u8 ch = chan->channel;
static const u8 rs[] = {
RTW89_RS_CCK,
RTW89_RS_OFDM,
RTW89_RS_MCS,
RTW89_RS_HEDCM,
};
s8 tmp;
u8 i, j;
u32 val, shf, addr = R_AX_PWR_BY_RATE;
struct rtw89_rate_desc cur;
rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
"[TXPWR] set txpwr byrate with ch=%d\n", ch);
for (cur.nss = 0; cur.nss <= RTW89_NSS_2; cur.nss++) {
for (i = 0; i < ARRAY_SIZE(rs); i++) {
if (cur.nss >= rtw89_rs_nss_max[rs[i]])
continue;
val = 0;
cur.rs = rs[i];
for (j = 0; j < rtw89_rs_idx_max[rs[i]]; j++) {
cur.idx = j;
shf = (j % 4) * 8;
tmp = rtw89_phy_read_txpwr_byrate(rtwdev, band,
&cur);
val |= (tmp << shf);
if ((j + 1) % 4)
continue;
rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
val = 0;
addr += 4;
}
}
}
}
static void rtw8852a_set_txpwr_offset(struct rtw89_dev *rtwdev,
const struct rtw89_chan *chan,
enum rtw89_phy_idx phy_idx)
{
u8 band = chan->band_type;
struct rtw89_rate_desc desc = {
.nss = RTW89_NSS_1,
.rs = RTW89_RS_OFFSET,
};
u32 val = 0;
s8 v;
rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr offset\n");
for (desc.idx = 0; desc.idx < RTW89_RATE_OFFSET_MAX; desc.idx++) {
v = rtw89_phy_read_txpwr_byrate(rtwdev, band, &desc);
val |= ((v & 0xf) << (4 * desc.idx));
}
rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_OFST_CTRL,
GENMASK(19, 0), val);
}
static void rtw8852a_set_txpwr_limit(struct rtw89_dev *rtwdev,
const struct rtw89_chan *chan,
enum rtw89_phy_idx phy_idx)
{
#define __MAC_TXPWR_LMT_PAGE_SIZE 40
u8 ch = chan->channel;
u8 bw = chan->band_width;
struct rtw89_txpwr_limit lmt[NTX_NUM_8852A];
u32 addr, val;
const s8 *ptr;
u8 i, j;
rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
"[TXPWR] set txpwr limit with ch=%d bw=%d\n", ch, bw);
for (i = 0; i < NTX_NUM_8852A; i++) {
rtw89_phy_fill_txpwr_limit(rtwdev, chan, &lmt[i], i);
for (j = 0; j < __MAC_TXPWR_LMT_PAGE_SIZE; j += 4) {
addr = R_AX_PWR_LMT + j + __MAC_TXPWR_LMT_PAGE_SIZE * i;
ptr = (s8 *)&lmt[i] + j;
val = FIELD_PREP(GENMASK(7, 0), ptr[0]) |
FIELD_PREP(GENMASK(15, 8), ptr[1]) |
FIELD_PREP(GENMASK(23, 16), ptr[2]) |
FIELD_PREP(GENMASK(31, 24), ptr[3]);
rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
}
}
#undef __MAC_TXPWR_LMT_PAGE_SIZE
}
static void rtw8852a_set_txpwr_limit_ru(struct rtw89_dev *rtwdev,
const struct rtw89_chan *chan,
enum rtw89_phy_idx phy_idx)
{
#define __MAC_TXPWR_LMT_RU_PAGE_SIZE 24
u8 ch = chan->channel;
u8 bw = chan->band_width;
struct rtw89_txpwr_limit_ru lmt_ru[NTX_NUM_8852A];
u32 addr, val;
const s8 *ptr;
u8 i, j;
rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
"[TXPWR] set txpwr limit ru with ch=%d bw=%d\n", ch, bw);
for (i = 0; i < NTX_NUM_8852A; i++) {
rtw89_phy_fill_txpwr_limit_ru(rtwdev, chan, &lmt_ru[i], i);
for (j = 0; j < __MAC_TXPWR_LMT_RU_PAGE_SIZE; j += 4) {
addr = R_AX_PWR_RU_LMT + j +
__MAC_TXPWR_LMT_RU_PAGE_SIZE * i;
ptr = (s8 *)&lmt_ru[i] + j;
val = FIELD_PREP(GENMASK(7, 0), ptr[0]) |
FIELD_PREP(GENMASK(15, 8), ptr[1]) |
FIELD_PREP(GENMASK(23, 16), ptr[2]) |
FIELD_PREP(GENMASK(31, 24), ptr[3]);
rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
}
}
#undef __MAC_TXPWR_LMT_RU_PAGE_SIZE
}
static void rtw8852a_set_txpwr(struct rtw89_dev *rtwdev, static void rtw8852a_set_txpwr(struct rtw89_dev *rtwdev,
const struct rtw89_chan *chan, const struct rtw89_chan *chan,
enum rtw89_phy_idx phy_idx) enum rtw89_phy_idx phy_idx)
{ {
rtw8852a_set_txpwr_byrate(rtwdev, chan, phy_idx); rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx);
rtw8852a_set_txpwr_offset(rtwdev, chan, phy_idx); rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx);
rtw8852a_set_txpwr_limit(rtwdev, chan, phy_idx); rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx);
rtw8852a_set_txpwr_limit_ru(rtwdev, chan, phy_idx); rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx);
} }
static void rtw8852a_set_txpwr_ctrl(struct rtw89_dev *rtwdev, static void rtw8852a_set_txpwr_ctrl(struct rtw89_dev *rtwdev,
@ -2007,19 +1870,6 @@ static struct rtw89_btc_fbtc_mreg rtw89_btc_8852a_mon_reg[] = {
RTW89_DEF_FBTC_MREG(REG_BT_MODEM, 4, 0x178), RTW89_DEF_FBTC_MREG(REG_BT_MODEM, 4, 0x178),
}; };
static
void rtw8852a_btc_bt_aci_imp(struct rtw89_dev *rtwdev)
{
struct rtw89_btc *btc = &rtwdev->btc;
struct rtw89_btc_dm *dm = &btc->dm;
struct rtw89_btc_bt_info *bt = &btc->cx.bt;
struct rtw89_btc_bt_link_info *b = &bt->link_info;
/* fix LNA2 = level-5 for BT ACI issue at BTG */
if (btc->dm.wl_btg_rx && b->profile_cnt.now != 0)
dm->trx_para_level = 1;
}
static static
void rtw8852a_btc_update_bt_cnt(struct rtw89_dev *rtwdev) void rtw8852a_btc_update_bt_cnt(struct rtw89_dev *rtwdev)
{ {
@ -2178,7 +2028,6 @@ static const struct rtw89_chip_ops rtw8852a_chip_ops = {
.btc_set_wl_pri = rtw8852a_btc_set_wl_pri, .btc_set_wl_pri = rtw8852a_btc_set_wl_pri,
.btc_set_wl_txpwr_ctrl = rtw8852a_btc_set_wl_txpwr_ctrl, .btc_set_wl_txpwr_ctrl = rtw8852a_btc_set_wl_txpwr_ctrl,
.btc_get_bt_rssi = rtw8852a_btc_get_bt_rssi, .btc_get_bt_rssi = rtw8852a_btc_get_bt_rssi,
.btc_bt_aci_imp = rtw8852a_btc_bt_aci_imp,
.btc_update_bt_cnt = rtw8852a_btc_update_bt_cnt, .btc_update_bt_cnt = rtw8852a_btc_update_bt_cnt,
.btc_wl_s1_standby = rtw8852a_btc_wl_s1_standby, .btc_wl_s1_standby = rtw8852a_btc_wl_s1_standby,
.btc_set_wl_rx_gain = rtw8852a_btc_set_wl_rx_gain, .btc_set_wl_rx_gain = rtw8852a_btc_set_wl_rx_gain,

View File

@ -8,7 +8,6 @@
#include "core.h" #include "core.h"
#define RF_PATH_NUM_8852A 2 #define RF_PATH_NUM_8852A 2
#define NTX_NUM_8852A 2
enum rtw8852a_pmac_mode { enum rtw8852a_pmac_mode {
NONE_TEST, NONE_TEST,

File diff suppressed because it is too large Load Diff

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@ -0,0 +1,137 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2019-2022 Realtek Corporation
*/
#ifndef __RTW89_8852B_H__
#define __RTW89_8852B_H__
#include "core.h"
#define RF_PATH_NUM_8852B 2
#define BB_PATH_NUM_8852B 2
enum rtw8852b_pmac_mode {
NONE_TEST,
PKTS_TX,
PKTS_RX,
CONT_TX
};
struct rtw8852b_u_efuse {
u8 rsvd[0x88];
u8 mac_addr[ETH_ALEN];
};
struct rtw8852b_e_efuse {
u8 mac_addr[ETH_ALEN];
};
struct rtw8852b_tssi_offset {
u8 cck_tssi[TSSI_CCK_CH_GROUP_NUM];
u8 bw40_tssi[TSSI_MCS_2G_CH_GROUP_NUM];
u8 rsvd[7];
u8 bw40_1s_tssi_5g[TSSI_MCS_5G_CH_GROUP_NUM];
} __packed;
struct rtw8852b_efuse {
u8 rsvd[0x210];
struct rtw8852b_tssi_offset path_a_tssi;
u8 rsvd1[10];
struct rtw8852b_tssi_offset path_b_tssi;
u8 rsvd2[94];
u8 channel_plan;
u8 xtal_k;
u8 rsvd3;
u8 iqk_lck;
u8 rsvd4[5];
u8 reg_setting:2;
u8 tx_diversity:1;
u8 rx_diversity:2;
u8 ac_mode:1;
u8 module_type:2;
u8 rsvd5;
u8 shared_ant:1;
u8 coex_type:3;
u8 ant_iso:1;
u8 radio_on_off:1;
u8 rsvd6:2;
u8 eeprom_version;
u8 customer_id;
u8 tx_bb_swing_2g;
u8 tx_bb_swing_5g;
u8 tx_cali_pwr_trk_mode;
u8 trx_path_selection;
u8 rfe_type;
u8 country_code[2];
u8 rsvd7[3];
u8 path_a_therm;
u8 path_b_therm;
u8 rsvd8[2];
u8 rx_gain_2g_ofdm;
u8 rsvd9;
u8 rx_gain_2g_cck;
u8 rsvd10;
u8 rx_gain_5g_low;
u8 rsvd11;
u8 rx_gain_5g_mid;
u8 rsvd12;
u8 rx_gain_5g_high;
u8 rsvd13[35];
u8 path_a_cck_pwr_idx[6];
u8 path_a_bw40_1tx_pwr_idx[5];
u8 path_a_ofdm_1tx_pwr_idx_diff:4;
u8 path_a_bw20_1tx_pwr_idx_diff:4;
u8 path_a_bw20_2tx_pwr_idx_diff:4;
u8 path_a_bw40_2tx_pwr_idx_diff:4;
u8 path_a_cck_2tx_pwr_idx_diff:4;
u8 path_a_ofdm_2tx_pwr_idx_diff:4;
u8 rsvd14[0xf2];
union {
struct rtw8852b_u_efuse u;
struct rtw8852b_e_efuse e;
};
} __packed;
struct rtw8852b_bb_pmac_info {
u8 en_pmac_tx:1;
u8 is_cck:1;
u8 mode:3;
u8 rsvd:3;
u16 tx_cnt;
u16 period;
u16 tx_time;
u8 duty_cycle;
};
struct rtw8852b_bb_tssi_bak {
u8 tx_path;
u8 rx_path;
u32 p0_rfmode;
u32 p0_rfmode_ftm;
u32 p1_rfmode;
u32 p1_rfmode_ftm;
s16 tx_pwr; /* S9 */
};
extern const struct rtw89_chip_info rtw8852b_chip_info;
void rtw8852b_bb_set_plcp_tx(struct rtw89_dev *rtwdev);
void rtw8852b_bb_set_pmac_tx(struct rtw89_dev *rtwdev,
struct rtw8852b_bb_pmac_info *tx_info,
enum rtw89_phy_idx idx);
void rtw8852b_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable,
u16 tx_cnt, u16 period, u16 tx_time,
enum rtw89_phy_idx idx);
void rtw8852b_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm,
enum rtw89_phy_idx idx);
void rtw8852b_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path);
void rtw8852b_bb_ctrl_rx_path(struct rtw89_dev *rtwdev,
enum rtw89_rf_path_bit rx_path);
void rtw8852b_bb_tx_mode_switch(struct rtw89_dev *rtwdev,
enum rtw89_phy_idx idx, u8 mode);
void rtw8852b_bb_backup_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx idx,
struct rtw8852b_bb_tssi_bak *bak);
void rtw8852b_bb_restore_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx idx,
const struct rtw8852b_bb_tssi_bak *bak);
#endif

File diff suppressed because it is too large Load Diff

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@ -0,0 +1,25 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2019-2022 Realtek Corporation
*/
#ifndef __RTW89_8852B_RFK_H__
#define __RTW89_8852B_RFK_H__
#include "core.h"
void rtw8852b_rck(struct rtw89_dev *rtwdev);
void rtw8852b_dack(struct rtw89_dev *rtwdev);
void rtw8852b_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
void rtw8852b_rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
void rtw8852b_dpk_init(struct rtw89_dev *rtwdev);
void rtw8852b_dpk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy);
void rtw8852b_dpk_track(struct rtw89_dev *rtwdev);
void rtw8852b_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, bool hwtx_en);
void rtw8852b_tssi_scan(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy);
void rtw8852b_wifi_scan_notify(struct rtw89_dev *rtwdev, bool scan_start,
enum rtw89_phy_idx phy_idx);
void rtw8852b_set_channel_rf(struct rtw89_dev *rtwdev,
const struct rtw89_chan *chan,
enum rtw89_phy_idx phy_idx);
#endif

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@ -0,0 +1,794 @@
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/* Copyright(c) 2019-2020 Realtek Corporation
*/
#include "rtw8852b_rfk_table.h"
static const struct rtw89_reg5_def rtw8852b_afe_init_defs[] = {
RTW89_DECL_RFK_WM(0xC0D4, 0xffffffff, 0x4486888c),
RTW89_DECL_RFK_WM(0xC0D8, 0xffffffff, 0xc6ba10e0),
RTW89_DECL_RFK_WM(0xc0dc, 0xffffffff, 0x30c52868),
RTW89_DECL_RFK_WM(0xc0e0, 0xffffffff, 0x05008128),
RTW89_DECL_RFK_WM(0xc0e4, 0xffffffff, 0x0000272b),
RTW89_DECL_RFK_WM(0xC1D4, 0xffffffff, 0x4486888c),
RTW89_DECL_RFK_WM(0xC1D8, 0xffffffff, 0xc6ba10e0),
RTW89_DECL_RFK_WM(0xc1dc, 0xffffffff, 0x30c52868),
RTW89_DECL_RFK_WM(0xc1e0, 0xffffffff, 0x05008128),
RTW89_DECL_RFK_WM(0xc1e4, 0xffffffff, 0x0000272b),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_afe_init_defs);
static const struct rtw89_reg5_def rtw8852b_check_addc_defs_a[] = {
RTW89_DECL_RFK_WM(0x20f4, BIT(24), 0x0),
RTW89_DECL_RFK_WM(0x20f8, 0x80000000, 0x1),
RTW89_DECL_RFK_WM(0x20f0, 0xff0000, 0x1),
RTW89_DECL_RFK_WM(0x20f0, 0xf00, 0x2),
RTW89_DECL_RFK_WM(0x20f0, 0xf, 0x0),
RTW89_DECL_RFK_WM(0x20f0, 0xc0, 0x2),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_check_addc_defs_a);
static const struct rtw89_reg5_def rtw8852b_check_addc_defs_b[] = {
RTW89_DECL_RFK_WM(0x20f4, BIT(24), 0x0),
RTW89_DECL_RFK_WM(0x20f8, 0x80000000, 0x1),
RTW89_DECL_RFK_WM(0x20f0, 0xff0000, 0x1),
RTW89_DECL_RFK_WM(0x20f0, 0xf00, 0x2),
RTW89_DECL_RFK_WM(0x20f0, 0xf, 0x0),
RTW89_DECL_RFK_WM(0x20f0, 0xc0, 0x3),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_check_addc_defs_b);
static const struct rtw89_reg5_def rtw8852b_check_dadc_en_defs_a[] = {
RTW89_DECL_RFK_WM(0x032C, BIT(30), 0x0),
RTW89_DECL_RFK_WM(0x030C, 0x0f000000, 0xf),
RTW89_DECL_RFK_WM(0x030C, 0x0f000000, 0x3),
RTW89_DECL_RFK_WM(0x032C, BIT(16), 0x0),
RTW89_DECL_RFK_WM(0x12dc, BIT(0), 0x1),
RTW89_DECL_RFK_WM(0x12e8, BIT(2), 0x1),
RTW89_DECL_RFK_WRF(RF_PATH_A, 0x8f, BIT(13), 0x1),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_check_dadc_en_defs_a);
static const struct rtw89_reg5_def rtw8852b_check_dadc_en_defs_b[] = {
RTW89_DECL_RFK_WM(0x032C, BIT(30), 0x0),
RTW89_DECL_RFK_WM(0x030C, 0x0f000000, 0xf),
RTW89_DECL_RFK_WM(0x030C, 0x0f000000, 0x3),
RTW89_DECL_RFK_WM(0x032C, BIT(16), 0x0),
RTW89_DECL_RFK_WM(0x32dc, BIT(0), 0x1),
RTW89_DECL_RFK_WM(0x32e8, BIT(2), 0x1),
RTW89_DECL_RFK_WRF(RF_PATH_B, 0x8f, BIT(13), 0x1),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_check_dadc_en_defs_b);
static const struct rtw89_reg5_def rtw8852b_check_dadc_dis_defs_a[] = {
RTW89_DECL_RFK_WM(0x12dc, BIT(0), 0x0),
RTW89_DECL_RFK_WM(0x12e8, BIT(2), 0x0),
RTW89_DECL_RFK_WRF(RF_PATH_A, 0x8f, BIT(13), 0x0),
RTW89_DECL_RFK_WM(0x032C, BIT(16), 0x1),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_check_dadc_dis_defs_a);
static const struct rtw89_reg5_def rtw8852b_check_dadc_dis_defs_b[] = {
RTW89_DECL_RFK_WM(0x32dc, BIT(0), 0x0),
RTW89_DECL_RFK_WM(0x32e8, BIT(2), 0x0),
RTW89_DECL_RFK_WRF(RF_PATH_B, 0x8f, BIT(13), 0x0),
RTW89_DECL_RFK_WM(0x032C, BIT(16), 0x1),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_check_dadc_dis_defs_b);
static const struct rtw89_reg5_def rtw8852b_dack_s0_1_defs[] = {
RTW89_DECL_RFK_WM(0x12A0, BIT(15), 0x1),
RTW89_DECL_RFK_WM(0x12A0, 0x00007000, 0x3),
RTW89_DECL_RFK_WM(0x12B8, BIT(30), 0x1),
RTW89_DECL_RFK_WM(0x030C, BIT(28), 0x1),
RTW89_DECL_RFK_WM(0x032C, 0x80000000, 0x0),
RTW89_DECL_RFK_WM(0xC0D8, BIT(16), 0x1),
RTW89_DECL_RFK_WM(0xc0dc, 0x0c000000, 0x3),
RTW89_DECL_RFK_WM(0xC004, BIT(30), 0x0),
RTW89_DECL_RFK_WM(0xc024, BIT(30), 0x0),
RTW89_DECL_RFK_WM(0xC004, 0x3ff00000, 0x30),
RTW89_DECL_RFK_WM(0xC004, 0xc0000000, 0x0),
RTW89_DECL_RFK_WM(0xC004, BIT(17), 0x1),
RTW89_DECL_RFK_WM(0xc024, BIT(17), 0x1),
RTW89_DECL_RFK_WM(0xc00c, BIT(2), 0x0),
RTW89_DECL_RFK_WM(0xc02c, BIT(2), 0x0),
RTW89_DECL_RFK_WM(0xC004, BIT(0), 0x1),
RTW89_DECL_RFK_WM(0xc024, BIT(0), 0x1),
RTW89_DECL_RFK_DELAY(1),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_dack_s0_1_defs);
static const struct rtw89_reg5_def rtw8852b_dack_s0_2_defs[] = {
RTW89_DECL_RFK_WM(0xc0dc, 0x0c000000, 0x0),
RTW89_DECL_RFK_WM(0xc00c, BIT(2), 0x1),
RTW89_DECL_RFK_WM(0xc02c, BIT(2), 0x1),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_dack_s0_2_defs);
static const struct rtw89_reg5_def rtw8852b_dack_s0_3_defs[] = {
RTW89_DECL_RFK_WM(0xC004, BIT(0), 0x0),
RTW89_DECL_RFK_WM(0xc024, BIT(0), 0x0),
RTW89_DECL_RFK_WM(0xC0D8, BIT(16), 0x0),
RTW89_DECL_RFK_WM(0x12A0, BIT(15), 0x0),
RTW89_DECL_RFK_WM(0x12A0, 0x00007000, 0x7),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_dack_s0_3_defs);
static const struct rtw89_reg5_def rtw8852b_dack_s1_1_defs[] = {
RTW89_DECL_RFK_WM(0x32a0, BIT(15), 0x1),
RTW89_DECL_RFK_WM(0x32a0, 0x7000, 0x3),
RTW89_DECL_RFK_WM(0x32B8, BIT(30), 0x1),
RTW89_DECL_RFK_WM(0x030C, BIT(28), 0x1),
RTW89_DECL_RFK_WM(0x032C, 0x80000000, 0x0),
RTW89_DECL_RFK_WM(0xC1D8, BIT(16), 0x1),
RTW89_DECL_RFK_WM(0xc1dc, 0x0c000000, 0x3),
RTW89_DECL_RFK_WM(0xc104, BIT(30), 0x0),
RTW89_DECL_RFK_WM(0xc124, BIT(30), 0x0),
RTW89_DECL_RFK_WM(0xc104, 0x3ff00000, 0x30),
RTW89_DECL_RFK_WM(0xc104, 0xc0000000, 0x0),
RTW89_DECL_RFK_WM(0xc104, BIT(17), 0x1),
RTW89_DECL_RFK_WM(0xc124, BIT(17), 0x1),
RTW89_DECL_RFK_WM(0xc10c, BIT(2), 0x0),
RTW89_DECL_RFK_WM(0xc12c, BIT(2), 0x0),
RTW89_DECL_RFK_WM(0xc104, BIT(0), 0x1),
RTW89_DECL_RFK_WM(0xc124, BIT(0), 0x1),
RTW89_DECL_RFK_DELAY(1),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_dack_s1_1_defs);
static const struct rtw89_reg5_def rtw8852b_dack_s1_2_defs[] = {
RTW89_DECL_RFK_WM(0xc1dc, 0x0c000000, 0x0),
RTW89_DECL_RFK_WM(0xc10c, BIT(2), 0x1),
RTW89_DECL_RFK_WM(0xc12c, BIT(2), 0x1),
RTW89_DECL_RFK_DELAY(1),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_dack_s1_2_defs);
static const struct rtw89_reg5_def rtw8852b_dack_s1_3_defs[] = {
RTW89_DECL_RFK_WM(0xc104, BIT(0), 0x0),
RTW89_DECL_RFK_WM(0xc124, BIT(0), 0x0),
RTW89_DECL_RFK_WM(0xC1D8, BIT(16), 0x0),
RTW89_DECL_RFK_WM(0x32a0, BIT(15), 0x0),
RTW89_DECL_RFK_WM(0x32a0, 0x7000, 0x7),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_dack_s1_3_defs);
static const struct rtw89_reg5_def rtw8852b_dpk_afe_defs[] = {
RTW89_DECL_RFK_WM(0x20fc, 0xffff0000, 0x0303),
RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
RTW89_DECL_RFK_WM(0x32b8, BIT(30), 0x1),
RTW89_DECL_RFK_WM(0x030c, 0xff000000, 0x13),
RTW89_DECL_RFK_WM(0x032c, 0xffff0000, 0x0041),
RTW89_DECL_RFK_WM(0x12b8, BIT(28), 0x1),
RTW89_DECL_RFK_WM(0x58c8, BIT(24), 0x1),
RTW89_DECL_RFK_WM(0x78c8, BIT(24), 0x1),
RTW89_DECL_RFK_WM(0x5864, 0xc0000000, 0x3),
RTW89_DECL_RFK_WM(0x7864, 0xc0000000, 0x3),
RTW89_DECL_RFK_WM(0x2008, 0x01FFFFFF, 0x1ffffff),
RTW89_DECL_RFK_WM(0x0c1c, BIT(2), 0x1),
RTW89_DECL_RFK_WM(0x0700, BIT(27), 0x1),
RTW89_DECL_RFK_WM(0x0c70, 0x000003FF, 0x3ff),
RTW89_DECL_RFK_WM(0x0c60, 0x00000003, 0x3),
RTW89_DECL_RFK_WM(0x0c6c, BIT(0), 0x1),
RTW89_DECL_RFK_WM(0x58ac, BIT(27), 0x1),
RTW89_DECL_RFK_WM(0x78ac, BIT(27), 0x1),
RTW89_DECL_RFK_WM(0x0c3c, BIT(9), 0x1),
RTW89_DECL_RFK_WM(0x2344, BIT(31), 0x1),
RTW89_DECL_RFK_WM(0x4490, BIT(31), 0x1),
RTW89_DECL_RFK_WM(0x12a0, 0x000ff000, 0xbf),
RTW89_DECL_RFK_WM(0x32a0, 0x000f0000, 0xb),
RTW89_DECL_RFK_WM(0x0700, 0x07000000, 0x5),
RTW89_DECL_RFK_WM(0x20fc, 0xffff0000, 0x3333),
RTW89_DECL_RFK_WM(0x580c, BIT(15), 0x1),
RTW89_DECL_RFK_WM(0x5800, 0x0000ffff, 0x0000),
RTW89_DECL_RFK_WM(0x780c, BIT(15), 0x1),
RTW89_DECL_RFK_WM(0x7800, 0x0000ffff, 0x0000),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_dpk_afe_defs);
static const struct rtw89_reg5_def rtw8852b_dpk_afe_restore_defs[] = {
RTW89_DECL_RFK_WM(0x20fc, 0xffff0000, 0x0303),
RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x0),
RTW89_DECL_RFK_WM(0x32b8, BIT(30), 0x0),
RTW89_DECL_RFK_WM(0x5864, 0xc0000000, 0x0),
RTW89_DECL_RFK_WM(0x7864, 0xc0000000, 0x0),
RTW89_DECL_RFK_WM(0x2008, 0x01FFFFFF, 0x0),
RTW89_DECL_RFK_WM(0x0c1c, BIT(2), 0x0),
RTW89_DECL_RFK_WM(0x0700, BIT(27), 0x0),
RTW89_DECL_RFK_WM(0x0c70, 0x000003FF, 0x63),
RTW89_DECL_RFK_WM(0x12a0, 0x000FF000, 0x00),
RTW89_DECL_RFK_WM(0x32a0, 0x000FF000, 0x00),
RTW89_DECL_RFK_WM(0x0700, 0x07000000, 0x0),
RTW89_DECL_RFK_WM(0x5864, BIT(29), 0x0),
RTW89_DECL_RFK_WM(0x7864, BIT(29), 0x0),
RTW89_DECL_RFK_WM(0x20fc, 0xffff0000, 0x0000),
RTW89_DECL_RFK_WM(0x58c8, BIT(24), 0x0),
RTW89_DECL_RFK_WM(0x78c8, BIT(24), 0x0),
RTW89_DECL_RFK_WM(0x0c3c, BIT(9), 0x0),
RTW89_DECL_RFK_WM(0x580c, BIT(15), 0x0),
RTW89_DECL_RFK_WM(0x58e4, 0x18000000, 0x1),
RTW89_DECL_RFK_WM(0x58e4, 0x18000000, 0x2),
RTW89_DECL_RFK_WM(0x780c, BIT(15), 0x0),
RTW89_DECL_RFK_WM(0x78e4, 0x18000000, 0x1),
RTW89_DECL_RFK_WM(0x78e4, 0x18000000, 0x2),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_dpk_afe_restore_defs);
static const struct rtw89_reg5_def rtw8852b_dpk_kip_defs[] = {
RTW89_DECL_RFK_WM(0x8008, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x8088, 0xffffffff, 0x80000000),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_dpk_kip_defs);
static const struct rtw89_reg5_def rtw8852b_tssi_sys_defs[] = {
RTW89_DECL_RFK_WM(0x12a8, 0x0000000f, 0x5),
RTW89_DECL_RFK_WM(0x32a8, 0x0000000f, 0x5),
RTW89_DECL_RFK_WM(0x12bc, 0x000ffff0, 0x5555),
RTW89_DECL_RFK_WM(0x32bc, 0x000ffff0, 0x5555),
RTW89_DECL_RFK_WM(0x0300, 0xff000000, 0x16),
RTW89_DECL_RFK_WM(0x0304, 0x000000ff, 0x19),
RTW89_DECL_RFK_WM(0x0314, 0xffff0000, 0x2041),
RTW89_DECL_RFK_WM(0x0318, 0xffffffff, 0x2041),
RTW89_DECL_RFK_WM(0x0318, 0xffffffff, 0x20012041),
RTW89_DECL_RFK_WM(0x0020, 0x00006000, 0x3),
RTW89_DECL_RFK_WM(0x0024, 0x00006000, 0x3),
RTW89_DECL_RFK_WM(0x0704, 0xffff0000, 0x601e),
RTW89_DECL_RFK_WM(0x2704, 0xffff0000, 0x601e),
RTW89_DECL_RFK_WM(0x0700, 0xf0000000, 0x4),
RTW89_DECL_RFK_WM(0x2700, 0xf0000000, 0x4),
RTW89_DECL_RFK_WM(0x0650, 0x3c000000, 0x0),
RTW89_DECL_RFK_WM(0x2650, 0x3c000000, 0x0),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_sys_defs);
static const struct rtw89_reg5_def rtw8852b_tssi_sys_a_defs_2g[] = {
RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x33),
RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x33),
RTW89_DECL_RFK_WM(0x58f8, 0x40000000, 0x1),
RTW89_DECL_RFK_WM(0x0304, 0x0000ff00, 0x1e),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_sys_a_defs_2g);
static const struct rtw89_reg5_def rtw8852b_tssi_sys_a_defs_5g[] = {
RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x44),
RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x44),
RTW89_DECL_RFK_WM(0x58f8, 0x40000000, 0x0),
RTW89_DECL_RFK_WM(0x0304, 0x0000ff00, 0x1d),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_sys_a_defs_5g);
static const struct rtw89_reg5_def rtw8852b_tssi_sys_b_defs_2g[] = {
RTW89_DECL_RFK_WM(0x32c0, 0x0ff00000, 0x33),
RTW89_DECL_RFK_WM(0x320c, 0x000000ff, 0x33),
RTW89_DECL_RFK_WM(0x78f8, 0x40000000, 0x1),
RTW89_DECL_RFK_WM(0x0304, 0x0000ff00, 0x1e),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_sys_b_defs_2g);
static const struct rtw89_reg5_def rtw8852b_tssi_sys_b_defs_5g[] = {
RTW89_DECL_RFK_WM(0x32c0, 0x0ff00000, 0x44),
RTW89_DECL_RFK_WM(0x320c, 0x000000ff, 0x44),
RTW89_DECL_RFK_WM(0x78f8, 0x40000000, 0x0),
RTW89_DECL_RFK_WM(0x0304, 0x0000ff00, 0x1d),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_sys_b_defs_5g);
static const struct rtw89_reg5_def rtw8852b_tssi_init_txpwr_defs_a[] = {
RTW89_DECL_RFK_WM(0x566c, 0x00001000, 0x0),
RTW89_DECL_RFK_WM(0x5800, 0xffffffff, 0x003f807f),
RTW89_DECL_RFK_WM(0x580c, 0x0000007f, 0x40),
RTW89_DECL_RFK_WM(0x580c, 0x0fffff00, 0x00040),
RTW89_DECL_RFK_WM(0x5810, 0xffffffff, 0x59010000),
RTW89_DECL_RFK_WM(0x5814, 0x01ffffff, 0x002d000),
RTW89_DECL_RFK_WM(0x5814, 0xf8000000, 0x00),
RTW89_DECL_RFK_WM(0x5818, 0xffffffff, 0x002c1800),
RTW89_DECL_RFK_WM(0x581c, 0x3fffffff, 0x1dc80280),
RTW89_DECL_RFK_WM(0x5820, 0xffffffff, 0x00002080),
RTW89_DECL_RFK_WM(0x580c, 0x10000000, 0x1),
RTW89_DECL_RFK_WM(0x580c, 0x40000000, 0x1),
RTW89_DECL_RFK_WM(0x5834, 0x3fffffff, 0x000115f2),
RTW89_DECL_RFK_WM(0x5838, 0x7fffffff, 0x0000121),
RTW89_DECL_RFK_WM(0x5854, 0x3fffffff, 0x000115f2),
RTW89_DECL_RFK_WM(0x5858, 0x7fffffff, 0x0000121),
RTW89_DECL_RFK_WM(0x5860, 0x80000000, 0x0),
RTW89_DECL_RFK_WM(0x5864, 0x07ffffff, 0x00801ff),
RTW89_DECL_RFK_WM(0x5898, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x589c, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x58a4, 0x000000ff, 0x16),
RTW89_DECL_RFK_WM(0x58b0, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x58b4, 0x7fffffff, 0x0a002000),
RTW89_DECL_RFK_WM(0x58b8, 0x7fffffff, 0x00007628),
RTW89_DECL_RFK_WM(0x58bc, 0x07ffffff, 0x7a7807f),
RTW89_DECL_RFK_WM(0x58c0, 0xfffe0000, 0x003f),
RTW89_DECL_RFK_WM(0x58c4, 0xffffffff, 0x0003ffff),
RTW89_DECL_RFK_WM(0x58c8, 0x00ffffff, 0x000000),
RTW89_DECL_RFK_WM(0x58c8, 0xf0000000, 0x0),
RTW89_DECL_RFK_WM(0x58cc, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x58d0, 0x07ffffff, 0x2008101),
RTW89_DECL_RFK_WM(0x58d4, 0x000000ff, 0x00),
RTW89_DECL_RFK_WM(0x58d4, 0x0003fe00, 0x0ff),
RTW89_DECL_RFK_WM(0x58d4, 0x07fc0000, 0x100),
RTW89_DECL_RFK_WM(0x58d8, 0xffffffff, 0x8008016c),
RTW89_DECL_RFK_WM(0x58dc, 0x0001ffff, 0x0807f),
RTW89_DECL_RFK_WM(0x58dc, 0xfff00000, 0x800),
RTW89_DECL_RFK_WM(0x58f0, 0x0003ffff, 0x001ff),
RTW89_DECL_RFK_WM(0x58f4, 0x000fffff, 0x000),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_init_txpwr_defs_a);
static const struct rtw89_reg5_def rtw8852b_tssi_init_txpwr_defs_b[] = {
RTW89_DECL_RFK_WM(0x566c, 0x00001000, 0x0),
RTW89_DECL_RFK_WM(0x7800, 0xffffffff, 0x003f807f),
RTW89_DECL_RFK_WM(0x780c, 0x0000007f, 0x40),
RTW89_DECL_RFK_WM(0x780c, 0x0fffff00, 0x00040),
RTW89_DECL_RFK_WM(0x7810, 0xffffffff, 0x59010000),
RTW89_DECL_RFK_WM(0x7814, 0x01ffffff, 0x002d000),
RTW89_DECL_RFK_WM(0x7814, 0xf8000000, 0x00),
RTW89_DECL_RFK_WM(0x7818, 0xffffffff, 0x002c1800),
RTW89_DECL_RFK_WM(0x781c, 0x3fffffff, 0x1dc80280),
RTW89_DECL_RFK_WM(0x7820, 0xffffffff, 0x00002080),
RTW89_DECL_RFK_WM(0x780c, 0x10000000, 0x1),
RTW89_DECL_RFK_WM(0x780c, 0x40000000, 0x1),
RTW89_DECL_RFK_WM(0x7834, 0x3fffffff, 0x000115f2),
RTW89_DECL_RFK_WM(0x7838, 0x7fffffff, 0x0000121),
RTW89_DECL_RFK_WM(0x7854, 0x3fffffff, 0x000115f2),
RTW89_DECL_RFK_WM(0x7858, 0x7fffffff, 0x0000121),
RTW89_DECL_RFK_WM(0x7860, 0x80000000, 0x0),
RTW89_DECL_RFK_WM(0x7864, 0x07ffffff, 0x00801ff),
RTW89_DECL_RFK_WM(0x7898, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x789c, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x78a4, 0x000000ff, 0x16),
RTW89_DECL_RFK_WM(0x78b0, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x78b4, 0x7fffffff, 0x0a002000),
RTW89_DECL_RFK_WM(0x78b8, 0x7fffffff, 0x00007628),
RTW89_DECL_RFK_WM(0x78bc, 0x07ffffff, 0x7a7807f),
RTW89_DECL_RFK_WM(0x78c0, 0xfffe0000, 0x003f),
RTW89_DECL_RFK_WM(0x78c4, 0xffffffff, 0x0003ffff),
RTW89_DECL_RFK_WM(0x78c8, 0x00ffffff, 0x000000),
RTW89_DECL_RFK_WM(0x78c8, 0xf0000000, 0x0),
RTW89_DECL_RFK_WM(0x78cc, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x78d0, 0x07ffffff, 0x2008101),
RTW89_DECL_RFK_WM(0x78d4, 0x000000ff, 0x00),
RTW89_DECL_RFK_WM(0x78d4, 0x0003fe00, 0x0ff),
RTW89_DECL_RFK_WM(0x78d4, 0x07fc0000, 0x100),
RTW89_DECL_RFK_WM(0x78d8, 0xffffffff, 0x8008016c),
RTW89_DECL_RFK_WM(0x78dc, 0x0001ffff, 0x0807f),
RTW89_DECL_RFK_WM(0x78dc, 0xfff00000, 0x800),
RTW89_DECL_RFK_WM(0x78f0, 0x0003ffff, 0x001ff),
RTW89_DECL_RFK_WM(0x78f4, 0x000fffff, 0x000),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_init_txpwr_defs_b);
static const struct rtw89_reg5_def rtw8852b_tssi_init_txpwr_he_tb_defs_a[] = {
RTW89_DECL_RFK_WM(0x58a0, 0xffffffff, 0x000000fe),
RTW89_DECL_RFK_WM(0x58e4, 0x0000007f, 0x1f),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_init_txpwr_he_tb_defs_a);
static const struct rtw89_reg5_def rtw8852b_tssi_init_txpwr_he_tb_defs_b[] = {
RTW89_DECL_RFK_WM(0x78a0, 0xffffffff, 0x000000fe),
RTW89_DECL_RFK_WM(0x78e4, 0x0000007f, 0x1f),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_init_txpwr_he_tb_defs_b);
static const struct rtw89_reg5_def rtw8852b_tssi_dck_defs_a[] = {
RTW89_DECL_RFK_WM(0x580c, 0x0fff0000, 0x000),
RTW89_DECL_RFK_WM(0x5814, 0x003ff000, 0x0ef),
RTW89_DECL_RFK_WM(0x5814, 0x18000000, 0x0),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_dck_defs_a);
static const struct rtw89_reg5_def rtw8852b_tssi_dck_defs_b[] = {
RTW89_DECL_RFK_WM(0x780c, 0x0fff0000, 0x000),
RTW89_DECL_RFK_WM(0x7814, 0x003ff000, 0x0ef),
RTW89_DECL_RFK_WM(0x7814, 0x18000000, 0x0),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_dck_defs_b);
static const struct rtw89_reg5_def rtw8852b_tssi_dac_gain_defs_a[] = {
RTW89_DECL_RFK_WM(0x58b0, 0x00000400, 0x1),
RTW89_DECL_RFK_WM(0x58b0, 0x00000fff, 0x000),
RTW89_DECL_RFK_WM(0x58b0, 0x00000800, 0x1),
RTW89_DECL_RFK_WM(0x5a00, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a04, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a08, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a0c, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a10, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a14, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a18, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a1c, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a20, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a24, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a28, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a2c, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a30, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a34, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a38, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a3c, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a40, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a44, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a48, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a4c, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a50, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a54, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a58, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a5c, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a60, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a64, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a68, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a6c, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a70, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a74, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a78, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a7c, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a80, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a84, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a88, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a8c, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a90, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a94, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a98, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5a9c, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5aa0, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5aa4, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5aa8, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5aac, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5ab0, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5ab4, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5ab8, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5abc, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5ac0, 0xffffffff, 0x00000000),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_dac_gain_defs_a);
static const struct rtw89_reg5_def rtw8852b_tssi_dac_gain_defs_b[] = {
RTW89_DECL_RFK_WM(0x78b0, 0x00000fff, 0x000),
RTW89_DECL_RFK_WM(0x78b0, 0x00000800, 0x1),
RTW89_DECL_RFK_WM(0x7a00, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a04, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a08, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a0c, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a10, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a14, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a18, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a1c, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a20, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a24, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a28, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a2c, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a30, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a34, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a38, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a3c, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a40, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a44, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a48, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a4c, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a50, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a54, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a58, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a5c, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a60, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a64, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a68, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a6c, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a70, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a74, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a78, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a7c, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a80, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a84, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a88, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a8c, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a90, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a94, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a98, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7a9c, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7aa0, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7aa4, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7aa8, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7aac, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7ab0, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7ab4, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7ab8, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7abc, 0xffffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7ac0, 0xffffffff, 0x00000000),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_dac_gain_defs_b);
static const struct rtw89_reg5_def rtw8852b_tssi_slope_a_defs_2g[] = {
RTW89_DECL_RFK_WM(0x5608, 0x07ffffff, 0x0801008),
RTW89_DECL_RFK_WM(0x560c, 0x07ffffff, 0x0201020),
RTW89_DECL_RFK_WM(0x5610, 0x07ffffff, 0x0201008),
RTW89_DECL_RFK_WM(0x5614, 0x07ffffff, 0x0804008),
RTW89_DECL_RFK_WM(0x5618, 0x07ffffff, 0x0201008),
RTW89_DECL_RFK_WM(0x561c, 0x000001ff, 0x008),
RTW89_DECL_RFK_WM(0x561c, 0xffff0000, 0x0808),
RTW89_DECL_RFK_WM(0x5620, 0xffffffff, 0x08081e28),
RTW89_DECL_RFK_WM(0x5624, 0xffffffff, 0x08080808),
RTW89_DECL_RFK_WM(0x5628, 0xffffffff, 0x08081e28),
RTW89_DECL_RFK_WM(0x562c, 0x0000ffff, 0x0808),
RTW89_DECL_RFK_WM(0x581c, 0x00100000, 0x1),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_slope_a_defs_2g);
static const struct rtw89_reg5_def rtw8852b_tssi_slope_a_defs_5g[] = {
RTW89_DECL_RFK_WM(0x5608, 0x07ffffff, 0x0201008),
RTW89_DECL_RFK_WM(0x560c, 0x07ffffff, 0x0201020),
RTW89_DECL_RFK_WM(0x5610, 0x07ffffff, 0x0201008),
RTW89_DECL_RFK_WM(0x5614, 0x07ffffff, 0x0201008),
RTW89_DECL_RFK_WM(0x5618, 0x07ffffff, 0x0201008),
RTW89_DECL_RFK_WM(0x561c, 0x000001ff, 0x008),
RTW89_DECL_RFK_WM(0x561c, 0xffff0000, 0x0808),
RTW89_DECL_RFK_WM(0x5620, 0xffffffff, 0x08081e08),
RTW89_DECL_RFK_WM(0x5624, 0xffffffff, 0x08080808),
RTW89_DECL_RFK_WM(0x5628, 0xffffffff, 0x08080808),
RTW89_DECL_RFK_WM(0x562c, 0x0000ffff, 0x0808),
RTW89_DECL_RFK_WM(0x581c, 0x00100000, 0x1),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_slope_a_defs_5g);
static const struct rtw89_reg5_def rtw8852b_tssi_slope_b_defs_2g[] = {
RTW89_DECL_RFK_WM(0x7608, 0x07ffffff, 0x0801008),
RTW89_DECL_RFK_WM(0x760c, 0x07ffffff, 0x0201020),
RTW89_DECL_RFK_WM(0x7610, 0x07ffffff, 0x0201008),
RTW89_DECL_RFK_WM(0x7614, 0x07ffffff, 0x0804008),
RTW89_DECL_RFK_WM(0x7618, 0x07ffffff, 0x0201008),
RTW89_DECL_RFK_WM(0x761c, 0x000001ff, 0x008),
RTW89_DECL_RFK_WM(0x761c, 0xffff0000, 0x0808),
RTW89_DECL_RFK_WM(0x7620, 0xffffffff, 0x08081e28),
RTW89_DECL_RFK_WM(0x7624, 0xffffffff, 0x08080808),
RTW89_DECL_RFK_WM(0x7628, 0xffffffff, 0x08081e28),
RTW89_DECL_RFK_WM(0x762c, 0x0000ffff, 0x0808),
RTW89_DECL_RFK_WM(0x781c, 0x00100000, 0x1),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_slope_b_defs_2g);
static const struct rtw89_reg5_def rtw8852b_tssi_slope_b_defs_5g[] = {
RTW89_DECL_RFK_WM(0x7608, 0x07ffffff, 0x0201008),
RTW89_DECL_RFK_WM(0x760c, 0x07ffffff, 0x0201020),
RTW89_DECL_RFK_WM(0x7610, 0x07ffffff, 0x0201008),
RTW89_DECL_RFK_WM(0x7614, 0x07ffffff, 0x0201008),
RTW89_DECL_RFK_WM(0x7618, 0x07ffffff, 0x0201008),
RTW89_DECL_RFK_WM(0x761c, 0x000001ff, 0x008),
RTW89_DECL_RFK_WM(0x761c, 0xffff0000, 0x0808),
RTW89_DECL_RFK_WM(0x7620, 0xffffffff, 0x08081e08),
RTW89_DECL_RFK_WM(0x7624, 0xffffffff, 0x08080808),
RTW89_DECL_RFK_WM(0x7628, 0xffffffff, 0x08080808),
RTW89_DECL_RFK_WM(0x762c, 0x0000ffff, 0x0808),
RTW89_DECL_RFK_WM(0x781c, 0x00100000, 0x1),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_slope_b_defs_5g);
static const struct rtw89_reg5_def rtw8852b_tssi_align_a_2g_all_defs[] = {
RTW89_DECL_RFK_WM(0x5604, 0x80000000, 0x1),
RTW89_DECL_RFK_WM(0x5600, 0x3fffffff, 0x3f2d2721),
RTW89_DECL_RFK_WM(0x5604, 0x003fffff, 0x010101),
RTW89_DECL_RFK_WM(0x5630, 0x3fffffff, 0x01ef27af),
RTW89_DECL_RFK_WM(0x5634, 0x3fffffff, 0x00000075),
RTW89_DECL_RFK_WM(0x5638, 0x000fffff, 0x00000),
RTW89_DECL_RFK_WM(0x563c, 0x3fffffff, 0x017f13ae),
RTW89_DECL_RFK_WM(0x5640, 0x3fffffff, 0x0000006e),
RTW89_DECL_RFK_WM(0x5644, 0x000fffff, 0x00000),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_a_2g_all_defs);
static const struct rtw89_reg5_def rtw8852b_tssi_align_a_2g_part_defs[] = {
RTW89_DECL_RFK_WM(0x5630, 0x3fffffff, 0x01ef27af),
RTW89_DECL_RFK_WM(0x5634, 0x3fffffff, 0x00000075),
RTW89_DECL_RFK_WM(0x563c, 0x3fffffff, 0x017f13ae),
RTW89_DECL_RFK_WM(0x5640, 0x3fffffff, 0x0000006e),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_a_2g_part_defs);
static const struct rtw89_reg5_def rtw8852b_tssi_align_a_5g1_all_defs[] = {
RTW89_DECL_RFK_WM(0x5604, 0x80000000, 0x1),
RTW89_DECL_RFK_WM(0x5600, 0x3fffffff, 0x3f2d2721),
RTW89_DECL_RFK_WM(0x5604, 0x003fffff, 0x010101),
RTW89_DECL_RFK_WM(0x5630, 0x3fffffff, 0x016037e7),
RTW89_DECL_RFK_WM(0x5634, 0x3fffffff, 0x0000006f),
RTW89_DECL_RFK_WM(0x5638, 0x000fffff, 0x00000),
RTW89_DECL_RFK_WM(0x563c, 0x3fffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5640, 0x3fffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5644, 0x000fffff, 0x00000),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_a_5g1_all_defs);
static const struct rtw89_reg5_def rtw8852b_tssi_align_a_5g1_part_defs[] = {
RTW89_DECL_RFK_WM(0x5630, 0x3fffffff, 0x016037e7),
RTW89_DECL_RFK_WM(0x5634, 0x3fffffff, 0x0000006f),
RTW89_DECL_RFK_WM(0x563c, 0x3fffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5640, 0x3fffffff, 0x00000000),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_a_5g1_part_defs);
static const struct rtw89_reg5_def rtw8852b_tssi_align_a_5g2_all_defs[] = {
RTW89_DECL_RFK_WM(0x5604, 0x80000000, 0x1),
RTW89_DECL_RFK_WM(0x5600, 0x3fffffff, 0x3f2d2721),
RTW89_DECL_RFK_WM(0x5604, 0x003fffff, 0x010101),
RTW89_DECL_RFK_WM(0x5630, 0x3fffffff, 0x01f053f1),
RTW89_DECL_RFK_WM(0x5634, 0x3fffffff, 0x00000070),
RTW89_DECL_RFK_WM(0x5638, 0x000fffff, 0x00000),
RTW89_DECL_RFK_WM(0x563c, 0x3fffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5640, 0x3fffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5644, 0x000fffff, 0x00000),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_a_5g2_all_defs);
static const struct rtw89_reg5_def rtw8852b_tssi_align_a_5g2_part_defs[] = {
RTW89_DECL_RFK_WM(0x5630, 0x3fffffff, 0x01f053f1),
RTW89_DECL_RFK_WM(0x5634, 0x3fffffff, 0x00000070),
RTW89_DECL_RFK_WM(0x563c, 0x3fffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5640, 0x3fffffff, 0x00000000),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_a_5g2_part_defs);
static const struct rtw89_reg5_def rtw8852b_tssi_align_a_5g3_all_defs[] = {
RTW89_DECL_RFK_WM(0x5604, 0x80000000, 0x1),
RTW89_DECL_RFK_WM(0x5600, 0x3fffffff, 0x3f2d2721),
RTW89_DECL_RFK_WM(0x5604, 0x003fffff, 0x010101),
RTW89_DECL_RFK_WM(0x5630, 0x3fffffff, 0x01c047ee),
RTW89_DECL_RFK_WM(0x5634, 0x3fffffff, 0x00000070),
RTW89_DECL_RFK_WM(0x5638, 0x000fffff, 0x00000),
RTW89_DECL_RFK_WM(0x563c, 0x3fffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5640, 0x3fffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5644, 0x000fffff, 0x00000),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_a_5g3_all_defs);
static const struct rtw89_reg5_def rtw8852b_tssi_align_a_5g3_part_defs[] = {
RTW89_DECL_RFK_WM(0x5630, 0x3fffffff, 0x01c047ee),
RTW89_DECL_RFK_WM(0x5634, 0x3fffffff, 0x00000070),
RTW89_DECL_RFK_WM(0x563c, 0x3fffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x5640, 0x3fffffff, 0x00000000),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_a_5g3_part_defs);
static const struct rtw89_reg5_def rtw8852b_tssi_align_b_2g_all_defs[] = {
RTW89_DECL_RFK_WM(0x7604, 0x80000000, 0x1),
RTW89_DECL_RFK_WM(0x7600, 0x3fffffff, 0x3f2d2721),
RTW89_DECL_RFK_WM(0x7604, 0x003fffff, 0x010101),
RTW89_DECL_RFK_WM(0x7630, 0x3fffffff, 0x01ff2bb5),
RTW89_DECL_RFK_WM(0x7634, 0x3fffffff, 0x00000078),
RTW89_DECL_RFK_WM(0x7638, 0x000fffff, 0x00000),
RTW89_DECL_RFK_WM(0x763c, 0x3fffffff, 0x018f2bb0),
RTW89_DECL_RFK_WM(0x7640, 0x3fffffff, 0x00000072),
RTW89_DECL_RFK_WM(0x7644, 0x000fffff, 0x00000),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_b_2g_all_defs);
static const struct rtw89_reg5_def rtw8852b_tssi_align_b_2g_part_defs[] = {
RTW89_DECL_RFK_WM(0x7630, 0x3fffffff, 0x01ff2bb5),
RTW89_DECL_RFK_WM(0x7634, 0x3fffffff, 0x00000078),
RTW89_DECL_RFK_WM(0x763c, 0x3fffffff, 0x018f2bb0),
RTW89_DECL_RFK_WM(0x7640, 0x3fffffff, 0x00000072),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_b_2g_part_defs);
static const struct rtw89_reg5_def rtw8852b_tssi_align_b_5g1_all_defs[] = {
RTW89_DECL_RFK_WM(0x7604, 0x80000000, 0x1),
RTW89_DECL_RFK_WM(0x7600, 0x3fffffff, 0x3f2d2721),
RTW89_DECL_RFK_WM(0x7604, 0x003fffff, 0x010101),
RTW89_DECL_RFK_WM(0x7630, 0x3fffffff, 0x009003da),
RTW89_DECL_RFK_WM(0x7634, 0x3fffffff, 0x00000069),
RTW89_DECL_RFK_WM(0x7638, 0x000fffff, 0x00000),
RTW89_DECL_RFK_WM(0x763c, 0x3fffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7640, 0x3fffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7644, 0x000fffff, 0x00000),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_b_5g1_all_defs);
static const struct rtw89_reg5_def rtw8852b_tssi_align_b_5g1_part_defs[] = {
RTW89_DECL_RFK_WM(0x7630, 0x3fffffff, 0x009003da),
RTW89_DECL_RFK_WM(0x7634, 0x3fffffff, 0x00000069),
RTW89_DECL_RFK_WM(0x763c, 0x3fffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7640, 0x3fffffff, 0x00000000),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_b_5g1_part_defs);
static const struct rtw89_reg5_def rtw8852b_tssi_align_b_5g2_all_defs[] = {
RTW89_DECL_RFK_WM(0x7604, 0x80000000, 0x1),
RTW89_DECL_RFK_WM(0x7600, 0x3fffffff, 0x3f2d2721),
RTW89_DECL_RFK_WM(0x7604, 0x003fffff, 0x010101),
RTW89_DECL_RFK_WM(0x7630, 0x3fffffff, 0x013027e6),
RTW89_DECL_RFK_WM(0x7634, 0x3fffffff, 0x00000069),
RTW89_DECL_RFK_WM(0x7638, 0x000fffff, 0x00000),
RTW89_DECL_RFK_WM(0x763c, 0x3fffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7640, 0x3fffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7644, 0x000fffff, 0x00000),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_b_5g2_all_defs);
static const struct rtw89_reg5_def rtw8852b_tssi_align_b_5g2_part_defs[] = {
RTW89_DECL_RFK_WM(0x7630, 0x3fffffff, 0x013027e6),
RTW89_DECL_RFK_WM(0x7634, 0x3fffffff, 0x00000069),
RTW89_DECL_RFK_WM(0x763c, 0x3fffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7640, 0x3fffffff, 0x00000000),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_b_5g2_part_defs);
static const struct rtw89_reg5_def rtw8852b_tssi_align_b_5g3_all_defs[] = {
RTW89_DECL_RFK_WM(0x7604, 0x80000000, 0x1),
RTW89_DECL_RFK_WM(0x7600, 0x3fffffff, 0x3f2d2721),
RTW89_DECL_RFK_WM(0x7604, 0x003fffff, 0x010101),
RTW89_DECL_RFK_WM(0x7630, 0x3fffffff, 0x009003da),
RTW89_DECL_RFK_WM(0x7634, 0x3fffffff, 0x00000069),
RTW89_DECL_RFK_WM(0x7638, 0x000fffff, 0x00000),
RTW89_DECL_RFK_WM(0x763c, 0x3fffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7640, 0x3fffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7644, 0x000fffff, 0x00000),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_b_5g3_all_defs);
static const struct rtw89_reg5_def rtw8852b_tssi_align_b_5g3_part_defs[] = {
RTW89_DECL_RFK_WM(0x7630, 0x3fffffff, 0x009003da),
RTW89_DECL_RFK_WM(0x7634, 0x3fffffff, 0x00000069),
RTW89_DECL_RFK_WM(0x763c, 0x3fffffff, 0x00000000),
RTW89_DECL_RFK_WM(0x7640, 0x3fffffff, 0x00000000),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_align_b_5g3_part_defs);
static const struct rtw89_reg5_def rtw8852b_tssi_slope_defs_a[] = {
RTW89_DECL_RFK_WM(0x5814, 0x00000800, 0x1),
RTW89_DECL_RFK_WM(0x581c, 0x20000000, 0x1),
RTW89_DECL_RFK_WM(0x5814, 0x20000000, 0x1),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_slope_defs_a);
static const struct rtw89_reg5_def rtw8852b_tssi_slope_defs_b[] = {
RTW89_DECL_RFK_WM(0x7814, 0x00000800, 0x1),
RTW89_DECL_RFK_WM(0x781c, 0x20000000, 0x1),
RTW89_DECL_RFK_WM(0x7814, 0x20000000, 0x1),
};
RTW89_DECLARE_RFK_TBL(rtw8852b_tssi_slope_defs_b);

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@ -0,0 +1,62 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2019-2020 Realtek Corporation
*/
#ifndef __RTW89_8852B_RFK_TABLE_H__
#define __RTW89_8852B_RFK_TABLE_H__
#include "phy.h"
extern const struct rtw89_rfk_tbl rtw8852b_afe_init_defs_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_check_addc_defs_a_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_check_addc_defs_b_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_check_dadc_en_defs_a_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_check_dadc_en_defs_b_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_check_dadc_dis_defs_a_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_check_dadc_dis_defs_b_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_dack_s0_1_defs_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_dack_s0_2_defs_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_dack_s0_3_defs_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_dack_s1_1_defs_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_dack_s1_2_defs_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_dack_s1_3_defs_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_dpk_afe_defs_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_dpk_afe_restore_defs_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_dpk_kip_defs_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_tssi_sys_defs_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_tssi_sys_a_defs_2g_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_tssi_sys_a_defs_5g_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_tssi_sys_b_defs_2g_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_tssi_sys_b_defs_5g_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_tssi_init_txpwr_defs_a_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_tssi_init_txpwr_defs_b_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_tssi_init_txpwr_he_tb_defs_a_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_tssi_init_txpwr_he_tb_defs_b_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_tssi_dck_defs_a_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_tssi_dck_defs_b_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_tssi_dac_gain_defs_a_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_tssi_dac_gain_defs_b_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_tssi_slope_a_defs_2g_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_tssi_slope_a_defs_5g_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_tssi_slope_b_defs_2g_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_tssi_slope_b_defs_5g_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_a_2g_all_defs_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_a_2g_part_defs_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_a_5g1_all_defs_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_a_5g1_part_defs_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_a_5g2_all_defs_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_a_5g2_part_defs_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_a_5g3_all_defs_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_a_5g3_part_defs_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_b_2g_all_defs_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_b_2g_part_defs_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_b_5g1_all_defs_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_b_5g1_part_defs_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_b_5g2_all_defs_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_b_5g2_part_defs_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_b_5g3_all_defs_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_tssi_align_b_5g3_part_defs_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_tssi_slope_defs_a_tbl;
extern const struct rtw89_rfk_tbl rtw8852b_tssi_slope_defs_b_tbl;
#endif

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@ -0,0 +1,30 @@
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2019-2020 Realtek Corporation
*/
#ifndef __RTW89_8852B_TABLE_H__
#define __RTW89_8852B_TABLE_H__
#include "core.h"
extern const struct rtw89_phy_table rtw89_8852b_phy_bb_table;
extern const struct rtw89_phy_table rtw89_8852b_phy_bb_gain_table;
extern const struct rtw89_phy_table rtw89_8852b_phy_radioa_table;
extern const struct rtw89_phy_table rtw89_8852b_phy_radiob_table;
extern const struct rtw89_phy_table rtw89_8852b_phy_nctl_table;
extern const struct rtw89_txpwr_table rtw89_8852b_byr_table;
extern const struct rtw89_txpwr_track_cfg rtw89_8852b_trk_cfg;
extern const u8 rtw89_8852b_tx_shape[RTW89_BAND_MAX][RTW89_RS_TX_SHAPE_NUM]
[RTW89_REGD_NUM];
extern const s8 rtw89_8852b_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
[RTW89_RS_LMT_NUM][RTW89_BF_NUM]
[RTW89_REGD_NUM][RTW89_2G_CH_NUM];
extern const s8 rtw89_8852b_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
[RTW89_RS_LMT_NUM][RTW89_BF_NUM]
[RTW89_REGD_NUM][RTW89_5G_CH_NUM];
extern const s8 rtw89_8852b_txpwr_lmt_ru_2g[RTW89_RU_NUM][RTW89_NTX_NUM]
[RTW89_REGD_NUM][RTW89_2G_CH_NUM];
extern const s8 rtw89_8852b_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
[RTW89_REGD_NUM][RTW89_5G_CH_NUM];
#endif

View File

@ -7,19 +7,83 @@
#include "pci.h" #include "pci.h"
#include "reg.h" #include "reg.h"
#include "rtw8852b.h"
static const struct rtw89_pci_info rtw8852b_pci_info = { static const struct rtw89_pci_info rtw8852b_pci_info = {
.txbd_trunc_mode = MAC_AX_BD_TRUNC,
.rxbd_trunc_mode = MAC_AX_BD_TRUNC,
.rxbd_mode = MAC_AX_RXBD_PKT,
.tag_mode = MAC_AX_TAG_MULTI,
.tx_burst = MAC_AX_TX_BURST_2048B,
.rx_burst = MAC_AX_RX_BURST_128B,
.wd_dma_idle_intvl = MAC_AX_WD_DMA_INTVL_256NS,
.wd_dma_act_intvl = MAC_AX_WD_DMA_INTVL_256NS,
.multi_tag_num = MAC_AX_TAG_NUM_8,
.lbc_en = MAC_AX_PCIE_ENABLE,
.lbc_tmr = MAC_AX_LBC_TMR_2MS,
.autok_en = MAC_AX_PCIE_DISABLE,
.io_rcy_en = MAC_AX_PCIE_DISABLE,
.io_rcy_tmr = MAC_AX_IO_RCY_ANA_TMR_6MS,
.init_cfg_reg = R_AX_PCIE_INIT_CFG1,
.txhci_en_bit = B_AX_TXHCI_EN,
.rxhci_en_bit = B_AX_RXHCI_EN,
.rxbd_mode_bit = B_AX_RXBD_MODE,
.exp_ctrl_reg = R_AX_PCIE_EXP_CTRL,
.max_tag_num_mask = B_AX_MAX_TAG_NUM,
.rxbd_rwptr_clr_reg = R_AX_RXBD_RWPTR_CLR,
.txbd_rwptr_clr2_reg = 0,
.dma_stop1 = {R_AX_PCIE_DMA_STOP1, B_AX_TX_STOP1_MASK_V1}, .dma_stop1 = {R_AX_PCIE_DMA_STOP1, B_AX_TX_STOP1_MASK_V1},
.dma_stop2 = {0}, .dma_stop2 = {0},
.dma_busy1 = {R_AX_PCIE_DMA_BUSY1, DMA_BUSY1_CHECK_V1}, .dma_busy1 = {R_AX_PCIE_DMA_BUSY1, DMA_BUSY1_CHECK_V1},
.dma_busy2_reg = 0, .dma_busy2_reg = 0,
.dma_busy3_reg = R_AX_PCIE_DMA_BUSY1, .dma_busy3_reg = R_AX_PCIE_DMA_BUSY1,
.rpwm_addr = R_AX_PCIE_HRPWM,
.cpwm_addr = R_AX_CPWM,
.tx_dma_ch_mask = BIT(RTW89_TXCH_ACH4) | BIT(RTW89_TXCH_ACH5) | .tx_dma_ch_mask = BIT(RTW89_TXCH_ACH4) | BIT(RTW89_TXCH_ACH5) |
BIT(RTW89_TXCH_ACH6) | BIT(RTW89_TXCH_ACH7) | BIT(RTW89_TXCH_ACH6) | BIT(RTW89_TXCH_ACH7) |
BIT(RTW89_TXCH_CH10) | BIT(RTW89_TXCH_CH11), BIT(RTW89_TXCH_CH10) | BIT(RTW89_TXCH_CH11),
.bd_idx_addr_low_power = NULL,
.dma_addr_set = &rtw89_pci_ch_dma_addr_set,
.ltr_set = rtw89_pci_ltr_set,
.fill_txaddr_info = rtw89_pci_fill_txaddr_info,
.config_intr_mask = rtw89_pci_config_intr_mask,
.enable_intr = rtw89_pci_enable_intr,
.disable_intr = rtw89_pci_disable_intr,
.recognize_intrs = rtw89_pci_recognize_intrs,
}; };
static const struct rtw89_driver_info rtw89_8852be_info = {
.chip = &rtw8852b_chip_info,
.bus = {
.pci = &rtw8852b_pci_info,
},
};
static const struct pci_device_id rtw89_8852be_id_table[] = {
{
PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0xb852),
.driver_data = (kernel_ulong_t)&rtw89_8852be_info,
},
{
PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0xb85b),
.driver_data = (kernel_ulong_t)&rtw89_8852be_info,
},
{},
};
MODULE_DEVICE_TABLE(pci, rtw89_8852be_id_table);
static struct pci_driver rtw89_8852be_driver = {
.name = "rtw89_8852be",
.id_table = rtw89_8852be_id_table,
.probe = rtw89_pci_probe,
.remove = rtw89_pci_remove,
.driver.pm = &rtw89_pm_ops,
};
module_pci_driver(rtw89_8852be_driver);
MODULE_AUTHOR("Realtek Corporation"); MODULE_AUTHOR("Realtek Corporation");
MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852BE driver"); MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852BE driver");
MODULE_LICENSE("Dual BSD/GPL"); MODULE_LICENSE("Dual BSD/GPL");

View File

@ -273,6 +273,9 @@ static int rtw8852c_pwr_on_func(struct rtw89_dev *rtwdev)
B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | B_AX_SCHEDULER_EN | B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | B_AX_SCHEDULER_EN |
B_AX_TMAC_EN | B_AX_RMAC_EN); B_AX_TMAC_EN | B_AX_RMAC_EN);
rtw89_write32_mask(rtwdev, R_AX_LED1_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_V1_MASK,
PINMUX_EESK_FUNC_SEL_BT_LOG);
return 0; return 0;
} }
@ -785,40 +788,12 @@ static const struct rtw8852c_bb_gain_op1db bb_gain_op1db_a = {
.mask_tia0_lna6 = 0xff000000, .mask_tia0_lna6 = 0xff000000,
}; };
static enum rtw89_phy_bb_gain_band
rtw8852c_mapping_gain_band(enum rtw89_subband subband)
{
switch (subband) {
default:
case RTW89_CH_2G:
return RTW89_BB_GAIN_BAND_2G;
case RTW89_CH_5G_BAND_1:
return RTW89_BB_GAIN_BAND_5G_L;
case RTW89_CH_5G_BAND_3:
return RTW89_BB_GAIN_BAND_5G_M;
case RTW89_CH_5G_BAND_4:
return RTW89_BB_GAIN_BAND_5G_H;
case RTW89_CH_6G_BAND_IDX0:
case RTW89_CH_6G_BAND_IDX1:
return RTW89_BB_GAIN_BAND_6G_L;
case RTW89_CH_6G_BAND_IDX2:
case RTW89_CH_6G_BAND_IDX3:
return RTW89_BB_GAIN_BAND_6G_M;
case RTW89_CH_6G_BAND_IDX4:
case RTW89_CH_6G_BAND_IDX5:
return RTW89_BB_GAIN_BAND_6G_H;
case RTW89_CH_6G_BAND_IDX6:
case RTW89_CH_6G_BAND_IDX7:
return RTW89_BB_GAIN_BAND_6G_UH;
}
}
static void rtw8852c_set_gain_error(struct rtw89_dev *rtwdev, static void rtw8852c_set_gain_error(struct rtw89_dev *rtwdev,
enum rtw89_subband subband, enum rtw89_subband subband,
enum rtw89_rf_path path) enum rtw89_rf_path path)
{ {
const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain;
u8 gain_band = rtw8852c_mapping_gain_band(subband); u8 gain_band = rtw89_subband_to_bb_gain_band(subband);
s32 val; s32 val;
u32 reg; u32 reg;
u32 mask; u32 mask;
@ -976,21 +951,7 @@ static void rtw8852c_set_gain_offset(struct rtw89_dev *rtwdev,
rtw89_phy_write32_mask(rtwdev, R_RPL_OFST, B_RPL_OFST_MASK, tmp & 0x7f); rtw89_phy_write32_mask(rtwdev, R_RPL_OFST, B_RPL_OFST_MASK, tmp & 0x7f);
} }
switch (chan->subband_type) { gain_band = rtw89_subband_to_gain_offset_band_of_ofdm(chan->subband_type);
default:
case RTW89_CH_2G:
gain_band = RTW89_GAIN_OFFSET_2G_OFDM;
break;
case RTW89_CH_5G_BAND_1:
gain_band = RTW89_GAIN_OFFSET_5G_LOW;
break;
case RTW89_CH_5G_BAND_3:
gain_band = RTW89_GAIN_OFFSET_5G_MID;
break;
case RTW89_CH_5G_BAND_4:
gain_band = RTW89_GAIN_OFFSET_5G_HIGH;
break;
}
offset_q0 = -efuse_gain->offset[path][gain_band]; offset_q0 = -efuse_gain->offset[path][gain_band];
offset_base_q4 = efuse_gain->offset_base[phy_idx]; offset_base_q4 = efuse_gain->offset_base[phy_idx];
@ -2006,75 +1967,6 @@ static void rtw8852c_set_txpwr_ref(struct rtw89_dev *rtwdev,
phy_idx); phy_idx);
} }
static void rtw8852c_set_txpwr_byrate(struct rtw89_dev *rtwdev,
const struct rtw89_chan *chan,
enum rtw89_phy_idx phy_idx)
{
u8 band = chan->band_type;
u8 ch = chan->channel;
static const u8 rs[] = {
RTW89_RS_CCK,
RTW89_RS_OFDM,
RTW89_RS_MCS,
RTW89_RS_HEDCM,
};
s8 tmp;
u8 i, j;
u32 val, shf, addr = R_AX_PWR_BY_RATE;
struct rtw89_rate_desc cur;
rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
"[TXPWR] set txpwr byrate with ch=%d\n", ch);
for (cur.nss = 0; cur.nss <= RTW89_NSS_2; cur.nss++) {
for (i = 0; i < ARRAY_SIZE(rs); i++) {
if (cur.nss >= rtw89_rs_nss_max[rs[i]])
continue;
val = 0;
cur.rs = rs[i];
for (j = 0; j < rtw89_rs_idx_max[rs[i]]; j++) {
cur.idx = j;
shf = (j % 4) * 8;
tmp = rtw89_phy_read_txpwr_byrate(rtwdev, band,
&cur);
val |= (tmp << shf);
if ((j + 1) % 4)
continue;
rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
val = 0;
addr += 4;
}
}
}
}
static void rtw8852c_set_txpwr_offset(struct rtw89_dev *rtwdev,
const struct rtw89_chan *chan,
enum rtw89_phy_idx phy_idx)
{
u8 band = chan->band_type;
struct rtw89_rate_desc desc = {
.nss = RTW89_NSS_1,
.rs = RTW89_RS_OFFSET,
};
u32 val = 0;
s8 v;
rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr offset\n");
for (desc.idx = 0; desc.idx < RTW89_RATE_OFFSET_MAX; desc.idx++) {
v = rtw89_phy_read_txpwr_byrate(rtwdev, band, &desc);
val |= ((v & 0xf) << (4 * desc.idx));
}
rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_OFST_CTRL,
GENMASK(19, 0), val);
}
static void rtw8852c_bb_set_tx_shape_dfir(struct rtw89_dev *rtwdev, static void rtw8852c_bb_set_tx_shape_dfir(struct rtw89_dev *rtwdev,
u8 tx_shape_idx, u8 tx_shape_idx,
enum rtw89_phy_idx phy_idx) enum rtw89_phy_idx phy_idx)
@ -2147,83 +2039,15 @@ static void rtw8852c_set_tx_shape(struct rtw89_dev *rtwdev,
tx_shape_ofdm); tx_shape_ofdm);
} }
static void rtw8852c_set_txpwr_limit(struct rtw89_dev *rtwdev,
const struct rtw89_chan *chan,
enum rtw89_phy_idx phy_idx)
{
#define __MAC_TXPWR_LMT_PAGE_SIZE 40
u8 ch = chan->channel;
u8 bw = chan->band_width;
struct rtw89_txpwr_limit lmt[NTX_NUM_8852C];
u32 addr, val;
const s8 *ptr;
u8 i, j;
rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
"[TXPWR] set txpwr limit with ch=%d bw=%d\n", ch, bw);
for (i = 0; i < NTX_NUM_8852C; i++) {
rtw89_phy_fill_txpwr_limit(rtwdev, chan, &lmt[i], i);
for (j = 0; j < __MAC_TXPWR_LMT_PAGE_SIZE; j += 4) {
addr = R_AX_PWR_LMT + j + __MAC_TXPWR_LMT_PAGE_SIZE * i;
ptr = (s8 *)&lmt[i] + j;
val = FIELD_PREP(GENMASK(7, 0), ptr[0]) |
FIELD_PREP(GENMASK(15, 8), ptr[1]) |
FIELD_PREP(GENMASK(23, 16), ptr[2]) |
FIELD_PREP(GENMASK(31, 24), ptr[3]);
rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
}
}
#undef __MAC_TXPWR_LMT_PAGE_SIZE
}
static void rtw8852c_set_txpwr_limit_ru(struct rtw89_dev *rtwdev,
const struct rtw89_chan *chan,
enum rtw89_phy_idx phy_idx)
{
#define __MAC_TXPWR_LMT_RU_PAGE_SIZE 24
u8 ch = chan->channel;
u8 bw = chan->band_width;
struct rtw89_txpwr_limit_ru lmt_ru[NTX_NUM_8852C];
u32 addr, val;
const s8 *ptr;
u8 i, j;
rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
"[TXPWR] set txpwr limit ru with ch=%d bw=%d\n", ch, bw);
for (i = 0; i < NTX_NUM_8852C; i++) {
rtw89_phy_fill_txpwr_limit_ru(rtwdev, chan, &lmt_ru[i], i);
for (j = 0; j < __MAC_TXPWR_LMT_RU_PAGE_SIZE; j += 4) {
addr = R_AX_PWR_RU_LMT + j +
__MAC_TXPWR_LMT_RU_PAGE_SIZE * i;
ptr = (s8 *)&lmt_ru[i] + j;
val = FIELD_PREP(GENMASK(7, 0), ptr[0]) |
FIELD_PREP(GENMASK(15, 8), ptr[1]) |
FIELD_PREP(GENMASK(23, 16), ptr[2]) |
FIELD_PREP(GENMASK(31, 24), ptr[3]);
rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
}
}
#undef __MAC_TXPWR_LMT_RU_PAGE_SIZE
}
static void rtw8852c_set_txpwr(struct rtw89_dev *rtwdev, static void rtw8852c_set_txpwr(struct rtw89_dev *rtwdev,
const struct rtw89_chan *chan, const struct rtw89_chan *chan,
enum rtw89_phy_idx phy_idx) enum rtw89_phy_idx phy_idx)
{ {
rtw8852c_set_txpwr_byrate(rtwdev, chan, phy_idx); rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx);
rtw8852c_set_txpwr_offset(rtwdev, chan, phy_idx); rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx);
rtw8852c_set_tx_shape(rtwdev, chan, phy_idx); rtw8852c_set_tx_shape(rtwdev, chan, phy_idx);
rtw8852c_set_txpwr_limit(rtwdev, chan, phy_idx); rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx);
rtw8852c_set_txpwr_limit_ru(rtwdev, chan, phy_idx); rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx);
} }
static void rtw8852c_set_txpwr_ctrl(struct rtw89_dev *rtwdev, static void rtw8852c_set_txpwr_ctrl(struct rtw89_dev *rtwdev,
@ -2818,19 +2642,6 @@ static const struct rtw89_btc_fbtc_mreg rtw89_btc_8852c_mon_reg[] = {
RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980), RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980),
}; };
static
void rtw8852c_btc_bt_aci_imp(struct rtw89_dev *rtwdev)
{
struct rtw89_btc *btc = &rtwdev->btc;
struct rtw89_btc_dm *dm = &btc->dm;
struct rtw89_btc_bt_info *bt = &btc->cx.bt;
struct rtw89_btc_bt_link_info *b = &bt->link_info;
/* fix LNA2 = level-5 for BT ACI issue at BTG */
if (btc->dm.wl_btg_rx && b->profile_cnt.now != 0)
dm->trx_para_level = 1;
}
static static
void rtw8852c_btc_update_bt_cnt(struct rtw89_dev *rtwdev) void rtw8852c_btc_update_bt_cnt(struct rtw89_dev *rtwdev)
{ {
@ -3027,7 +2838,6 @@ static const struct rtw89_chip_ops rtw8852c_chip_ops = {
.btc_set_wl_pri = rtw8852c_btc_set_wl_pri, .btc_set_wl_pri = rtw8852c_btc_set_wl_pri,
.btc_set_wl_txpwr_ctrl = rtw8852c_btc_set_wl_txpwr_ctrl, .btc_set_wl_txpwr_ctrl = rtw8852c_btc_set_wl_txpwr_ctrl,
.btc_get_bt_rssi = rtw8852c_btc_get_bt_rssi, .btc_get_bt_rssi = rtw8852c_btc_get_bt_rssi,
.btc_bt_aci_imp = rtw8852c_btc_bt_aci_imp,
.btc_update_bt_cnt = rtw8852c_btc_update_bt_cnt, .btc_update_bt_cnt = rtw8852c_btc_update_bt_cnt,
.btc_wl_s1_standby = rtw8852c_btc_wl_s1_standby, .btc_wl_s1_standby = rtw8852c_btc_wl_s1_standby,
.btc_set_wl_rx_gain = rtw8852c_btc_set_wl_rx_gain, .btc_set_wl_rx_gain = rtw8852c_btc_set_wl_rx_gain,

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@ -9,7 +9,6 @@
#define RF_PATH_NUM_8852C 2 #define RF_PATH_NUM_8852C 2
#define BB_PATH_NUM_8852C 2 #define BB_PATH_NUM_8852C 2
#define NTX_NUM_8852C 2
struct rtw8852c_u_efuse { struct rtw8852c_u_efuse {
u8 rsvd[0x38]; u8 rsvd[0x38];

View File

@ -22,8 +22,7 @@ static const u32 _tssi_de_mcs_5m[RF_PATH_NUM_8852C] = {0x5828, 0x7828};
static const u32 _tssi_de_mcs_10m[RF_PATH_NUM_8852C] = {0x5830, 0x7830}; static const u32 _tssi_de_mcs_10m[RF_PATH_NUM_8852C] = {0x5830, 0x7830};
static const u32 rtw8852c_backup_bb_regs[] = { static const u32 rtw8852c_backup_bb_regs[] = {
0x813c, 0x8124, 0x8120, 0xc0d4, 0xc0d8, 0xc0e8, 0x823c, 0x8224, 0x8220, 0x8120, 0xc0d4, 0xc0d8, 0xc0e8, 0x8220, 0xc1d4, 0xc1d8, 0xc1e8
0xc1d4, 0xc1d8, 0xc1e8
}; };
static const u32 rtw8852c_backup_rf_regs[] = { static const u32 rtw8852c_backup_rf_regs[] = {
@ -1667,7 +1666,7 @@ static u8 _dpk_one_shot(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val == 0x55, ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val == 0x55,
10, 20000, false, rtwdev, 0xbff8, MASKBYTE0); 10, 20000, false, rtwdev, 0xbff8, MASKBYTE0);
mdelay(10); udelay(10);
rtw89_phy_write32_clr(rtwdev, R_NCTL_N1, MASKBYTE0); rtw89_phy_write32_clr(rtwdev, R_NCTL_N1, MASKBYTE0);
rtw89_debug(rtwdev, RTW89_DBG_RFK, rtw89_debug(rtwdev, RTW89_DBG_RFK,

File diff suppressed because it is too large Load Diff

View File

@ -1958,6 +1958,7 @@ static int rsi_mac80211_resume(struct ieee80211_hw *hw)
static const struct ieee80211_ops mac80211_ops = { static const struct ieee80211_ops mac80211_ops = {
.tx = rsi_mac80211_tx, .tx = rsi_mac80211_tx,
.wake_tx_queue = ieee80211_handle_wake_tx_queue,
.start = rsi_mac80211_start, .start = rsi_mac80211_start,
.stop = rsi_mac80211_stop, .stop = rsi_mac80211_stop,
.add_interface = rsi_mac80211_add_interface, .add_interface = rsi_mac80211_add_interface,

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@ -128,6 +128,7 @@ static const struct ieee80211_ops wfx_ops = {
.remove_interface = wfx_remove_interface, .remove_interface = wfx_remove_interface,
.config = wfx_config, .config = wfx_config,
.tx = wfx_tx, .tx = wfx_tx,
.wake_tx_queue = ieee80211_handle_wake_tx_queue,
.join_ibss = wfx_join_ibss, .join_ibss = wfx_join_ibss,
.leave_ibss = wfx_leave_ibss, .leave_ibss = wfx_leave_ibss,
.conf_tx = wfx_conf_tx, .conf_tx = wfx_conf_tx,

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@ -209,6 +209,7 @@ static const struct ieee80211_ops cw1200_ops = {
.remove_interface = cw1200_remove_interface, .remove_interface = cw1200_remove_interface,
.change_interface = cw1200_change_interface, .change_interface = cw1200_change_interface,
.tx = cw1200_tx, .tx = cw1200_tx,
.wake_tx_queue = ieee80211_handle_wake_tx_queue,
.hw_scan = cw1200_hw_scan, .hw_scan = cw1200_hw_scan,
.set_tim = cw1200_set_tim, .set_tim = cw1200_set_tim,
.sta_notify = cw1200_sta_notify, .sta_notify = cw1200_sta_notify,

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@ -1359,6 +1359,7 @@ static const struct ieee80211_ops wl1251_ops = {
.prepare_multicast = wl1251_op_prepare_multicast, .prepare_multicast = wl1251_op_prepare_multicast,
.configure_filter = wl1251_op_configure_filter, .configure_filter = wl1251_op_configure_filter,
.tx = wl1251_op_tx, .tx = wl1251_op_tx,
.wake_tx_queue = ieee80211_handle_wake_tx_queue,
.set_key = wl1251_op_set_key, .set_key = wl1251_op_set_key,
.hw_scan = wl1251_op_hw_scan, .hw_scan = wl1251_op_hw_scan,
.bss_info_changed = wl1251_op_bss_info_changed, .bss_info_changed = wl1251_op_bss_info_changed,

View File

@ -5942,6 +5942,7 @@ static const struct ieee80211_ops wl1271_ops = {
.prepare_multicast = wl1271_op_prepare_multicast, .prepare_multicast = wl1271_op_prepare_multicast,
.configure_filter = wl1271_op_configure_filter, .configure_filter = wl1271_op_configure_filter,
.tx = wl1271_op_tx, .tx = wl1271_op_tx,
.wake_tx_queue = ieee80211_handle_wake_tx_queue,
.set_key = wlcore_op_set_key, .set_key = wlcore_op_set_key,
.hw_scan = wl1271_op_hw_scan, .hw_scan = wl1271_op_hw_scan,
.cancel_hw_scan = wl1271_op_cancel_hw_scan, .cancel_hw_scan = wl1271_op_cancel_hw_scan,

View File

@ -1344,6 +1344,7 @@ static u64 zd_op_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
static const struct ieee80211_ops zd_ops = { static const struct ieee80211_ops zd_ops = {
.tx = zd_op_tx, .tx = zd_op_tx,
.wake_tx_queue = ieee80211_handle_wake_tx_queue,
.start = zd_op_start, .start = zd_op_start,
.stop = zd_op_stop, .stop = zd_op_stop,
.add_interface = zd_op_add_interface, .add_interface = zd_op_add_interface,

View File

@ -1685,6 +1685,7 @@ static void vnt_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
static const struct ieee80211_ops vnt_mac_ops = { static const struct ieee80211_ops vnt_mac_ops = {
.tx = vnt_tx_80211, .tx = vnt_tx_80211,
.wake_tx_queue = ieee80211_handle_wake_tx_queue,
.start = vnt_start, .start = vnt_start,
.stop = vnt_stop, .stop = vnt_stop,
.add_interface = vnt_add_interface, .add_interface = vnt_add_interface,

View File

@ -957,6 +957,7 @@ static void vnt_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
static const struct ieee80211_ops vnt_mac_ops = { static const struct ieee80211_ops vnt_mac_ops = {
.tx = vnt_tx_80211, .tx = vnt_tx_80211,
.wake_tx_queue = ieee80211_handle_wake_tx_queue,
.start = vnt_start, .start = vnt_start,
.stop = vnt_stop, .stop = vnt_stop,
.add_interface = vnt_add_interface, .add_interface = vnt_add_interface,

View File

@ -4573,18 +4573,17 @@ static inline u8 ieee80211_mle_common_size(const u8 *data)
switch (u16_get_bits(control, IEEE80211_ML_CONTROL_TYPE)) { switch (u16_get_bits(control, IEEE80211_ML_CONTROL_TYPE)) {
case IEEE80211_ML_CONTROL_TYPE_BASIC: case IEEE80211_ML_CONTROL_TYPE_BASIC:
common += sizeof(struct ieee80211_mle_basic_common_info);
break;
case IEEE80211_ML_CONTROL_TYPE_PREQ: case IEEE80211_ML_CONTROL_TYPE_PREQ:
common += sizeof(struct ieee80211_mle_preq_common_info); case IEEE80211_ML_CONTROL_TYPE_TDLS:
/*
* The length is the first octet pointed by mle->variable so no
* need to add anything
*/
break; break;
case IEEE80211_ML_CONTROL_TYPE_RECONF: case IEEE80211_ML_CONTROL_TYPE_RECONF:
if (control & IEEE80211_MLC_RECONF_PRES_MLD_MAC_ADDR) if (control & IEEE80211_MLC_RECONF_PRES_MLD_MAC_ADDR)
common += ETH_ALEN; common += ETH_ALEN;
return common; return common;
case IEEE80211_ML_CONTROL_TYPE_TDLS:
common += sizeof(struct ieee80211_mle_tdls_common_info);
break;
case IEEE80211_ML_CONTROL_TYPE_PRIO_ACCESS: case IEEE80211_ML_CONTROL_TYPE_PRIO_ACCESS:
if (control & IEEE80211_MLC_PRIO_ACCESS_PRES_AP_MLD_MAC_ADDR) if (control & IEEE80211_MLC_PRIO_ACCESS_PRES_AP_MLD_MAC_ADDR)
common += ETH_ALEN; common += ETH_ALEN;
@ -4594,7 +4593,7 @@ static inline u8 ieee80211_mle_common_size(const u8 *data)
return 0; return 0;
} }
return common + mle->variable[0]; return sizeof(*mle) + common + mle->variable[0];
} }
/** /**
@ -4602,7 +4601,7 @@ static inline u8 ieee80211_mle_common_size(const u8 *data)
* @data: pointer to the element data * @data: pointer to the element data
* @len: length of the containing element * @len: length of the containing element
*/ */
static inline bool ieee80211_mle_size_ok(const u8 *data, u8 len) static inline bool ieee80211_mle_size_ok(const u8 *data, size_t len)
{ {
const struct ieee80211_multi_link_elem *mle = (const void *)data; const struct ieee80211_multi_link_elem *mle = (const void *)data;
u8 fixed = sizeof(*mle); u8 fixed = sizeof(*mle);
@ -4667,6 +4666,7 @@ static inline bool ieee80211_mle_size_ok(const u8 *data, u8 len)
enum ieee80211_mle_subelems { enum ieee80211_mle_subelems {
IEEE80211_MLE_SUBELEM_PER_STA_PROFILE = 0, IEEE80211_MLE_SUBELEM_PER_STA_PROFILE = 0,
IEEE80211_MLE_SUBELEM_FRAGMENT = 254,
}; };
#define IEEE80211_MLE_STA_CONTROL_LINK_ID 0x000f #define IEEE80211_MLE_STA_CONTROL_LINK_ID 0x000f
@ -4685,6 +4685,46 @@ struct ieee80211_mle_per_sta_profile {
u8 variable[]; u8 variable[];
} __packed; } __packed;
/**
* ieee80211_mle_sta_prof_size_ok - validate multi-link element sta profile size
* @data: pointer to the sub element data
* @len: length of the containing sub element
*/
static inline bool ieee80211_mle_sta_prof_size_ok(const u8 *data, size_t len)
{
const struct ieee80211_mle_per_sta_profile *prof = (const void *)data;
u16 control;
u8 fixed = sizeof(*prof);
u8 info_len = 1;
if (len < fixed)
return false;
control = le16_to_cpu(prof->control);
if (control & IEEE80211_MLE_STA_CONTROL_STA_MAC_ADDR_PRESENT)
info_len += 6;
if (control & IEEE80211_MLE_STA_CONTROL_BEACON_INT_PRESENT)
info_len += 2;
if (control & IEEE80211_MLE_STA_CONTROL_TSF_OFFS_PRESENT)
info_len += 8;
if (control & IEEE80211_MLE_STA_CONTROL_DTIM_INFO_PRESENT)
info_len += 2;
if (control & IEEE80211_MLE_STA_CONTROL_BSS_PARAM_CHANGE_CNT_PRESENT)
info_len += 1;
if (control & IEEE80211_MLE_STA_CONTROL_COMPLETE_PROFILE &&
control & IEEE80211_MLE_STA_CONTROL_NSTR_BITMAP_SIZE) {
if (control & IEEE80211_MLE_STA_CONTROL_NSTR_BITMAP_SIZE)
info_len += 2;
else
info_len += 1;
}
return prof->sta_info_len >= info_len &&
fixed + prof->sta_info_len <= len;
}
#define for_each_mle_subelement(_elem, _data, _len) \ #define for_each_mle_subelement(_elem, _data, _len) \
if (ieee80211_mle_size_ok(_data, _len)) \ if (ieee80211_mle_size_ok(_data, _len)) \
for_each_element(_elem, \ for_each_element(_elem, \

View File

@ -2105,6 +2105,7 @@ struct mpath_info {
* *
* Used to change BSS parameters (mainly for AP mode). * Used to change BSS parameters (mainly for AP mode).
* *
* @link_id: link_id or -1 for non-MLD
* @use_cts_prot: Whether to use CTS protection * @use_cts_prot: Whether to use CTS protection
* (0 = no, 1 = yes, -1 = do not change) * (0 = no, 1 = yes, -1 = do not change)
* @use_short_preamble: Whether the use of short preambles is allowed * @use_short_preamble: Whether the use of short preambles is allowed
@ -2122,6 +2123,7 @@ struct mpath_info {
* @p2p_opp_ps: P2P opportunistic PS (-1 = no change) * @p2p_opp_ps: P2P opportunistic PS (-1 = no change)
*/ */
struct bss_parameters { struct bss_parameters {
int link_id;
int use_cts_prot; int use_cts_prot;
int use_short_preamble; int use_short_preamble;
int use_short_slot_time; int use_short_slot_time;
@ -6933,6 +6935,8 @@ void cfg80211_auth_timeout(struct net_device *dev, const u8 *addr);
* @ap_mld_addr: AP MLD address (in case of MLO) * @ap_mld_addr: AP MLD address (in case of MLO)
* @links: per-link information indexed by link ID, use links[0] for * @links: per-link information indexed by link ID, use links[0] for
* non-MLO connections * non-MLO connections
* @links.status: Set this (along with a BSS pointer) for links that
* were rejected by the AP.
*/ */
struct cfg80211_rx_assoc_resp { struct cfg80211_rx_assoc_resp {
const u8 *buf; const u8 *buf;
@ -6944,6 +6948,7 @@ struct cfg80211_rx_assoc_resp {
struct { struct {
const u8 *addr; const u8 *addr;
struct cfg80211_bss *bss; struct cfg80211_bss *bss;
u16 status;
} links[IEEE80211_MLD_MAX_NUM_LINKS]; } links[IEEE80211_MLD_MAX_NUM_LINKS];
}; };
@ -7454,6 +7459,9 @@ struct cfg80211_fils_resp_params {
* if the bss is expired during the connection, esp. for those drivers * if the bss is expired during the connection, esp. for those drivers
* implementing connect op. Only one parameter among @bssid and @bss needs * implementing connect op. Only one parameter among @bssid and @bss needs
* to be specified. * to be specified.
* @links.status: per-link status code, to report a status code that's not
* %WLAN_STATUS_SUCCESS for a given link, it must also be in the
* @valid_links bitmap and may have a BSS pointer (which is then released)
*/ */
struct cfg80211_connect_resp_params { struct cfg80211_connect_resp_params {
int status; int status;
@ -7470,6 +7478,7 @@ struct cfg80211_connect_resp_params {
const u8 *addr; const u8 *addr;
const u8 *bssid; const u8 *bssid;
struct cfg80211_bss *bss; struct cfg80211_bss *bss;
u16 status;
} links[IEEE80211_MLD_MAX_NUM_LINKS]; } links[IEEE80211_MLD_MAX_NUM_LINKS];
}; };
@ -7674,6 +7683,8 @@ void cfg80211_roamed(struct net_device *dev, struct cfg80211_roam_info *info,
* *
* @dev: network device * @dev: network device
* @bssid: the BSSID of the AP * @bssid: the BSSID of the AP
* @td_bitmap: transition disable policy
* @td_bitmap_len: Length of transition disable policy
* @gfp: allocation flags * @gfp: allocation flags
* *
* This function should be called by a driver that supports 4 way handshake * This function should be called by a driver that supports 4 way handshake
@ -7684,7 +7695,7 @@ void cfg80211_roamed(struct net_device *dev, struct cfg80211_roam_info *info,
* indicate the 802.11 association. * indicate the 802.11 association.
*/ */
void cfg80211_port_authorized(struct net_device *dev, const u8 *bssid, void cfg80211_port_authorized(struct net_device *dev, const u8 *bssid,
gfp_t gfp); const u8* td_bitmap, u8 td_bitmap_len, gfp_t gfp);
/** /**
* cfg80211_disconnected - notify cfg80211 that connection was dropped * cfg80211_disconnected - notify cfg80211 that connection was dropped

View File

@ -89,15 +89,13 @@
/** /**
* DOC: mac80211 software tx queueing * DOC: mac80211 software tx queueing
* *
* mac80211 provides an optional intermediate queueing implementation designed * mac80211 uses an intermediate queueing implementation, designed to allow the
* to allow the driver to keep hardware queues short and provide some fairness * driver to keep hardware queues short and to provide some fairness between
* between different stations/interfaces. * different stations/interfaces.
* In this model, the driver pulls data frames from the mac80211 queue instead
* of letting mac80211 push them via drv_tx().
* Other frames (e.g. control or management) are still pushed using drv_tx().
* *
* Drivers indicate that they use this model by implementing the .wake_tx_queue * Drivers must provide the .wake_tx_queue driver operation by either
* driver operation. * linking it to ieee80211_handle_wake_tx_queue() or implementing a custom
* handler.
* *
* Intermediate queues (struct ieee80211_txq) are kept per-sta per-tid, with * Intermediate queues (struct ieee80211_txq) are kept per-sta per-tid, with
* another per-sta for non-data/non-mgmt and bufferable management frames, and * another per-sta for non-data/non-mgmt and bufferable management frames, and
@ -106,9 +104,12 @@
* The driver is expected to initialize its private per-queue data for stations * The driver is expected to initialize its private per-queue data for stations
* and interfaces in the .add_interface and .sta_add ops. * and interfaces in the .add_interface and .sta_add ops.
* *
* The driver can't access the queue directly. To dequeue a frame from a * The driver can't access the internal TX queues (iTXQs) directly.
* txq, it calls ieee80211_tx_dequeue(). Whenever mac80211 adds a new frame to a * Whenever mac80211 adds a new frame to a queue, it calls the .wake_tx_queue
* queue, it calls the .wake_tx_queue driver op. * driver op.
* Drivers implementing a custom .wake_tx_queue op can get them by calling
* ieee80211_tx_dequeue(). Drivers using ieee80211_handle_wake_tx_queue() will
* simply get the individual frames pushed via the .tx driver operation.
* *
* Drivers can optionally delegate responsibility for scheduling queues to * Drivers can optionally delegate responsibility for scheduling queues to
* mac80211, to take advantage of airtime fairness accounting. In this case, to * mac80211, to take advantage of airtime fairness accounting. In this case, to
@ -1826,7 +1827,7 @@ struct ieee80211_vif_cfg {
* for this interface. * for this interface.
* @drv_priv: data area for driver use, will always be aligned to * @drv_priv: data area for driver use, will always be aligned to
* sizeof(void \*). * sizeof(void \*).
* @txq: the multicast data TX queue (if driver uses the TXQ abstraction) * @txq: the multicast data TX queue
* @txqs_stopped: per AC flag to indicate that intermediate TXQs are stopped, * @txqs_stopped: per AC flag to indicate that intermediate TXQs are stopped,
* protected by fq->lock. * protected by fq->lock.
* @offload_flags: 802.3 -> 802.11 enapsulation offload flags, see * @offload_flags: 802.3 -> 802.11 enapsulation offload flags, see
@ -1915,6 +1916,10 @@ static inline bool lockdep_vif_mutex_held(struct ieee80211_vif *vif)
rcu_dereference_protected((vif)->link_conf[link_id], \ rcu_dereference_protected((vif)->link_conf[link_id], \
lockdep_vif_mutex_held(vif)) lockdep_vif_mutex_held(vif))
#define link_conf_dereference_check(vif, link_id) \
rcu_dereference_check((vif)->link_conf[link_id], \
lockdep_vif_mutex_held(vif))
/** /**
* enum ieee80211_key_flags - key flags * enum ieee80211_key_flags - key flags
* *
@ -2176,6 +2181,7 @@ struct ieee80211_sta_aggregates {
* All link specific info for a STA link for a non MLD STA(single) * All link specific info for a STA link for a non MLD STA(single)
* or a MLD STA(multiple entries) are stored here. * or a MLD STA(multiple entries) are stored here.
* *
* @sta: reference to owning STA
* @addr: MAC address of the Link STA. For non-MLO STA this is same as the addr * @addr: MAC address of the Link STA. For non-MLO STA this is same as the addr
* in ieee80211_sta. For MLO Link STA this addr can be same or different * in ieee80211_sta. For MLO Link STA this addr can be same or different
* from addr in ieee80211_sta (representing MLD STA addr) * from addr in ieee80211_sta (representing MLD STA addr)
@ -2196,6 +2202,8 @@ struct ieee80211_sta_aggregates {
* *
*/ */
struct ieee80211_link_sta { struct ieee80211_link_sta {
struct ieee80211_sta *sta;
u8 addr[ETH_ALEN]; u8 addr[ETH_ALEN];
u8 link_id; u8 link_id;
enum ieee80211_smps_mode smps_mode; enum ieee80211_smps_mode smps_mode;
@ -2252,8 +2260,8 @@ struct ieee80211_link_sta {
* For non MLO STA it will point to the deflink data. For MLO STA * For non MLO STA it will point to the deflink data. For MLO STA
* ieee80211_sta_recalc_aggregates() must be called to update it. * ieee80211_sta_recalc_aggregates() must be called to update it.
* @support_p2p_ps: indicates whether the STA supports P2P PS mechanism or not. * @support_p2p_ps: indicates whether the STA supports P2P PS mechanism or not.
* @txq: per-TID data TX queues (if driver uses the TXQ abstraction); note that * @txq: per-TID data TX queues; note that the last entry (%IEEE80211_NUM_TIDS)
* the last entry (%IEEE80211_NUM_TIDS) is used for non-data frames * is used for non-data frames
* @deflink: This holds the default link STA information, for non MLO STA all link * @deflink: This holds the default link STA information, for non MLO STA all link
* specific STA information is accessed through @deflink or through * specific STA information is accessed through @deflink or through
* link[0] which points to address of @deflink. For MLO Link STA * link[0] which points to address of @deflink. For MLO Link STA
@ -2308,6 +2316,10 @@ static inline bool lockdep_sta_mutex_held(struct ieee80211_sta *pubsta)
rcu_dereference_protected((sta)->link[link_id], \ rcu_dereference_protected((sta)->link[link_id], \
lockdep_sta_mutex_held(sta)) lockdep_sta_mutex_held(sta))
#define link_sta_dereference_check(sta, link_id) \
rcu_dereference_check((sta)->link[link_id], \
lockdep_sta_mutex_held(sta))
#define for_each_sta_active_link(vif, sta, link_sta, link_id) \ #define for_each_sta_active_link(vif, sta, link_sta, link_id) \
for (link_id = 0; link_id < ARRAY_SIZE((sta)->link); link_id++) \ for (link_id = 0; link_id < ARRAY_SIZE((sta)->link); link_id++) \
if ((!(vif)->active_links || \ if ((!(vif)->active_links || \
@ -3787,6 +3799,13 @@ struct ieee80211_prep_tx_info {
* should be within a CONFIG_MAC80211_DEBUGFS conditional. This * should be within a CONFIG_MAC80211_DEBUGFS conditional. This
* callback can sleep. * callback can sleep.
* *
* @link_sta_add_debugfs: Drivers can use this callback to add debugfs files
* when a link is added to a mac80211 station. This callback
* should be within a CPTCFG_MAC80211_DEBUGFS conditional. This
* callback can sleep.
* For non-MLO the callback will be called once for the deflink with the
* station's directory rather than a separate subdirectory.
*
* @sta_notify: Notifies low level driver about power state transition of an * @sta_notify: Notifies low level driver about power state transition of an
* associated station, AP, IBSS/WDS/mesh peer etc. For a VIF operating * associated station, AP, IBSS/WDS/mesh peer etc. For a VIF operating
* in AP mode, this callback will not be called when the flag * in AP mode, this callback will not be called when the flag
@ -4257,6 +4276,10 @@ struct ieee80211_ops {
struct ieee80211_vif *vif, struct ieee80211_vif *vif,
struct ieee80211_sta *sta, struct ieee80211_sta *sta,
struct dentry *dir); struct dentry *dir);
void (*link_sta_add_debugfs)(struct ieee80211_hw *hw,
struct ieee80211_vif *vif,
struct ieee80211_link_sta *link_sta,
struct dentry *dir);
#endif #endif
void (*sta_notify)(struct ieee80211_hw *hw, struct ieee80211_vif *vif, void (*sta_notify)(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
enum sta_notify_cmd, struct ieee80211_sta *sta); enum sta_notify_cmd, struct ieee80211_sta *sta);
@ -5691,7 +5714,7 @@ void ieee80211_key_replay(struct ieee80211_key_conf *keyconf);
* @hw: pointer as obtained from ieee80211_alloc_hw(). * @hw: pointer as obtained from ieee80211_alloc_hw().
* @queue: queue number (counted from zero). * @queue: queue number (counted from zero).
* *
* Drivers should use this function instead of netif_wake_queue. * Drivers must use this function instead of netif_wake_queue.
*/ */
void ieee80211_wake_queue(struct ieee80211_hw *hw, int queue); void ieee80211_wake_queue(struct ieee80211_hw *hw, int queue);
@ -5700,7 +5723,7 @@ void ieee80211_wake_queue(struct ieee80211_hw *hw, int queue);
* @hw: pointer as obtained from ieee80211_alloc_hw(). * @hw: pointer as obtained from ieee80211_alloc_hw().
* @queue: queue number (counted from zero). * @queue: queue number (counted from zero).
* *
* Drivers should use this function instead of netif_stop_queue. * Drivers must use this function instead of netif_stop_queue.
*/ */
void ieee80211_stop_queue(struct ieee80211_hw *hw, int queue); void ieee80211_stop_queue(struct ieee80211_hw *hw, int queue);
@ -5709,7 +5732,7 @@ void ieee80211_stop_queue(struct ieee80211_hw *hw, int queue);
* @hw: pointer as obtained from ieee80211_alloc_hw(). * @hw: pointer as obtained from ieee80211_alloc_hw().
* @queue: queue number (counted from zero). * @queue: queue number (counted from zero).
* *
* Drivers should use this function instead of netif_stop_queue. * Drivers must use this function instead of netif_queue_stopped.
* *
* Return: %true if the queue is stopped. %false otherwise. * Return: %true if the queue is stopped. %false otherwise.
*/ */
@ -5720,7 +5743,7 @@ int ieee80211_queue_stopped(struct ieee80211_hw *hw, int queue);
* ieee80211_stop_queues - stop all queues * ieee80211_stop_queues - stop all queues
* @hw: pointer as obtained from ieee80211_alloc_hw(). * @hw: pointer as obtained from ieee80211_alloc_hw().
* *
* Drivers should use this function instead of netif_stop_queue. * Drivers must use this function instead of netif_tx_stop_all_queues.
*/ */
void ieee80211_stop_queues(struct ieee80211_hw *hw); void ieee80211_stop_queues(struct ieee80211_hw *hw);
@ -5728,7 +5751,7 @@ void ieee80211_stop_queues(struct ieee80211_hw *hw);
* ieee80211_wake_queues - wake all queues * ieee80211_wake_queues - wake all queues
* @hw: pointer as obtained from ieee80211_alloc_hw(). * @hw: pointer as obtained from ieee80211_alloc_hw().
* *
* Drivers should use this function instead of netif_wake_queue. * Drivers must use this function instead of netif_tx_wake_all_queues.
*/ */
void ieee80211_wake_queues(struct ieee80211_hw *hw); void ieee80211_wake_queues(struct ieee80211_hw *hw);
@ -6949,6 +6972,18 @@ static inline struct sk_buff *ieee80211_tx_dequeue_ni(struct ieee80211_hw *hw,
return skb; return skb;
} }
/**
* ieee80211_handle_wake_tx_queue - mac80211 handler for wake_tx_queue callback
*
* @hw: pointer as obtained from wake_tx_queue() callback().
* @txq: pointer as obtained from wake_tx_queue() callback().
*
* Drivers can use this function for the mandatory mac80211 wake_tx_queue
* callback in struct ieee80211_ops. They should not call this function.
*/
void ieee80211_handle_wake_tx_queue(struct ieee80211_hw *hw,
struct ieee80211_txq *txq);
/** /**
* ieee80211_next_txq - get next tx queue to pull packets from * ieee80211_next_txq - get next tx queue to pull packets from
* *

View File

@ -2749,6 +2749,8 @@ enum nl80211_commands {
* When used with %NL80211_CMD_FRAME_TX_STATUS, indicates the ack RX * When used with %NL80211_CMD_FRAME_TX_STATUS, indicates the ack RX
* timestamp. When used with %NL80211_CMD_FRAME RX notification, indicates * timestamp. When used with %NL80211_CMD_FRAME RX notification, indicates
* the incoming frame RX timestamp. * the incoming frame RX timestamp.
* @NL80211_ATTR_TD_BITMAP: Transition Disable bitmap, for subsequent
* (re)associations.
* @NUM_NL80211_ATTR: total number of nl80211_attrs available * @NUM_NL80211_ATTR: total number of nl80211_attrs available
* @NL80211_ATTR_MAX: highest attribute number currently defined * @NL80211_ATTR_MAX: highest attribute number currently defined
* @__NL80211_ATTR_AFTER_LAST: internal use * @__NL80211_ATTR_AFTER_LAST: internal use
@ -3276,6 +3278,7 @@ enum nl80211_attrs {
NL80211_ATTR_TX_HW_TIMESTAMP, NL80211_ATTR_TX_HW_TIMESTAMP,
NL80211_ATTR_RX_HW_TIMESTAMP, NL80211_ATTR_RX_HW_TIMESTAMP,
NL80211_ATTR_TD_BITMAP,
/* add attributes here, update the policy in nl80211.c */ /* add attributes here, update the policy in nl80211.c */

View File

@ -183,34 +183,15 @@ static void ieee80211_add_addbaext(struct ieee80211_sub_if_data *sdata,
const struct ieee80211_addba_ext_ie *req, const struct ieee80211_addba_ext_ie *req,
u16 buf_size) u16 buf_size)
{ {
struct ieee80211_supported_band *sband;
struct ieee80211_addba_ext_ie *resp; struct ieee80211_addba_ext_ie *resp;
const struct ieee80211_sta_he_cap *he_cap;
u8 frag_level, cap_frag_level;
u8 *pos; u8 *pos;
sband = ieee80211_get_sband(sdata);
if (!sband)
return;
he_cap = ieee80211_get_he_iftype_cap(sband,
ieee80211_vif_type_p2p(&sdata->vif));
if (!he_cap)
return;
pos = skb_put_zero(skb, 2 + sizeof(struct ieee80211_addba_ext_ie)); pos = skb_put_zero(skb, 2 + sizeof(struct ieee80211_addba_ext_ie));
*pos++ = WLAN_EID_ADDBA_EXT; *pos++ = WLAN_EID_ADDBA_EXT;
*pos++ = sizeof(struct ieee80211_addba_ext_ie); *pos++ = sizeof(struct ieee80211_addba_ext_ie);
resp = (struct ieee80211_addba_ext_ie *)pos; resp = (struct ieee80211_addba_ext_ie *)pos;
resp->data = req->data & IEEE80211_ADDBA_EXT_NO_FRAG; resp->data = req->data & IEEE80211_ADDBA_EXT_NO_FRAG;
frag_level = u32_get_bits(req->data,
IEEE80211_ADDBA_EXT_FRAG_LEVEL_MASK);
cap_frag_level = u32_get_bits(he_cap->he_cap_elem.mac_cap_info[0],
IEEE80211_HE_MAC_CAP0_DYNAMIC_FRAG_MASK);
if (frag_level > cap_frag_level)
frag_level = cap_frag_level;
resp->data |= u8_encode_bits(frag_level,
IEEE80211_ADDBA_EXT_FRAG_LEVEL_MASK);
resp->data |= u8_encode_bits(buf_size >> IEEE80211_ADDBA_EXT_BUF_SIZE_SHIFT, resp->data |= u8_encode_bits(buf_size >> IEEE80211_ADDBA_EXT_BUF_SIZE_SHIFT,
IEEE80211_ADDBA_EXT_BUF_SIZE_MASK); IEEE80211_ADDBA_EXT_BUF_SIZE_MASK);
} }
@ -242,7 +223,7 @@ static void ieee80211_send_addba_resp(struct sta_info *sta, u8 *da, u16 tid,
sdata->vif.type == NL80211_IFTYPE_MESH_POINT) sdata->vif.type == NL80211_IFTYPE_MESH_POINT)
memcpy(mgmt->bssid, sdata->vif.addr, ETH_ALEN); memcpy(mgmt->bssid, sdata->vif.addr, ETH_ALEN);
else if (sdata->vif.type == NL80211_IFTYPE_STATION) else if (sdata->vif.type == NL80211_IFTYPE_STATION)
memcpy(mgmt->bssid, sdata->deflink.u.mgd.bssid, ETH_ALEN); memcpy(mgmt->bssid, sdata->vif.cfg.ap_addr, ETH_ALEN);
else if (sdata->vif.type == NL80211_IFTYPE_ADHOC) else if (sdata->vif.type == NL80211_IFTYPE_ADHOC)
memcpy(mgmt->bssid, sdata->u.ibss.bssid, ETH_ALEN); memcpy(mgmt->bssid, sdata->u.ibss.bssid, ETH_ALEN);
@ -297,9 +278,9 @@ void ___ieee80211_start_rx_ba_session(struct sta_info *sta,
} }
if (!sta->sta.deflink.ht_cap.ht_supported && if (!sta->sta.deflink.ht_cap.ht_supported &&
sta->sdata->vif.bss_conf.chandef.chan->band != NL80211_BAND_6GHZ) { !sta->sta.deflink.he_cap.has_he) {
ht_dbg(sta->sdata, ht_dbg(sta->sdata,
"STA %pM erroneously requests BA session on tid %d w/o QoS\n", "STA %pM erroneously requests BA session on tid %d w/o HT\n",
sta->sta.addr, tid); sta->sta.addr, tid);
/* send a response anyway, it's an error case if we get here */ /* send a response anyway, it's an error case if we get here */
goto end; goto end;

View File

@ -82,7 +82,7 @@ static void ieee80211_send_addba_request(struct ieee80211_sub_if_data *sdata,
sdata->vif.type == NL80211_IFTYPE_MESH_POINT) sdata->vif.type == NL80211_IFTYPE_MESH_POINT)
memcpy(mgmt->bssid, sdata->vif.addr, ETH_ALEN); memcpy(mgmt->bssid, sdata->vif.addr, ETH_ALEN);
else if (sdata->vif.type == NL80211_IFTYPE_STATION) else if (sdata->vif.type == NL80211_IFTYPE_STATION)
memcpy(mgmt->bssid, sdata->deflink.u.mgd.bssid, ETH_ALEN); memcpy(mgmt->bssid, sdata->vif.cfg.ap_addr, ETH_ALEN);
else if (sdata->vif.type == NL80211_IFTYPE_ADHOC) else if (sdata->vif.type == NL80211_IFTYPE_ADHOC)
memcpy(mgmt->bssid, sdata->u.ibss.bssid, ETH_ALEN); memcpy(mgmt->bssid, sdata->u.ibss.bssid, ETH_ALEN);

View File

@ -2554,47 +2554,50 @@ static int ieee80211_change_bss(struct wiphy *wiphy,
struct bss_parameters *params) struct bss_parameters *params)
{ {
struct ieee80211_sub_if_data *sdata = IEEE80211_DEV_TO_SUB_IF(dev); struct ieee80211_sub_if_data *sdata = IEEE80211_DEV_TO_SUB_IF(dev);
struct ieee80211_link_data *link;
struct ieee80211_supported_band *sband; struct ieee80211_supported_band *sband;
u32 changed = 0; u32 changed = 0;
if (!sdata_dereference(sdata->deflink.u.ap.beacon, sdata)) link = ieee80211_link_or_deflink(sdata, params->link_id, true);
if (IS_ERR(link))
return PTR_ERR(link);
if (!sdata_dereference(link->u.ap.beacon, sdata))
return -ENOENT; return -ENOENT;
sband = ieee80211_get_sband(sdata); sband = ieee80211_get_link_sband(link);
if (!sband) if (!sband)
return -EINVAL; return -EINVAL;
if (params->use_cts_prot >= 0) { if (params->use_cts_prot >= 0) {
sdata->vif.bss_conf.use_cts_prot = params->use_cts_prot; link->conf->use_cts_prot = params->use_cts_prot;
changed |= BSS_CHANGED_ERP_CTS_PROT; changed |= BSS_CHANGED_ERP_CTS_PROT;
} }
if (params->use_short_preamble >= 0) { if (params->use_short_preamble >= 0) {
sdata->vif.bss_conf.use_short_preamble = link->conf->use_short_preamble = params->use_short_preamble;
params->use_short_preamble;
changed |= BSS_CHANGED_ERP_PREAMBLE; changed |= BSS_CHANGED_ERP_PREAMBLE;
} }
if (!sdata->vif.bss_conf.use_short_slot && if (!link->conf->use_short_slot &&
(sband->band == NL80211_BAND_5GHZ || (sband->band == NL80211_BAND_5GHZ ||
sband->band == NL80211_BAND_6GHZ)) { sband->band == NL80211_BAND_6GHZ)) {
sdata->vif.bss_conf.use_short_slot = true; link->conf->use_short_slot = true;
changed |= BSS_CHANGED_ERP_SLOT; changed |= BSS_CHANGED_ERP_SLOT;
} }
if (params->use_short_slot_time >= 0) { if (params->use_short_slot_time >= 0) {
sdata->vif.bss_conf.use_short_slot = link->conf->use_short_slot = params->use_short_slot_time;
params->use_short_slot_time;
changed |= BSS_CHANGED_ERP_SLOT; changed |= BSS_CHANGED_ERP_SLOT;
} }
if (params->basic_rates) { if (params->basic_rates) {
ieee80211_parse_bitrates(sdata->vif.bss_conf.chandef.width, ieee80211_parse_bitrates(link->conf->chandef.width,
wiphy->bands[sband->band], wiphy->bands[sband->band],
params->basic_rates, params->basic_rates,
params->basic_rates_len, params->basic_rates_len,
&sdata->vif.bss_conf.basic_rates); &link->conf->basic_rates);
changed |= BSS_CHANGED_BASIC_RATES; changed |= BSS_CHANGED_BASIC_RATES;
ieee80211_check_rate_mask(&sdata->deflink); ieee80211_check_rate_mask(link);
} }
if (params->ap_isolate >= 0) { if (params->ap_isolate >= 0) {
@ -2606,30 +2609,29 @@ static int ieee80211_change_bss(struct wiphy *wiphy,
} }
if (params->ht_opmode >= 0) { if (params->ht_opmode >= 0) {
sdata->vif.bss_conf.ht_operation_mode = link->conf->ht_operation_mode = (u16)params->ht_opmode;
(u16) params->ht_opmode;
changed |= BSS_CHANGED_HT; changed |= BSS_CHANGED_HT;
} }
if (params->p2p_ctwindow >= 0) { if (params->p2p_ctwindow >= 0) {
sdata->vif.bss_conf.p2p_noa_attr.oppps_ctwindow &= link->conf->p2p_noa_attr.oppps_ctwindow &=
~IEEE80211_P2P_OPPPS_CTWINDOW_MASK; ~IEEE80211_P2P_OPPPS_CTWINDOW_MASK;
sdata->vif.bss_conf.p2p_noa_attr.oppps_ctwindow |= link->conf->p2p_noa_attr.oppps_ctwindow |=
params->p2p_ctwindow & IEEE80211_P2P_OPPPS_CTWINDOW_MASK; params->p2p_ctwindow & IEEE80211_P2P_OPPPS_CTWINDOW_MASK;
changed |= BSS_CHANGED_P2P_PS; changed |= BSS_CHANGED_P2P_PS;
} }
if (params->p2p_opp_ps > 0) { if (params->p2p_opp_ps > 0) {
sdata->vif.bss_conf.p2p_noa_attr.oppps_ctwindow |= link->conf->p2p_noa_attr.oppps_ctwindow |=
IEEE80211_P2P_OPPPS_ENABLE_BIT; IEEE80211_P2P_OPPPS_ENABLE_BIT;
changed |= BSS_CHANGED_P2P_PS; changed |= BSS_CHANGED_P2P_PS;
} else if (params->p2p_opp_ps == 0) { } else if (params->p2p_opp_ps == 0) {
sdata->vif.bss_conf.p2p_noa_attr.oppps_ctwindow &= link->conf->p2p_noa_attr.oppps_ctwindow &=
~IEEE80211_P2P_OPPPS_ENABLE_BIT; ~IEEE80211_P2P_OPPPS_ENABLE_BIT;
changed |= BSS_CHANGED_P2P_PS; changed |= BSS_CHANGED_P2P_PS;
} }
ieee80211_link_info_change_notify(sdata, &sdata->deflink, changed); ieee80211_link_info_change_notify(sdata, link, changed);
return 0; return 0;
} }
@ -4338,9 +4340,6 @@ static int ieee80211_get_txq_stats(struct wiphy *wiphy,
struct ieee80211_sub_if_data *sdata; struct ieee80211_sub_if_data *sdata;
int ret = 0; int ret = 0;
if (!local->ops->wake_tx_queue)
return 1;
spin_lock_bh(&local->fq.lock); spin_lock_bh(&local->fq.lock);
rcu_read_lock(); rcu_read_lock();

View File

@ -663,9 +663,7 @@ void debugfs_hw_add(struct ieee80211_local *local)
DEBUGFS_ADD_MODE(force_tx_status, 0600); DEBUGFS_ADD_MODE(force_tx_status, 0600);
DEBUGFS_ADD_MODE(aql_enable, 0600); DEBUGFS_ADD_MODE(aql_enable, 0600);
DEBUGFS_ADD(aql_pending); DEBUGFS_ADD(aql_pending);
DEBUGFS_ADD_MODE(aqm, 0600);
if (local->ops->wake_tx_queue)
DEBUGFS_ADD_MODE(aqm, 0600);
DEBUGFS_ADD_MODE(airtime_flags, 0600); DEBUGFS_ADD_MODE(airtime_flags, 0600);

View File

@ -677,8 +677,7 @@ static void add_common_files(struct ieee80211_sub_if_data *sdata)
DEBUGFS_ADD(rc_rateidx_vht_mcs_mask_5ghz); DEBUGFS_ADD(rc_rateidx_vht_mcs_mask_5ghz);
DEBUGFS_ADD(hw_queues); DEBUGFS_ADD(hw_queues);
if (sdata->local->ops->wake_tx_queue && if (sdata->vif.type != NL80211_IFTYPE_P2P_DEVICE &&
sdata->vif.type != NL80211_IFTYPE_P2P_DEVICE &&
sdata->vif.type != NL80211_IFTYPE_NAN) sdata->vif.type != NL80211_IFTYPE_NAN)
DEBUGFS_ADD(aqm); DEBUGFS_ADD(aqm);
} }

View File

@ -5,7 +5,7 @@
* Copyright 2007 Johannes Berg <johannes@sipsolutions.net> * Copyright 2007 Johannes Berg <johannes@sipsolutions.net>
* Copyright 2013-2014 Intel Mobile Communications GmbH * Copyright 2013-2014 Intel Mobile Communications GmbH
* Copyright(c) 2016 Intel Deutschland GmbH * Copyright(c) 2016 Intel Deutschland GmbH
* Copyright (C) 2018 - 2021 Intel Corporation * Copyright (C) 2018 - 2022 Intel Corporation
*/ */
#include <linux/debugfs.h> #include <linux/debugfs.h>
@ -435,8 +435,29 @@ static ssize_t sta_agg_status_write(struct file *file, const char __user *userbu
} }
STA_OPS_RW(agg_status); STA_OPS_RW(agg_status);
static ssize_t sta_ht_capa_read(struct file *file, char __user *userbuf, /* link sta attributes */
size_t count, loff_t *ppos) #define LINK_STA_OPS(name) \
static const struct file_operations link_sta_ ##name## _ops = { \
.read = link_sta_##name##_read, \
.open = simple_open, \
.llseek = generic_file_llseek, \
}
static ssize_t link_sta_addr_read(struct file *file, char __user *userbuf,
size_t count, loff_t *ppos)
{
struct link_sta_info *link_sta = file->private_data;
u8 mac[3 * ETH_ALEN + 1];
snprintf(mac, sizeof(mac), "%pM\n", link_sta->pub->addr);
return simple_read_from_buffer(userbuf, count, ppos, mac, 3 * ETH_ALEN);
}
LINK_STA_OPS(addr);
static ssize_t link_sta_ht_capa_read(struct file *file, char __user *userbuf,
size_t count, loff_t *ppos)
{ {
#define PRINT_HT_CAP(_cond, _str) \ #define PRINT_HT_CAP(_cond, _str) \
do { \ do { \
@ -446,8 +467,8 @@ static ssize_t sta_ht_capa_read(struct file *file, char __user *userbuf,
char *buf, *p; char *buf, *p;
int i; int i;
ssize_t bufsz = 512; ssize_t bufsz = 512;
struct sta_info *sta = file->private_data; struct link_sta_info *link_sta = file->private_data;
struct ieee80211_sta_ht_cap *htc = &sta->sta.deflink.ht_cap; struct ieee80211_sta_ht_cap *htc = &link_sta->pub->ht_cap;
ssize_t ret; ssize_t ret;
buf = kzalloc(bufsz, GFP_KERNEL); buf = kzalloc(bufsz, GFP_KERNEL);
@ -524,14 +545,14 @@ static ssize_t sta_ht_capa_read(struct file *file, char __user *userbuf,
kfree(buf); kfree(buf);
return ret; return ret;
} }
STA_OPS(ht_capa); LINK_STA_OPS(ht_capa);
static ssize_t sta_vht_capa_read(struct file *file, char __user *userbuf, static ssize_t link_sta_vht_capa_read(struct file *file, char __user *userbuf,
size_t count, loff_t *ppos) size_t count, loff_t *ppos)
{ {
char *buf, *p; char *buf, *p;
struct sta_info *sta = file->private_data; struct link_sta_info *link_sta = file->private_data;
struct ieee80211_sta_vht_cap *vhtc = &sta->sta.deflink.vht_cap; struct ieee80211_sta_vht_cap *vhtc = &link_sta->pub->vht_cap;
ssize_t ret; ssize_t ret;
ssize_t bufsz = 512; ssize_t bufsz = 512;
@ -638,15 +659,15 @@ static ssize_t sta_vht_capa_read(struct file *file, char __user *userbuf,
kfree(buf); kfree(buf);
return ret; return ret;
} }
STA_OPS(vht_capa); LINK_STA_OPS(vht_capa);
static ssize_t sta_he_capa_read(struct file *file, char __user *userbuf, static ssize_t link_sta_he_capa_read(struct file *file, char __user *userbuf,
size_t count, loff_t *ppos) size_t count, loff_t *ppos)
{ {
char *buf, *p; char *buf, *p;
size_t buf_sz = PAGE_SIZE; size_t buf_sz = PAGE_SIZE;
struct sta_info *sta = file->private_data; struct link_sta_info *link_sta = file->private_data;
struct ieee80211_sta_he_cap *hec = &sta->sta.deflink.he_cap; struct ieee80211_sta_he_cap *hec = &link_sta->pub->he_cap;
struct ieee80211_he_mcs_nss_supp *nss = &hec->he_mcs_nss_supp; struct ieee80211_he_mcs_nss_supp *nss = &hec->he_mcs_nss_supp;
u8 ppe_size; u8 ppe_size;
u8 *cap; u8 *cap;
@ -1011,7 +1032,7 @@ out:
kfree(buf); kfree(buf);
return ret; return ret;
} }
STA_OPS(he_capa); LINK_STA_OPS(he_capa);
#define DEBUGFS_ADD(name) \ #define DEBUGFS_ADD(name) \
debugfs_create_file(#name, 0400, \ debugfs_create_file(#name, 0400, \
@ -1048,18 +1069,11 @@ void ieee80211_sta_debugfs_add(struct sta_info *sta)
DEBUGFS_ADD(num_ps_buf_frames); DEBUGFS_ADD(num_ps_buf_frames);
DEBUGFS_ADD(last_seq_ctrl); DEBUGFS_ADD(last_seq_ctrl);
DEBUGFS_ADD(agg_status); DEBUGFS_ADD(agg_status);
DEBUGFS_ADD(ht_capa); /* FIXME: Kept here as the statistics are only done on the deflink */
DEBUGFS_ADD(vht_capa);
DEBUGFS_ADD(he_capa);
DEBUGFS_ADD_COUNTER(rx_duplicates, deflink.rx_stats.num_duplicates);
DEBUGFS_ADD_COUNTER(rx_fragments, deflink.rx_stats.fragments);
DEBUGFS_ADD_COUNTER(tx_filtered, deflink.status_stats.filtered); DEBUGFS_ADD_COUNTER(tx_filtered, deflink.status_stats.filtered);
if (local->ops->wake_tx_queue) { DEBUGFS_ADD(aqm);
DEBUGFS_ADD(aqm); DEBUGFS_ADD(airtime);
DEBUGFS_ADD(airtime);
}
if (wiphy_ext_feature_isset(local->hw.wiphy, if (wiphy_ext_feature_isset(local->hw.wiphy,
NL80211_EXT_FEATURE_AQL)) NL80211_EXT_FEATURE_AQL))
@ -1076,3 +1090,85 @@ void ieee80211_sta_debugfs_remove(struct sta_info *sta)
debugfs_remove_recursive(sta->debugfs_dir); debugfs_remove_recursive(sta->debugfs_dir);
sta->debugfs_dir = NULL; sta->debugfs_dir = NULL;
} }
#undef DEBUGFS_ADD
#undef DEBUGFS_ADD_COUNTER
#define DEBUGFS_ADD(name) \
debugfs_create_file(#name, 0400, \
link_sta->debugfs_dir, link_sta, &link_sta_ ##name## _ops)
#define DEBUGFS_ADD_COUNTER(name, field) \
debugfs_create_ulong(#name, 0400, link_sta->debugfs_dir, &link_sta->field)
void ieee80211_link_sta_debugfs_add(struct link_sta_info *link_sta)
{
if (WARN_ON(!link_sta->sta->debugfs_dir))
return;
/* For non-MLO, leave the files in the main directory. */
if (link_sta->sta->sta.valid_links) {
char link_dir_name[10];
snprintf(link_dir_name, sizeof(link_dir_name),
"link-%d", link_sta->link_id);
link_sta->debugfs_dir =
debugfs_create_dir(link_dir_name,
link_sta->sta->debugfs_dir);
DEBUGFS_ADD(addr);
} else {
if (WARN_ON(link_sta != &link_sta->sta->deflink))
return;
link_sta->debugfs_dir = link_sta->sta->debugfs_dir;
}
DEBUGFS_ADD(ht_capa);
DEBUGFS_ADD(vht_capa);
DEBUGFS_ADD(he_capa);
DEBUGFS_ADD_COUNTER(rx_duplicates, rx_stats.num_duplicates);
DEBUGFS_ADD_COUNTER(rx_fragments, rx_stats.fragments);
}
void ieee80211_link_sta_debugfs_remove(struct link_sta_info *link_sta)
{
if (!link_sta->debugfs_dir || !link_sta->sta->debugfs_dir) {
link_sta->debugfs_dir = NULL;
return;
}
if (link_sta->debugfs_dir == link_sta->sta->debugfs_dir) {
WARN_ON(link_sta != &link_sta->sta->deflink);
link_sta->sta->debugfs_dir = NULL;
return;
}
debugfs_remove_recursive(link_sta->debugfs_dir);
link_sta->debugfs_dir = NULL;
}
void ieee80211_link_sta_debugfs_drv_add(struct link_sta_info *link_sta)
{
if (WARN_ON(!link_sta->debugfs_dir))
return;
drv_link_sta_add_debugfs(link_sta->sta->local, link_sta->sta->sdata,
link_sta->pub, link_sta->debugfs_dir);
}
void ieee80211_link_sta_debugfs_drv_remove(struct link_sta_info *link_sta)
{
if (!link_sta->debugfs_dir)
return;
if (WARN_ON(link_sta->debugfs_dir == link_sta->sta->debugfs_dir))
return;
/* Recreate the directory excluding the driver data */
debugfs_remove_recursive(link_sta->debugfs_dir);
link_sta->debugfs_dir = NULL;
ieee80211_link_sta_debugfs_add(link_sta);
}

View File

@ -7,9 +7,21 @@
#ifdef CONFIG_MAC80211_DEBUGFS #ifdef CONFIG_MAC80211_DEBUGFS
void ieee80211_sta_debugfs_add(struct sta_info *sta); void ieee80211_sta_debugfs_add(struct sta_info *sta);
void ieee80211_sta_debugfs_remove(struct sta_info *sta); void ieee80211_sta_debugfs_remove(struct sta_info *sta);
void ieee80211_link_sta_debugfs_add(struct link_sta_info *link_sta);
void ieee80211_link_sta_debugfs_remove(struct link_sta_info *link_sta);
void ieee80211_link_sta_debugfs_drv_add(struct link_sta_info *link_sta);
void ieee80211_link_sta_debugfs_drv_remove(struct link_sta_info *link_sta);
#else #else
static inline void ieee80211_sta_debugfs_add(struct sta_info *sta) {} static inline void ieee80211_sta_debugfs_add(struct sta_info *sta) {}
static inline void ieee80211_sta_debugfs_remove(struct sta_info *sta) {} static inline void ieee80211_sta_debugfs_remove(struct sta_info *sta) {}
static inline void ieee80211_link_sta_debugfs_add(struct link_sta_info *link_sta) {}
static inline void ieee80211_link_sta_debugfs_remove(struct link_sta_info *link_sta) {}
static inline void ieee80211_link_sta_debugfs_drv_add(struct link_sta_info *link_sta) {}
static inline void ieee80211_link_sta_debugfs_drv_remove(struct link_sta_info *link_sta) {}
#endif #endif
#endif /* __MAC80211_DEBUGFS_STA_H */ #endif /* __MAC80211_DEBUGFS_STA_H */

View File

@ -7,6 +7,7 @@
#include "ieee80211_i.h" #include "ieee80211_i.h"
#include "trace.h" #include "trace.h"
#include "driver-ops.h" #include "driver-ops.h"
#include "debugfs_sta.h"
int drv_start(struct ieee80211_local *local) int drv_start(struct ieee80211_local *local)
{ {
@ -497,6 +498,11 @@ int drv_change_sta_links(struct ieee80211_local *local,
struct ieee80211_sta *sta, struct ieee80211_sta *sta,
u16 old_links, u16 new_links) u16 old_links, u16 new_links)
{ {
struct sta_info *info = container_of(sta, struct sta_info, sta);
struct link_sta_info *link_sta;
unsigned long links_to_add;
unsigned long links_to_rem;
unsigned int link_id;
int ret = -EOPNOTSUPP; int ret = -EOPNOTSUPP;
might_sleep(); might_sleep();
@ -510,11 +516,30 @@ int drv_change_sta_links(struct ieee80211_local *local,
if (old_links == new_links) if (old_links == new_links)
return 0; return 0;
links_to_add = ~old_links & new_links;
links_to_rem = old_links & ~new_links;
for_each_set_bit(link_id, &links_to_rem, IEEE80211_MLD_MAX_NUM_LINKS) {
link_sta = rcu_dereference_protected(info->link[link_id],
lockdep_is_held(&local->sta_mtx));
ieee80211_link_sta_debugfs_drv_remove(link_sta);
}
trace_drv_change_sta_links(local, sdata, sta, old_links, new_links); trace_drv_change_sta_links(local, sdata, sta, old_links, new_links);
if (local->ops->change_sta_links) if (local->ops->change_sta_links)
ret = local->ops->change_sta_links(&local->hw, &sdata->vif, sta, ret = local->ops->change_sta_links(&local->hw, &sdata->vif, sta,
old_links, new_links); old_links, new_links);
trace_drv_return_int(local, ret); trace_drv_return_int(local, ret);
return ret; if (ret)
return ret;
for_each_set_bit(link_id, &links_to_add, IEEE80211_MLD_MAX_NUM_LINKS) {
link_sta = rcu_dereference_protected(info->link[link_id],
lockdep_is_held(&local->sta_mtx));
ieee80211_link_sta_debugfs_drv_add(link_sta);
}
return 0;
} }

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